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[mesa.git] / src / gallium / drivers / panfrost / pan_context.c
1 /*
2 * © Copyright 2018 Alyssa Rosenzweig
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 */
24
25 #include <sys/poll.h>
26 #include <errno.h>
27
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
31
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/half_float.h"
38 #include "indices/u_primconvert.h"
39 #include "tgsi/tgsi_parse.h"
40
41 #include "pan_screen.h"
42 #include "pan_blending.h"
43 #include "pan_blend_shaders.h"
44 #include "pan_wallpaper.h"
45
46 #ifdef DUMP_PERFORMANCE_COUNTERS
47 static int performance_counter_number = 0;
48 #endif
49
50 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
51 //#define DRY_RUN
52
53 #define SET_BIT(lval, bit, cond) \
54 if (cond) \
55 lval |= (bit); \
56 else \
57 lval &= ~(bit);
58
59 /* TODO: Sample size, etc */
60
61 /* True for t6XX, false for t8xx. TODO: Run-time settable for automatic
62 * hardware configuration. */
63
64 static bool is_t6xx = false;
65
66 /* If set, we'll require the use of single render-target framebuffer
67 * descriptors (SFBD), for older hardware -- specifically, <T760 hardware, If
68 * false, we'll use the MFBD no matter what. New hardware -does- retain support
69 * for SFBD, and in theory we could flip between them on a per-RT basis, but
70 * there's no real advantage to doing so */
71
72 static bool require_sfbd = false;
73
74 static void
75 panfrost_set_framebuffer_msaa(struct panfrost_context *ctx, bool enabled)
76 {
77 SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_HAS_MSAA, enabled);
78 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_NO_MSAA, !enabled);
79
80 if (require_sfbd) {
81 SET_BIT(ctx->fragment_sfbd.format, MALI_FRAMEBUFFER_MSAA_A | MALI_FRAMEBUFFER_MSAA_B, enabled);
82 } else {
83 SET_BIT(ctx->fragment_rts[0].format, MALI_MFBD_FORMAT_MSAA, enabled);
84
85 SET_BIT(ctx->fragment_mfbd.unk1, (1 << 4) | (1 << 1), enabled);
86
87 /* XXX */
88 ctx->fragment_mfbd.rt_count_2 = enabled ? 4 : 1;
89 }
90 }
91
92 /* AFBC is enabled on a per-resource basis (AFBC enabling is theoretically
93 * indepdent between color buffers and depth/stencil). To enable, we allocate
94 * the AFBC metadata buffer and mark that it is enabled. We do -not- actually
95 * edit the fragment job here. This routine should be called ONCE per
96 * AFBC-compressed buffer, rather than on every frame. */
97
98 static void
99 panfrost_enable_afbc(struct panfrost_context *ctx, struct panfrost_resource *rsrc, bool ds)
100 {
101 if (require_sfbd) {
102 printf("AFBC not supported yet on SFBD\n");
103 assert(0);
104 }
105
106 struct pipe_context *gallium = (struct pipe_context *) ctx;
107 struct panfrost_screen *screen = pan_screen(gallium->screen);
108 /* AFBC metadata is 16 bytes per tile */
109 int tile_w = (rsrc->base.width0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
110 int tile_h = (rsrc->base.height0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
111 int bytes_per_pixel = util_format_get_blocksize(rsrc->base.format);
112 int stride = bytes_per_pixel * rsrc->base.width0; /* TODO: Alignment? */
113
114 stride *= 2; /* TODO: Should this be carried over? */
115 int main_size = stride * rsrc->base.height0;
116 rsrc->bo->afbc_metadata_size = tile_w * tile_h * 16;
117
118 /* Allocate the AFBC slab itself, large enough to hold the above */
119 screen->driver->allocate_slab(screen, &rsrc->bo->afbc_slab,
120 (rsrc->bo->afbc_metadata_size + main_size + 4095) / 4096,
121 true, 0, 0, 0);
122
123 rsrc->bo->has_afbc = true;
124
125 /* Compressed textured reads use a tagged pointer to the metadata */
126
127 rsrc->bo->gpu[0] = rsrc->bo->afbc_slab.gpu | (ds ? 0 : 1);
128 rsrc->bo->cpu[0] = rsrc->bo->afbc_slab.cpu;
129 }
130
131 static void
132 panfrost_enable_checksum(struct panfrost_context *ctx, struct panfrost_resource *rsrc)
133 {
134 struct pipe_context *gallium = (struct pipe_context *) ctx;
135 struct panfrost_screen *screen = pan_screen(gallium->screen);
136 int tile_w = (rsrc->base.width0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
137 int tile_h = (rsrc->base.height0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
138
139 /* 8 byte checksum per tile */
140 rsrc->bo->checksum_stride = tile_w * 8;
141 int pages = (((rsrc->bo->checksum_stride * tile_h) + 4095) / 4096);
142 screen->driver->allocate_slab(screen, &rsrc->bo->checksum_slab, pages, false, 0, 0, 0);
143
144 rsrc->bo->has_checksum = true;
145 }
146
147 /* ..by contrast, this routine runs for every FRAGMENT job, but does no
148 * allocation. AFBC is enabled on a per-surface basis */
149
150 static void
151 panfrost_set_fragment_afbc(struct panfrost_context *ctx)
152 {
153 for (int cb = 0; cb < ctx->pipe_framebuffer.nr_cbufs; ++cb) {
154 struct panfrost_resource *rsrc = (struct panfrost_resource *) ctx->pipe_framebuffer.cbufs[cb]->texture;
155
156 /* Non-AFBC is the default */
157 if (!rsrc->bo->has_afbc)
158 continue;
159
160 if (require_sfbd) {
161 fprintf(stderr, "Color AFBC not supported on SFBD\n");
162 assert(0);
163 }
164
165 /* Enable AFBC for the render target */
166 ctx->fragment_rts[0].afbc.metadata = rsrc->bo->afbc_slab.gpu;
167 ctx->fragment_rts[0].afbc.stride = 0;
168 ctx->fragment_rts[0].afbc.unk = 0x30009;
169
170 ctx->fragment_rts[0].format |= MALI_MFBD_FORMAT_AFBC;
171
172 /* Point rendering to our special framebuffer */
173 ctx->fragment_rts[0].framebuffer = rsrc->bo->afbc_slab.gpu + rsrc->bo->afbc_metadata_size;
174
175 /* WAT? Stride is diff from the scanout case */
176 ctx->fragment_rts[0].framebuffer_stride = ctx->pipe_framebuffer.width * 2 * 4;
177 }
178
179 /* Enable depth/stencil AFBC for the framebuffer (not the render target) */
180 if (ctx->pipe_framebuffer.zsbuf) {
181 struct panfrost_resource *rsrc = (struct panfrost_resource *) ctx->pipe_framebuffer.zsbuf->texture;
182
183 if (rsrc->bo->has_afbc) {
184 if (require_sfbd) {
185 fprintf(stderr, "Depth AFBC not supported on SFBD\n");
186 assert(0);
187 }
188
189 ctx->fragment_mfbd.unk3 |= MALI_MFBD_EXTRA;
190
191 ctx->fragment_extra.ds_afbc.depth_stencil_afbc_metadata = rsrc->bo->afbc_slab.gpu;
192 ctx->fragment_extra.ds_afbc.depth_stencil_afbc_stride = 0;
193
194 ctx->fragment_extra.ds_afbc.depth_stencil = rsrc->bo->afbc_slab.gpu + rsrc->bo->afbc_metadata_size;
195
196 ctx->fragment_extra.ds_afbc.zero1 = 0x10009;
197 ctx->fragment_extra.ds_afbc.padding = 0x1000;
198
199 ctx->fragment_extra.unk = 0x435; /* General 0x400 in all unks. 0x5 for depth/stencil. 0x10 for AFBC encoded depth stencil. Unclear where the 0x20 is from */
200
201 ctx->fragment_mfbd.unk3 |= 0x400;
202 }
203 }
204
205 /* For the special case of a depth-only FBO, we need to attach a dummy render target */
206
207 if (ctx->pipe_framebuffer.nr_cbufs == 0) {
208 if (require_sfbd) {
209 fprintf(stderr, "Depth-only FBO not supported on SFBD\n");
210 assert(0);
211 }
212
213 ctx->fragment_rts[0].format = 0x80008000;
214 ctx->fragment_rts[0].framebuffer = 0;
215 ctx->fragment_rts[0].framebuffer_stride = 0;
216 }
217 }
218
219 /* Framebuffer descriptor */
220
221 static void
222 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer *fb, int w, int h)
223 {
224 fb->width = MALI_POSITIVE(w);
225 fb->height = MALI_POSITIVE(h);
226
227 /* No idea why this is needed, but it's how resolution_check is
228 * calculated. It's not clear to us yet why the hardware wants this.
229 * The formula itself was discovered mostly by manual bruteforce and
230 * aggressive algebraic simplification. */
231
232 fb->resolution_check = ((w + h) / 3) << 4;
233 }
234
235 static struct mali_single_framebuffer
236 panfrost_emit_sfbd(struct panfrost_context *ctx)
237 {
238 struct mali_single_framebuffer framebuffer = {
239 .unknown2 = 0x1f,
240 .format = 0x30000000,
241 .clear_flags = 0x1000,
242 .unknown_address_0 = ctx->scratchpad.gpu,
243 .unknown_address_1 = ctx->misc_0.gpu,
244 .unknown_address_2 = ctx->misc_0.gpu + 40960,
245 .tiler_flags = 0xf0,
246 .tiler_heap_free = ctx->tiler_heap.gpu,
247 .tiler_heap_end = ctx->tiler_heap.gpu + ctx->tiler_heap.size,
248 };
249
250 panfrost_set_framebuffer_resolution(&framebuffer, ctx->pipe_framebuffer.width, ctx->pipe_framebuffer.height);
251
252 return framebuffer;
253 }
254
255 static struct bifrost_framebuffer
256 panfrost_emit_mfbd(struct panfrost_context *ctx)
257 {
258 struct bifrost_framebuffer framebuffer = {
259 .tiler_meta = 0xf00000c600,
260
261 .width1 = MALI_POSITIVE(ctx->pipe_framebuffer.width),
262 .height1 = MALI_POSITIVE(ctx->pipe_framebuffer.height),
263 .width2 = MALI_POSITIVE(ctx->pipe_framebuffer.width),
264 .height2 = MALI_POSITIVE(ctx->pipe_framebuffer.height),
265
266 .unk1 = 0x1080,
267
268 /* TODO: MRT */
269 .rt_count_1 = MALI_POSITIVE(1),
270 .rt_count_2 = 4,
271
272 .unknown2 = 0x1f,
273
274 /* Presumably corresponds to unknown_address_X of SFBD */
275 .scratchpad = ctx->scratchpad.gpu,
276 .tiler_scratch_start = ctx->misc_0.gpu,
277 .tiler_scratch_middle = ctx->misc_0.gpu + /*ctx->misc_0.size*/40960, /* Size depends on the size of the framebuffer and the number of vertices */
278
279 .tiler_heap_start = ctx->tiler_heap.gpu,
280 .tiler_heap_end = ctx->tiler_heap.gpu + ctx->tiler_heap.size,
281 };
282
283 return framebuffer;
284 }
285
286 /* Are we currently rendering to the screen (rather than an FBO)? */
287
288 static bool
289 panfrost_is_scanout(struct panfrost_context *ctx)
290 {
291 /* If there is no color buffer, it's an FBO */
292 if (!ctx->pipe_framebuffer.nr_cbufs)
293 return false;
294
295 /* If we're too early that no framebuffer was sent, it's scanout */
296 if (!ctx->pipe_framebuffer.cbufs[0])
297 return true;
298
299 return ctx->pipe_framebuffer.cbufs[0]->texture->bind & PIPE_BIND_DISPLAY_TARGET ||
300 ctx->pipe_framebuffer.cbufs[0]->texture->bind & PIPE_BIND_SCANOUT ||
301 ctx->pipe_framebuffer.cbufs[0]->texture->bind & PIPE_BIND_SHARED;
302 }
303
304 /* The above function is for generalised fbd emission, used in both fragment as
305 * well as vertex/tiler payloads. This payload is specific to fragment
306 * payloads. */
307
308 static void
309 panfrost_new_frag_framebuffer(struct panfrost_context *ctx)
310 {
311 mali_ptr framebuffer;
312 int stride;
313
314 if (ctx->pipe_framebuffer.nr_cbufs > 0) {
315 framebuffer = ((struct panfrost_resource *) ctx->pipe_framebuffer.cbufs[0]->texture)->bo->gpu[0];
316 stride = util_format_get_stride(ctx->pipe_framebuffer.cbufs[0]->format, ctx->pipe_framebuffer.width);
317 } else {
318 /* Depth-only framebuffer -> dummy RT */
319 framebuffer = 0;
320 stride = 0;
321 }
322
323 /* The default is upside down from OpenGL's perspective. */
324 if (panfrost_is_scanout(ctx)) {
325 framebuffer += stride * (ctx->pipe_framebuffer.height - 1);
326 stride = -stride;
327 }
328
329 if (require_sfbd) {
330 struct mali_single_framebuffer fb = panfrost_emit_sfbd(ctx);
331
332 fb.framebuffer = framebuffer;
333 fb.stride = stride;
334
335 fb.format = 0xb84e0281; /* RGB32, no MSAA */
336 memcpy(&ctx->fragment_sfbd, &fb, sizeof(fb));
337 } else {
338 struct bifrost_framebuffer fb = panfrost_emit_mfbd(ctx);
339
340 /* XXX: MRT case */
341 fb.rt_count_2 = 1;
342 fb.unk3 = 0x100;
343
344 struct bifrost_render_target rt = {
345 .unk1 = 0x4000000,
346 .format = 0x860a8899, /* RGBA32, no MSAA */
347 .framebuffer = framebuffer,
348 .framebuffer_stride = (stride / 16) & 0xfffffff,
349 };
350
351 memcpy(&ctx->fragment_rts[0], &rt, sizeof(rt));
352
353 memset(&ctx->fragment_extra, 0, sizeof(ctx->fragment_extra));
354 memcpy(&ctx->fragment_mfbd, &fb, sizeof(fb));
355 }
356 }
357
358 /* Maps float 0.0-1.0 to int 0x00-0xFF */
359 static uint8_t
360 normalised_float_to_u8(float f)
361 {
362 return (uint8_t) (int) (f * 255.0f);
363 }
364
365 static void
366 panfrost_clear_sfbd(struct panfrost_context *ctx,
367 bool clear_color,
368 bool clear_depth,
369 bool clear_stencil,
370 uint32_t packed_color,
371 double depth, unsigned stencil
372 )
373 {
374 struct mali_single_framebuffer *sfbd = &ctx->fragment_sfbd;
375
376 if (clear_color) {
377 sfbd->clear_color_1 = packed_color;
378 sfbd->clear_color_2 = packed_color;
379 sfbd->clear_color_3 = packed_color;
380 sfbd->clear_color_4 = packed_color;
381 }
382
383 if (clear_depth) {
384 sfbd->clear_depth_1 = depth;
385 sfbd->clear_depth_2 = depth;
386 sfbd->clear_depth_3 = depth;
387 sfbd->clear_depth_4 = depth;
388 }
389
390 if (clear_stencil) {
391 sfbd->clear_stencil = stencil;
392 }
393
394 /* Setup buffers */
395
396 if (clear_depth) {
397 sfbd->depth_buffer = ctx->depth_stencil_buffer.gpu;
398 sfbd->depth_buffer_enable = MALI_DEPTH_STENCIL_ENABLE;
399 }
400
401 if (clear_stencil) {
402 sfbd->stencil_buffer = ctx->depth_stencil_buffer.gpu;
403 sfbd->stencil_buffer_enable = MALI_DEPTH_STENCIL_ENABLE;
404 }
405
406 /* Set flags based on what has been cleared, for the SFBD case */
407 /* XXX: What do these flags mean? */
408 int clear_flags = 0x101100;
409
410 if (clear_color && clear_depth && clear_stencil) {
411 /* On a tiler like this, it's fastest to clear all three buffers at once */
412
413 clear_flags |= MALI_CLEAR_FAST;
414 } else {
415 clear_flags |= MALI_CLEAR_SLOW;
416
417 if (clear_stencil)
418 clear_flags |= MALI_CLEAR_SLOW_STENCIL;
419 }
420
421 sfbd->clear_flags = clear_flags;
422 }
423
424 static void
425 panfrost_clear_mfbd(struct panfrost_context *ctx,
426 bool clear_color,
427 bool clear_depth,
428 bool clear_stencil,
429 uint32_t packed_color,
430 double depth, unsigned stencil
431 )
432 {
433 struct bifrost_render_target *buffer_color = &ctx->fragment_rts[0];
434 struct bifrost_framebuffer *buffer_ds = &ctx->fragment_mfbd;
435
436 if (clear_color) {
437 buffer_color->clear_color_1 = packed_color;
438 buffer_color->clear_color_2 = packed_color;
439 buffer_color->clear_color_3 = packed_color;
440 buffer_color->clear_color_4 = packed_color;
441 }
442
443 if (clear_depth) {
444 buffer_ds->clear_depth = depth;
445 }
446
447 if (clear_stencil) {
448 buffer_ds->clear_stencil = stencil;
449 }
450
451 if (clear_depth || clear_stencil) {
452 /* Setup combined 24/8 depth/stencil */
453 ctx->fragment_mfbd.unk3 |= MALI_MFBD_EXTRA;
454 //ctx->fragment_extra.unk = /*0x405*/0x404;
455 ctx->fragment_extra.unk = 0x405;
456 ctx->fragment_extra.ds_linear.depth = ctx->depth_stencil_buffer.gpu;
457 ctx->fragment_extra.ds_linear.depth_stride = ctx->pipe_framebuffer.width * 4;
458 }
459 }
460
461 static void
462 panfrost_clear(
463 struct pipe_context *pipe,
464 unsigned buffers,
465 const union pipe_color_union *color,
466 double depth, unsigned stencil)
467 {
468 struct panfrost_context *ctx = pan_context(pipe);
469
470 if (!color) {
471 printf("Warning: clear color null?\n");
472 return;
473 }
474
475 /* Save settings for FBO switch */
476 ctx->last_clear.buffers = buffers;
477 ctx->last_clear.color = color;
478 ctx->last_clear.depth = depth;
479 ctx->last_clear.depth = depth;
480
481 bool clear_color = buffers & PIPE_CLEAR_COLOR;
482 bool clear_depth = buffers & PIPE_CLEAR_DEPTH;
483 bool clear_stencil = buffers & PIPE_CLEAR_STENCIL;
484
485 /* Remember that we've done something */
486 ctx->frame_cleared = true;
487
488 /* Alpha clear only meaningful without alpha channel */
489 bool has_alpha = ctx->pipe_framebuffer.nr_cbufs && util_format_has_alpha(ctx->pipe_framebuffer.cbufs[0]->format);
490 float clear_alpha = has_alpha ? color->f[3] : 1.0f;
491
492 uint32_t packed_color =
493 (normalised_float_to_u8(clear_alpha) << 24) |
494 (normalised_float_to_u8(color->f[2]) << 16) |
495 (normalised_float_to_u8(color->f[1]) << 8) |
496 (normalised_float_to_u8(color->f[0]) << 0);
497
498 if (require_sfbd) {
499 panfrost_clear_sfbd(ctx, clear_color, clear_depth, clear_stencil, packed_color, depth, stencil);
500 } else {
501 panfrost_clear_mfbd(ctx, clear_color, clear_depth, clear_stencil, packed_color, depth, stencil);
502 }
503 }
504
505 static mali_ptr
506 panfrost_attach_vt_mfbd(struct panfrost_context *ctx)
507 {
508 /* MFBD needs a sequential semi-render target upload, but what exactly this is, is beyond me for now */
509 struct bifrost_render_target rts_list[] = {
510 {
511 .chunknown = {
512 .unk = 0x30005,
513 },
514 .framebuffer = ctx->misc_0.gpu,
515 .zero2 = 0x3,
516 },
517 };
518
519 /* Allocate memory for the three components */
520 int size = 1024 + sizeof(ctx->vt_framebuffer_mfbd) + sizeof(rts_list);
521 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, size);
522
523 /* Opaque 1024-block */
524 rts_list[0].chunknown.pointer = transfer.gpu;
525
526 memcpy(transfer.cpu + 1024, &ctx->vt_framebuffer_mfbd, sizeof(ctx->vt_framebuffer_mfbd));
527 memcpy(transfer.cpu + 1024 + sizeof(ctx->vt_framebuffer_mfbd), rts_list, sizeof(rts_list));
528
529 return (transfer.gpu + 1024) | MALI_MFBD;
530 }
531
532 static mali_ptr
533 panfrost_attach_vt_sfbd(struct panfrost_context *ctx)
534 {
535 return panfrost_upload_transient(ctx, &ctx->vt_framebuffer_sfbd, sizeof(ctx->vt_framebuffer_sfbd)) | MALI_SFBD;
536 }
537
538 static void
539 panfrost_attach_vt_framebuffer(struct panfrost_context *ctx)
540 {
541 mali_ptr framebuffer = require_sfbd ?
542 panfrost_attach_vt_sfbd(ctx) :
543 panfrost_attach_vt_mfbd(ctx);
544
545 ctx->payload_vertex.postfix.framebuffer = framebuffer;
546 ctx->payload_tiler.postfix.framebuffer = framebuffer;
547 }
548
549 static void
550 panfrost_viewport(struct panfrost_context *ctx,
551 float depth_clip_near,
552 float depth_clip_far,
553 int viewport_x0, int viewport_y0,
554 int viewport_x1, int viewport_y1)
555 {
556 /* Clip bounds are encoded as floats. The viewport itself is encoded as
557 * (somewhat) asymmetric ints. */
558
559 struct mali_viewport ret = {
560 .clip_minx = viewport_x0,
561 .clip_miny = viewport_y0,
562 .clip_maxx = viewport_x1,
563 .clip_maxy = viewport_x1,
564
565 .clip_minz = depth_clip_near,
566 .clip_maxz = depth_clip_far,
567
568 .viewport0 = { viewport_x0, viewport_y0 },
569 .viewport1 = { MALI_POSITIVE(viewport_x1), MALI_POSITIVE(viewport_y1) },
570 };
571
572 memcpy(ctx->viewport, &ret, sizeof(ret));
573 }
574
575 /* Reset per-frame context, called on context initialisation as well as after
576 * flushing a frame */
577
578 static void
579 panfrost_invalidate_frame(struct panfrost_context *ctx)
580 {
581 unsigned transient_count = ctx->transient_pools[ctx->cmdstream_i].entry_index*ctx->transient_pools[0].entry_size + ctx->transient_pools[ctx->cmdstream_i].entry_offset;
582 printf("Uploaded transient %d bytes\n", transient_count);
583
584 /* Rotate cmdstream */
585 if ((++ctx->cmdstream_i) == (sizeof(ctx->transient_pools) / sizeof(ctx->transient_pools[0])))
586 ctx->cmdstream_i = 0;
587
588 if (require_sfbd)
589 ctx->vt_framebuffer_sfbd = panfrost_emit_sfbd(ctx);
590 else
591 ctx->vt_framebuffer_mfbd = panfrost_emit_mfbd(ctx);
592
593 panfrost_new_frag_framebuffer(ctx);
594
595 /* Reset varyings allocated */
596 ctx->varying_height = 0;
597
598 /* The transient cmdstream is dirty every frame; the only bits worth preserving
599 * (textures, shaders, etc) are in other buffers anyways */
600
601 ctx->transient_pools[ctx->cmdstream_i].entry_index = 0;
602 ctx->transient_pools[ctx->cmdstream_i].entry_offset = 0;
603
604 /* Regenerate payloads */
605 panfrost_attach_vt_framebuffer(ctx);
606
607 if (ctx->rasterizer)
608 ctx->dirty |= PAN_DIRTY_RASTERIZER;
609
610 /* XXX */
611 ctx->dirty |= PAN_DIRTY_SAMPLERS | PAN_DIRTY_TEXTURES;
612 }
613
614 /* In practice, every field of these payloads should be configurable
615 * arbitrarily, which means these functions are basically catch-all's for
616 * as-of-yet unwavering unknowns */
617
618 static void
619 panfrost_emit_vertex_payload(struct panfrost_context *ctx)
620 {
621 struct midgard_payload_vertex_tiler payload = {
622 .prefix = {
623 .workgroups_z_shift = 32,
624 .workgroups_x_shift_2 = 0x2,
625 .workgroups_x_shift_3 = 0x5,
626 },
627 .gl_enables = 0x4 | (is_t6xx ? 0 : 0x2),
628 };
629
630 memcpy(&ctx->payload_vertex, &payload, sizeof(payload));
631 }
632
633 static void
634 panfrost_emit_tiler_payload(struct panfrost_context *ctx)
635 {
636 struct midgard_payload_vertex_tiler payload = {
637 .prefix = {
638 .workgroups_z_shift = 32,
639 .workgroups_x_shift_2 = 0x2,
640 .workgroups_x_shift_3 = 0x6,
641
642 .zero1 = 0xffff, /* Why is this only seen on test-quad-textured? */
643 },
644 };
645
646 /* Reserve the viewport */
647 struct panfrost_transfer t = panfrost_allocate_chunk(ctx, sizeof(struct mali_viewport), HEAP_DESCRIPTOR);
648 ctx->viewport = (struct mali_viewport *) t.cpu;
649 payload.postfix.viewport = t.gpu;
650
651 memcpy(&ctx->payload_tiler, &payload, sizeof(payload));
652 }
653
654 static unsigned
655 translate_tex_wrap(enum pipe_tex_wrap w)
656 {
657 switch (w) {
658 case PIPE_TEX_WRAP_REPEAT:
659 return MALI_WRAP_REPEAT;
660
661 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
662 return MALI_WRAP_CLAMP_TO_EDGE;
663
664 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
665 return MALI_WRAP_CLAMP_TO_BORDER;
666
667 case PIPE_TEX_WRAP_MIRROR_REPEAT:
668 return MALI_WRAP_MIRRORED_REPEAT;
669
670 default:
671 assert(0);
672 return 0;
673 }
674 }
675
676 static unsigned
677 translate_tex_filter(enum pipe_tex_filter f)
678 {
679 switch (f) {
680 case PIPE_TEX_FILTER_NEAREST:
681 return MALI_NEAREST;
682
683 case PIPE_TEX_FILTER_LINEAR:
684 return MALI_LINEAR;
685
686 default:
687 assert(0);
688 return 0;
689 }
690 }
691
692 static unsigned
693 translate_mip_filter(enum pipe_tex_mipfilter f)
694 {
695 return (f == PIPE_TEX_MIPFILTER_LINEAR) ? MALI_MIP_LINEAR : 0;
696 }
697
698 static unsigned
699 panfrost_translate_compare_func(enum pipe_compare_func in)
700 {
701 switch (in) {
702 case PIPE_FUNC_NEVER:
703 return MALI_FUNC_NEVER;
704
705 case PIPE_FUNC_LESS:
706 return MALI_FUNC_LESS;
707
708 case PIPE_FUNC_EQUAL:
709 return MALI_FUNC_EQUAL;
710
711 case PIPE_FUNC_LEQUAL:
712 return MALI_FUNC_LEQUAL;
713
714 case PIPE_FUNC_GREATER:
715 return MALI_FUNC_GREATER;
716
717 case PIPE_FUNC_NOTEQUAL:
718 return MALI_FUNC_NOTEQUAL;
719
720 case PIPE_FUNC_GEQUAL:
721 return MALI_FUNC_GEQUAL;
722
723 case PIPE_FUNC_ALWAYS:
724 return MALI_FUNC_ALWAYS;
725 }
726
727 assert (0);
728 return 0; /* Unreachable */
729 }
730
731 static unsigned
732 panfrost_translate_alt_compare_func(enum pipe_compare_func in)
733 {
734 switch (in) {
735 case PIPE_FUNC_NEVER:
736 return MALI_ALT_FUNC_NEVER;
737
738 case PIPE_FUNC_LESS:
739 return MALI_ALT_FUNC_LESS;
740
741 case PIPE_FUNC_EQUAL:
742 return MALI_ALT_FUNC_EQUAL;
743
744 case PIPE_FUNC_LEQUAL:
745 return MALI_ALT_FUNC_LEQUAL;
746
747 case PIPE_FUNC_GREATER:
748 return MALI_ALT_FUNC_GREATER;
749
750 case PIPE_FUNC_NOTEQUAL:
751 return MALI_ALT_FUNC_NOTEQUAL;
752
753 case PIPE_FUNC_GEQUAL:
754 return MALI_ALT_FUNC_GEQUAL;
755
756 case PIPE_FUNC_ALWAYS:
757 return MALI_ALT_FUNC_ALWAYS;
758 }
759
760 assert (0);
761 return 0; /* Unreachable */
762 }
763
764 static unsigned
765 panfrost_translate_stencil_op(enum pipe_stencil_op in)
766 {
767 switch (in) {
768 case PIPE_STENCIL_OP_KEEP:
769 return MALI_STENCIL_KEEP;
770
771 case PIPE_STENCIL_OP_ZERO:
772 return MALI_STENCIL_ZERO;
773
774 case PIPE_STENCIL_OP_REPLACE:
775 return MALI_STENCIL_REPLACE;
776
777 case PIPE_STENCIL_OP_INCR:
778 return MALI_STENCIL_INCR;
779
780 case PIPE_STENCIL_OP_DECR:
781 return MALI_STENCIL_DECR;
782
783 case PIPE_STENCIL_OP_INCR_WRAP:
784 return MALI_STENCIL_INCR_WRAP;
785
786 case PIPE_STENCIL_OP_DECR_WRAP:
787 return MALI_STENCIL_DECR_WRAP;
788
789 case PIPE_STENCIL_OP_INVERT:
790 return MALI_STENCIL_INVERT;
791 }
792
793 assert (0);
794 return 0; /* Unreachable */
795 }
796
797 static void
798 panfrost_make_stencil_state(const struct pipe_stencil_state *in, struct mali_stencil_test *out)
799 {
800 out->ref = 0; /* Gallium gets it from elsewhere */
801
802 out->mask = in->valuemask;
803 out->func = panfrost_translate_compare_func(in->func);
804 out->sfail = panfrost_translate_stencil_op(in->fail_op);
805 out->dpfail = panfrost_translate_stencil_op(in->zfail_op);
806 out->dppass = panfrost_translate_stencil_op(in->zpass_op);
807 }
808
809 static void
810 panfrost_default_shader_backend(struct panfrost_context *ctx)
811 {
812 struct mali_shader_meta shader = {
813 .alpha_coverage = ~MALI_ALPHA_COVERAGE(0.000000),
814
815 .unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x3010,
816 .unknown2_4 = MALI_NO_MSAA | 0x4e0,
817 };
818
819 if (is_t6xx) {
820 shader.unknown2_4 |= 0x10;
821 }
822
823 struct pipe_stencil_state default_stencil = {
824 .enabled = 0,
825 .func = PIPE_FUNC_ALWAYS,
826 .fail_op = MALI_STENCIL_KEEP,
827 .zfail_op = MALI_STENCIL_KEEP,
828 .zpass_op = MALI_STENCIL_KEEP,
829 .writemask = 0xFF,
830 .valuemask = 0xFF
831 };
832
833 panfrost_make_stencil_state(&default_stencil, &shader.stencil_front);
834 shader.stencil_mask_front = default_stencil.writemask;
835
836 panfrost_make_stencil_state(&default_stencil, &shader.stencil_back);
837 shader.stencil_mask_back = default_stencil.writemask;
838
839 if (default_stencil.enabled)
840 shader.unknown2_4 |= MALI_STENCIL_TEST;
841
842 memcpy(&ctx->fragment_shader_core, &shader, sizeof(shader));
843 }
844
845 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
846 * graphics command stream. It should be called once per draw, accordding to
847 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
848 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
849 * vertex jobs. */
850
851 struct panfrost_transfer
852 panfrost_vertex_tiler_job(struct panfrost_context *ctx, bool is_tiler, bool is_elided_tiler)
853 {
854 /* Each draw call corresponds to two jobs, and we want to offset to leave room for the set-value job */
855 int draw_job_index = 1 + (2 * ctx->draw_count);
856
857 struct mali_job_descriptor_header job = {
858 .job_type = is_tiler ? JOB_TYPE_TILER : JOB_TYPE_VERTEX,
859 .job_index = draw_job_index + (is_tiler ? 1 : 0),
860 #ifdef __LP64__
861 .job_descriptor_size = 1,
862 #endif
863 };
864
865 /* Only non-elided tiler jobs have dependencies which are known at this point */
866
867 if (is_tiler && !is_elided_tiler) {
868 /* Tiler jobs depend on vertex jobs */
869
870 job.job_dependency_index_1 = draw_job_index;
871
872 /* Tiler jobs also depend on the previous tiler job */
873
874 if (ctx->draw_count)
875 job.job_dependency_index_2 = draw_job_index - 1;
876 }
877
878 struct midgard_payload_vertex_tiler *payload = is_tiler ? &ctx->payload_tiler : &ctx->payload_vertex;
879
880 /* There's some padding hacks on 32-bit */
881
882 #ifdef __LP64__
883 int offset = 0;
884 #else
885 int offset = 4;
886 #endif
887 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(job) + sizeof(*payload));
888 memcpy(transfer.cpu, &job, sizeof(job));
889 memcpy(transfer.cpu + sizeof(job) - offset, payload, sizeof(*payload));
890 return transfer;
891 }
892
893 /* Generates a set value job. It's unclear what exactly this does, why it's
894 * necessary, and when to call it. */
895
896 static void
897 panfrost_set_value_job(struct panfrost_context *ctx)
898 {
899 struct mali_job_descriptor_header job = {
900 .job_type = JOB_TYPE_SET_VALUE,
901 .job_descriptor_size = 1,
902 .job_index = 1 + (2 * ctx->draw_count),
903 };
904
905 struct mali_payload_set_value payload = {
906 .out = ctx->misc_0.gpu,
907 .unknown = 0x3,
908 };
909
910 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(job) + sizeof(payload));
911 memcpy(transfer.cpu, &job, sizeof(job));
912 memcpy(transfer.cpu + sizeof(job), &payload, sizeof(payload));
913
914 ctx->u_set_value_job = (struct mali_job_descriptor_header *) transfer.cpu;
915 ctx->set_value_job = transfer.gpu;
916 }
917
918 /* Generate a fragment job. This should be called once per frame. (According to
919 * presentations, this is supposed to correspond to eglSwapBuffers) */
920
921 mali_ptr
922 panfrost_fragment_job(struct panfrost_context *ctx)
923 {
924 /* Update fragment FBD */
925 panfrost_set_fragment_afbc(ctx);
926
927 if (ctx->pipe_framebuffer.nr_cbufs == 1) {
928 struct panfrost_resource *rsrc = (struct panfrost_resource *) ctx->pipe_framebuffer.cbufs[0]->texture;
929
930 if (rsrc->bo->has_checksum) {
931 if (require_sfbd) {
932 fprintf(stderr, "Checksumming not supported on SFBD\n");
933 assert(0);
934 }
935
936 int stride = util_format_get_stride(rsrc->base.format, rsrc->base.width0);
937
938 ctx->fragment_mfbd.unk3 |= MALI_MFBD_EXTRA;
939 ctx->fragment_extra.unk |= 0x420;
940 ctx->fragment_extra.checksum_stride = rsrc->bo->checksum_stride;
941 ctx->fragment_extra.checksum = rsrc->bo->gpu[0] + stride * rsrc->base.height0;
942 }
943 }
944
945 /* The frame is complete and therefore the framebuffer descriptor is
946 * ready for linkage and upload */
947
948 size_t sz = require_sfbd ? sizeof(struct mali_single_framebuffer) : (sizeof(struct bifrost_framebuffer) + sizeof(struct bifrost_fb_extra) + sizeof(struct bifrost_render_target) * 1);
949 struct panfrost_transfer fbd_t = panfrost_allocate_transient(ctx, sz);
950 off_t offset = 0;
951
952 if (require_sfbd) {
953 /* Upload just the SFBD all at once */
954 memcpy(fbd_t.cpu, &ctx->fragment_sfbd, sizeof(ctx->fragment_sfbd));
955 offset += sizeof(ctx->fragment_sfbd);
956 } else {
957 /* Upload the MFBD header */
958 memcpy(fbd_t.cpu, &ctx->fragment_mfbd, sizeof(ctx->fragment_mfbd));
959 offset += sizeof(ctx->fragment_mfbd);
960
961 /* Upload extra framebuffer info if necessary */
962 if (ctx->fragment_mfbd.unk3 & MALI_MFBD_EXTRA) {
963 memcpy(fbd_t.cpu + offset, &ctx->fragment_extra, sizeof(struct bifrost_fb_extra));
964 offset += sizeof(struct bifrost_fb_extra);
965 }
966
967 /* Upload (single) render target */
968 memcpy(fbd_t.cpu + offset, &ctx->fragment_rts[0], sizeof(struct bifrost_render_target) * 1);
969 }
970
971 /* Generate the fragment (frame) job */
972
973 struct mali_job_descriptor_header header = {
974 .job_type = JOB_TYPE_FRAGMENT,
975 .job_index = 1,
976 #ifdef __LP64__
977 .job_descriptor_size = 1
978 #endif
979 };
980
981 struct mali_payload_fragment payload = {
982 .min_tile_coord = MALI_COORDINATE_TO_TILE_MIN(0, 0),
983 .max_tile_coord = MALI_COORDINATE_TO_TILE_MAX(ctx->pipe_framebuffer.width, ctx->pipe_framebuffer.height),
984 .framebuffer = fbd_t.gpu | (require_sfbd ? MALI_SFBD : MALI_MFBD),
985 };
986
987 if (!require_sfbd && ctx->fragment_mfbd.unk3 & MALI_MFBD_EXTRA) {
988 /* Signal that there is an extra portion of the framebuffer
989 * descriptor */
990
991 payload.framebuffer |= 2;
992 }
993
994 /* Normally, there should be no padding. However, fragment jobs are
995 * shared with 64-bit Bifrost systems, and accordingly there is 4-bytes
996 * of zero padding in between. */
997
998 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(header) + sizeof(payload));
999 memcpy(transfer.cpu, &header, sizeof(header));
1000 memcpy(transfer.cpu + sizeof(header), &payload, sizeof(payload));
1001 return transfer.gpu;
1002 }
1003
1004 /* Emits attributes and varying descriptors, which should be called every draw,
1005 * excepting some obscure circumstances */
1006
1007 static void
1008 panfrost_emit_vertex_data(struct panfrost_context *ctx)
1009 {
1010 /* TODO: Only update the dirtied buffers */
1011 union mali_attr attrs[PIPE_MAX_ATTRIBS];
1012 union mali_attr varyings[PIPE_MAX_ATTRIBS];
1013
1014 unsigned invocation_count = MALI_NEGATIVE(ctx->payload_tiler.prefix.invocation_count);
1015
1016 for (int i = 0; i < ctx->vertex_buffer_count; ++i) {
1017 struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[i];
1018 struct panfrost_resource *rsrc = (struct panfrost_resource *) (buf->buffer.resource);
1019
1020 /* Let's figure out the layout of the attributes in memory so
1021 * we can be smart about size computation. The idea is to
1022 * figure out the maximum src_offset, which tells us the latest
1023 * spot a vertex could start. Meanwhile, we figure out the size
1024 * of the attribute memory (assuming interleaved
1025 * representation) and tack on the max src_offset for a
1026 * reasonably good upper bound on the size.
1027 *
1028 * Proving correctness is left as an exercise to the reader.
1029 */
1030
1031 unsigned max_src_offset = 0;
1032
1033 for (unsigned j = 0; j < ctx->vertex->num_elements; ++j) {
1034 if (ctx->vertex->pipe[j].vertex_buffer_index != i) continue;
1035 max_src_offset = MAX2(max_src_offset, ctx->vertex->pipe[j].src_offset);
1036 }
1037
1038 /* Offset vertex count by draw_start to make sure we upload enough */
1039 attrs[i].stride = buf->stride;
1040 attrs[i].size = buf->stride * (ctx->payload_vertex.draw_start + invocation_count) + max_src_offset;
1041
1042 /* Vertex elements are -already- GPU-visible, at
1043 * rsrc->gpu. However, attribute buffers must be 64 aligned. If
1044 * it is not, for now we have to duplicate the buffer. */
1045
1046 mali_ptr effective_address = (rsrc->bo->gpu[0] + buf->buffer_offset);
1047
1048 if (effective_address & 0x3F) {
1049 attrs[i].elements = panfrost_upload_transient(ctx, rsrc->bo->cpu[0] + buf->buffer_offset, attrs[i].size) | 1;
1050 } else {
1051 attrs[i].elements = effective_address | 1;
1052 }
1053 }
1054
1055 struct panfrost_varyings *vars = &ctx->vs->variants[ctx->vs->active_variant].varyings;
1056
1057 for (int i = 0; i < vars->varying_buffer_count; ++i) {
1058 mali_ptr varying_address = ctx->varying_mem.gpu + ctx->varying_height;
1059
1060 varyings[i].elements = varying_address | 1;
1061 varyings[i].stride = vars->varyings_stride[i];
1062 varyings[i].size = vars->varyings_stride[i] * invocation_count;
1063
1064 /* If this varying has to be linked somewhere, do it now. See
1065 * pan_assemble.c for the indices. TODO: Use a more generic
1066 * linking interface */
1067
1068 if (i == 1) {
1069 /* gl_Position */
1070 ctx->payload_tiler.postfix.position_varying = varying_address;
1071 } else if (i == 2) {
1072 /* gl_PointSize */
1073 ctx->payload_tiler.primitive_size.pointer = varying_address;
1074 }
1075
1076 /* Varyings appear to need 64-byte alignment */
1077 ctx->varying_height += ALIGN(varyings[i].size, 64);
1078
1079 /* Ensure that we fit */
1080 assert(ctx->varying_height < ctx->varying_mem.size);
1081 }
1082
1083 ctx->payload_vertex.postfix.attributes = panfrost_upload_transient(ctx, attrs, ctx->vertex_buffer_count * sizeof(union mali_attr));
1084
1085 mali_ptr varyings_p = panfrost_upload_transient(ctx, &varyings, vars->varying_buffer_count * sizeof(union mali_attr));
1086 ctx->payload_vertex.postfix.varyings = varyings_p;
1087 ctx->payload_tiler.postfix.varyings = varyings_p;
1088 }
1089
1090 /* Go through dirty flags and actualise them in the cmdstream. */
1091
1092 void
1093 panfrost_emit_for_draw(struct panfrost_context *ctx, bool with_vertex_data)
1094 {
1095 if (with_vertex_data) {
1096 panfrost_emit_vertex_data(ctx);
1097 }
1098
1099 if (ctx->dirty & PAN_DIRTY_RASTERIZER) {
1100 ctx->payload_tiler.gl_enables = ctx->rasterizer->tiler_gl_enables;
1101 panfrost_set_framebuffer_msaa(ctx, ctx->rasterizer->base.multisample);
1102 }
1103
1104 if (ctx->occlusion_query) {
1105 ctx->payload_tiler.gl_enables |= MALI_OCCLUSION_QUERY | MALI_OCCLUSION_PRECISE;
1106 ctx->payload_tiler.postfix.occlusion_counter = ctx->occlusion_query->transfer.gpu;
1107 }
1108
1109 if (ctx->dirty & PAN_DIRTY_VS) {
1110 assert(ctx->vs);
1111
1112 struct panfrost_shader_state *vs = &ctx->vs->variants[ctx->vs->active_variant];
1113
1114 /* Late shader descriptor assignments */
1115 vs->tripipe->texture_count = ctx->sampler_view_count[PIPE_SHADER_VERTEX];
1116 vs->tripipe->sampler_count = ctx->sampler_count[PIPE_SHADER_VERTEX];
1117
1118 /* Who knows */
1119 vs->tripipe->midgard1.unknown1 = 0x2201;
1120
1121 ctx->payload_vertex.postfix._shader_upper = vs->tripipe_gpu >> 4;
1122
1123 /* Varying descriptor is tied to the vertex shader. Also the
1124 * fragment shader, I suppose, but it's generated with the
1125 * vertex shader so */
1126
1127 struct panfrost_varyings *varyings = &ctx->vs->variants[ctx->vs->active_variant].varyings;
1128
1129 ctx->payload_vertex.postfix.varying_meta = varyings->varyings_descriptor;
1130 ctx->payload_tiler.postfix.varying_meta = varyings->varyings_descriptor_fragment;
1131 }
1132
1133 if (ctx->dirty & (PAN_DIRTY_RASTERIZER | PAN_DIRTY_VS)) {
1134 /* Check if we need to link the gl_PointSize varying */
1135 assert(ctx->vs);
1136 struct panfrost_shader_state *vs = &ctx->vs->variants[ctx->vs->active_variant];
1137
1138 bool needs_gl_point_size = vs->writes_point_size && ctx->payload_tiler.prefix.draw_mode == MALI_POINTS;
1139
1140 if (!needs_gl_point_size) {
1141 /* If the size is constant, write it out. Otherwise,
1142 * don't touch primitive_size (since we would clobber
1143 * the pointer there) */
1144
1145 ctx->payload_tiler.primitive_size.constant = ctx->rasterizer->base.line_width;
1146 }
1147
1148 /* Set the flag for varying (pointer) point size if the shader needs that */
1149 SET_BIT(ctx->payload_tiler.prefix.unknown_draw, MALI_DRAW_VARYING_SIZE, needs_gl_point_size);
1150 }
1151
1152 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1153 if (ctx->fs)
1154 ctx->dirty |= PAN_DIRTY_FS;
1155
1156 if (ctx->dirty & PAN_DIRTY_FS) {
1157 assert(ctx->fs);
1158 struct panfrost_shader_state *variant = &ctx->fs->variants[ctx->fs->active_variant];
1159
1160 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1161
1162 COPY(shader);
1163 COPY(attribute_count);
1164 COPY(varying_count);
1165 COPY(midgard1.uniform_count);
1166 COPY(midgard1.work_count);
1167 COPY(midgard1.unknown2);
1168
1169 #undef COPY
1170 /* If there is a blend shader, work registers are shared */
1171
1172 if (ctx->blend->has_blend_shader)
1173 ctx->fragment_shader_core.midgard1.work_count = /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1174
1175 /* Set late due to depending on render state */
1176 /* The one at the end seems to mean "1 UBO" */
1177 ctx->fragment_shader_core.midgard1.unknown1 = MALI_NO_ALPHA_TO_COVERAGE | 0x200 | 0x2201;
1178
1179 /* Assign texture/sample count right before upload */
1180 ctx->fragment_shader_core.texture_count = ctx->sampler_view_count[PIPE_SHADER_FRAGMENT];
1181 ctx->fragment_shader_core.sampler_count = ctx->sampler_count[PIPE_SHADER_FRAGMENT];
1182
1183 /* Assign the stencil refs late */
1184 ctx->fragment_shader_core.stencil_front.ref = ctx->stencil_ref.ref_value[0];
1185 ctx->fragment_shader_core.stencil_back.ref = ctx->stencil_ref.ref_value[1];
1186
1187 /* CAN_DISCARD should be set if the fragment shader possibly
1188 * contains a 'discard' instruction. It is likely this is
1189 * related to optimizations related to forward-pixel kill, as
1190 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1191 * thing?" by Peter Harris
1192 */
1193
1194 if (variant->can_discard) {
1195 ctx->fragment_shader_core.unknown2_3 |= MALI_CAN_DISCARD;
1196 ctx->fragment_shader_core.midgard1.unknown1 &= ~MALI_NO_ALPHA_TO_COVERAGE;
1197 ctx->fragment_shader_core.midgard1.unknown1 |= 0x4000;
1198 ctx->fragment_shader_core.midgard1.unknown1 = 0x4200;
1199 }
1200
1201 /* Check if we're using the default blend descriptor (fast path) */
1202
1203 bool no_blending =
1204 !ctx->blend->has_blend_shader &&
1205 (ctx->blend->equation.rgb_mode == 0x122) &&
1206 (ctx->blend->equation.alpha_mode == 0x122) &&
1207 (ctx->blend->equation.color_mask == 0xf);
1208
1209 if (require_sfbd) {
1210 /* When only a single render target platform is used, the blend
1211 * information is inside the shader meta itself. We
1212 * additionally need to signal CAN_DISCARD for nontrivial blend
1213 * modes (so we're able to read back the destination buffer) */
1214
1215 if (ctx->blend->has_blend_shader) {
1216 ctx->fragment_shader_core.blend_shader = ctx->blend->blend_shader;
1217 } else {
1218 memcpy(&ctx->fragment_shader_core.blend_equation, &ctx->blend->equation, sizeof(ctx->blend->equation));
1219 }
1220
1221 if (!no_blending) {
1222 ctx->fragment_shader_core.unknown2_3 |= MALI_CAN_DISCARD;
1223 }
1224 }
1225
1226 size_t size = sizeof(struct mali_shader_meta) + sizeof(struct mali_blend_meta);
1227 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, size);
1228 memcpy(transfer.cpu, &ctx->fragment_shader_core, sizeof(struct mali_shader_meta));
1229
1230 ctx->payload_tiler.postfix._shader_upper = (transfer.gpu) >> 4;
1231
1232 if (!require_sfbd) {
1233 /* Additional blend descriptor tacked on for jobs using MFBD */
1234
1235 unsigned blend_count = 0;
1236
1237 if (ctx->blend->has_blend_shader) {
1238 /* For a blend shader, the bottom nibble corresponds to
1239 * the number of work registers used, which signals the
1240 * -existence- of a blend shader */
1241
1242 assert(ctx->blend->blend_work_count >= 2);
1243 blend_count |= MIN2(ctx->blend->blend_work_count, 3);
1244 } else {
1245 /* Otherwise, the bottom bit simply specifies if
1246 * blending (anything other than REPLACE) is enabled */
1247
1248
1249 if (!no_blending)
1250 blend_count |= 0x1;
1251 }
1252
1253 /* Second blend equation is always a simple replace */
1254
1255 uint64_t replace_magic = 0xf0122122;
1256 struct mali_blend_equation replace_mode;
1257 memcpy(&replace_mode, &replace_magic, sizeof(replace_mode));
1258
1259 struct mali_blend_meta blend_meta[] = {
1260 {
1261 .unk1 = 0x200 | blend_count,
1262 .blend_equation_1 = ctx->blend->equation,
1263 .blend_equation_2 = replace_mode
1264 },
1265 };
1266
1267 if (ctx->blend->has_blend_shader)
1268 memcpy(&blend_meta[0].blend_equation_1, &ctx->blend->blend_shader, sizeof(ctx->blend->blend_shader));
1269
1270 memcpy(transfer.cpu + sizeof(struct mali_shader_meta), blend_meta, sizeof(blend_meta));
1271 }
1272 }
1273
1274 if (ctx->dirty & PAN_DIRTY_VERTEX) {
1275 ctx->payload_vertex.postfix.attribute_meta = ctx->vertex->descriptor_ptr;
1276 }
1277
1278 if (ctx->dirty & PAN_DIRTY_SAMPLERS) {
1279 /* Upload samplers back to back, no padding */
1280
1281 for (int t = 0; t <= PIPE_SHADER_FRAGMENT; ++t) {
1282 if (!ctx->sampler_count[t]) continue;
1283
1284 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(struct mali_sampler_descriptor) * ctx->sampler_count[t]);
1285 struct mali_sampler_descriptor *desc = (struct mali_sampler_descriptor *) transfer.cpu;
1286
1287 for (int i = 0; i < ctx->sampler_count[t]; ++i) {
1288 desc[i] = ctx->samplers[t][i]->hw;
1289 }
1290
1291 if (t == PIPE_SHADER_FRAGMENT)
1292 ctx->payload_tiler.postfix.sampler_descriptor = transfer.gpu;
1293 else if (t == PIPE_SHADER_VERTEX)
1294 ctx->payload_vertex.postfix.sampler_descriptor = transfer.gpu;
1295 else
1296 assert(0);
1297 }
1298 }
1299
1300 if (ctx->dirty & PAN_DIRTY_TEXTURES) {
1301 for (int t = 0; t <= PIPE_SHADER_FRAGMENT; ++t) {
1302 /* Shortcircuit */
1303 if (!ctx->sampler_view_count[t]) continue;
1304
1305 uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS];
1306
1307 for (int i = 0; i < ctx->sampler_view_count[t]; ++i) {
1308 if (!ctx->sampler_views[t][i])
1309 continue;
1310
1311 struct pipe_resource *tex_rsrc = ctx->sampler_views[t][i]->base.texture;
1312 struct panfrost_resource *rsrc = (struct panfrost_resource *) tex_rsrc;
1313
1314 /* Inject the address in. */
1315 for (int l = 0; l < (tex_rsrc->last_level + 1); ++l)
1316 ctx->sampler_views[t][i]->hw.swizzled_bitmaps[l] = rsrc->bo->gpu[l];
1317
1318 /* Workaround maybe-errata (?) with non-mipmaps */
1319 int s = ctx->sampler_views[t][i]->hw.nr_mipmap_levels;
1320
1321 if (!rsrc->bo->is_mipmap) {
1322 if (is_t6xx) {
1323 /* HW ERRATA, not needed after t6XX */
1324 ctx->sampler_views[t][i]->hw.swizzled_bitmaps[1] = rsrc->bo->gpu[0];
1325
1326 ctx->sampler_views[t][i]->hw.unknown3A = 1;
1327 }
1328
1329 ctx->sampler_views[t][i]->hw.nr_mipmap_levels = 0;
1330 }
1331
1332 trampolines[i] = panfrost_upload_transient(ctx, &ctx->sampler_views[t][i]->hw, sizeof(struct mali_texture_descriptor));
1333
1334 /* Restore */
1335 ctx->sampler_views[t][i]->hw.nr_mipmap_levels = s;
1336
1337 if (is_t6xx) {
1338 ctx->sampler_views[t][i]->hw.unknown3A = 0;
1339 }
1340 }
1341
1342 mali_ptr trampoline = panfrost_upload_transient(ctx, trampolines, sizeof(uint64_t) * ctx->sampler_view_count[t]);
1343
1344 if (t == PIPE_SHADER_FRAGMENT)
1345 ctx->payload_tiler.postfix.texture_trampoline = trampoline;
1346 else if (t == PIPE_SHADER_VERTEX)
1347 ctx->payload_vertex.postfix.texture_trampoline = trampoline;
1348 else
1349 assert(0);
1350 }
1351 }
1352
1353 /* Generate the viewport vector of the form: <width/2, height/2, centerx, centery> */
1354 const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
1355
1356 float viewport_vec4[] = {
1357 vp->scale[0],
1358 fabsf(vp->scale[1]),
1359
1360 vp->translate[0],
1361 /* -1.0 * vp->translate[1] */ fabs(1.0 * vp->scale[1]) /* XXX */
1362 };
1363
1364 for (int i = 0; i < PIPE_SHADER_TYPES; ++i) {
1365 struct panfrost_constant_buffer *buf = &ctx->constant_buffer[i];
1366
1367 if (i == PIPE_SHADER_VERTEX || i == PIPE_SHADER_FRAGMENT) {
1368 /* It doesn't matter if we don't use all the memory;
1369 * we'd need a dummy UBO anyway. Compute the max */
1370
1371 size_t size = sizeof(viewport_vec4) + buf->size;
1372 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, size);
1373
1374 /* Keep track how much we've uploaded */
1375 off_t offset = 0;
1376
1377 if (i == PIPE_SHADER_VERTEX) {
1378 /* Upload viewport */
1379 memcpy(transfer.cpu + offset, viewport_vec4, sizeof(viewport_vec4));
1380 offset += sizeof(viewport_vec4);
1381 }
1382
1383 /* Upload uniforms */
1384 memcpy(transfer.cpu + offset, buf->buffer, buf->size);
1385
1386 int uniform_count = 0;
1387
1388 struct mali_vertex_tiler_postfix *postfix;
1389
1390 switch (i) {
1391 case PIPE_SHADER_VERTEX:
1392 uniform_count = ctx->vs->variants[ctx->vs->active_variant].uniform_count;
1393 postfix = &ctx->payload_vertex.postfix;
1394 break;
1395
1396 case PIPE_SHADER_FRAGMENT:
1397 uniform_count = ctx->fs->variants[ctx->fs->active_variant].uniform_count;
1398 postfix = &ctx->payload_tiler.postfix;
1399 break;
1400
1401 default:
1402 printf("Unknown shader stage %d in uniform upload\n", i);
1403 assert(0);
1404 }
1405
1406 /* Also attach the same buffer as a UBO for extended access */
1407
1408 struct mali_uniform_buffer_meta uniform_buffers[] = {
1409 {
1410 .size = MALI_POSITIVE((2 + uniform_count)),
1411 .ptr = transfer.gpu >> 2,
1412 },
1413 };
1414
1415 mali_ptr ubufs = panfrost_upload_transient(ctx, uniform_buffers, sizeof(uniform_buffers));
1416 postfix->uniforms = transfer.gpu;
1417 postfix->uniform_buffers = ubufs;
1418
1419 buf->dirty = 0;
1420 }
1421 }
1422
1423 ctx->dirty = 0;
1424 }
1425
1426 /* Corresponds to exactly one draw, but does not submit anything */
1427
1428 static void
1429 panfrost_queue_draw(struct panfrost_context *ctx)
1430 {
1431 /* TODO: Expand the array? */
1432 if (ctx->draw_count >= MAX_DRAW_CALLS) {
1433 printf("Job buffer overflow, ignoring draw\n");
1434 assert(0);
1435 }
1436
1437 /* Handle dirty flags now */
1438 panfrost_emit_for_draw(ctx, true);
1439
1440 struct panfrost_transfer vertex = panfrost_vertex_tiler_job(ctx, false, false);
1441 struct panfrost_transfer tiler = panfrost_vertex_tiler_job(ctx, true, false);
1442
1443 ctx->u_vertex_jobs[ctx->vertex_job_count] = (struct mali_job_descriptor_header *) vertex.cpu;
1444 ctx->vertex_jobs[ctx->vertex_job_count++] = vertex.gpu;
1445
1446 ctx->u_tiler_jobs[ctx->tiler_job_count] = (struct mali_job_descriptor_header *) tiler.cpu;
1447 ctx->tiler_jobs[ctx->tiler_job_count++] = tiler.gpu;
1448
1449 ctx->draw_count++;
1450 }
1451
1452 /* At the end of the frame, the vertex and tiler jobs are linked together and
1453 * then the fragment job is plonked at the end. Set value job is first for
1454 * unknown reasons. */
1455
1456 static void
1457 panfrost_link_job_pair(struct mali_job_descriptor_header *first, mali_ptr next)
1458 {
1459 if (first->job_descriptor_size)
1460 first->next_job_64 = (u64) (uintptr_t) next;
1461 else
1462 first->next_job_32 = (u32) (uintptr_t) next;
1463 }
1464
1465 static void
1466 panfrost_link_jobs(struct panfrost_context *ctx)
1467 {
1468 if (ctx->draw_count) {
1469 /* Generate the set_value_job */
1470 panfrost_set_value_job(ctx);
1471
1472 /* Have the first vertex job depend on the set value job */
1473 ctx->u_vertex_jobs[0]->job_dependency_index_1 = ctx->u_set_value_job->job_index;
1474
1475 /* SV -> V */
1476 panfrost_link_job_pair(ctx->u_set_value_job, ctx->vertex_jobs[0]);
1477 }
1478
1479 /* V -> V/T ; T -> T/null */
1480 for (int i = 0; i < ctx->vertex_job_count; ++i) {
1481 bool isLast = (i + 1) == ctx->vertex_job_count;
1482
1483 panfrost_link_job_pair(ctx->u_vertex_jobs[i], isLast ? ctx->tiler_jobs[0] : ctx->vertex_jobs[i + 1]);
1484 }
1485
1486 /* T -> T/null */
1487 for (int i = 0; i < ctx->tiler_job_count; ++i) {
1488 bool isLast = (i + 1) == ctx->tiler_job_count;
1489 panfrost_link_job_pair(ctx->u_tiler_jobs[i], isLast ? 0 : ctx->tiler_jobs[i + 1]);
1490 }
1491 }
1492
1493 /* The entire frame is in memory -- send it off to the kernel! */
1494
1495 static void
1496 panfrost_submit_frame(struct panfrost_context *ctx, bool flush_immediate)
1497 {
1498 struct pipe_context *gallium = (struct pipe_context *) ctx;
1499 struct panfrost_screen *screen = pan_screen(gallium->screen);
1500
1501 /* Edge case if screen is cleared and nothing else */
1502 bool has_draws = ctx->draw_count > 0;
1503
1504 /* Workaround a bizarre lockup (a hardware errata?) */
1505 if (!has_draws)
1506 flush_immediate = true;
1507
1508 /* A number of jobs are batched -- this must be linked and cleared */
1509 panfrost_link_jobs(ctx);
1510
1511 ctx->draw_count = 0;
1512 ctx->vertex_job_count = 0;
1513 ctx->tiler_job_count = 0;
1514
1515 #ifndef DRY_RUN
1516
1517 bool is_scanout = panfrost_is_scanout(ctx);
1518 int fragment_id = screen->driver->submit_vs_fs_job(ctx, has_draws, is_scanout);
1519
1520 /* If visual, we can stall a frame */
1521
1522 if (panfrost_is_scanout(ctx) && !flush_immediate)
1523 screen->driver->force_flush_fragment(ctx);
1524
1525 screen->last_fragment_id = fragment_id;
1526 screen->last_fragment_flushed = false;
1527
1528 /* If readback, flush now (hurts the pipelined performance) */
1529 if (panfrost_is_scanout(ctx) && flush_immediate)
1530 screen->driver->force_flush_fragment(ctx);
1531
1532 #ifdef DUMP_PERFORMANCE_COUNTERS
1533 char filename[128];
1534 snprintf(filename, sizeof(filename), "/dev/shm/frame%d.mdgprf", ++performance_counter_number);
1535 FILE *fp = fopen(filename, "wb");
1536 fwrite(screen->perf_counters.cpu, 4096, sizeof(uint32_t), fp);
1537 fclose(fp);
1538 #endif
1539
1540 #endif
1541 }
1542
1543 bool dont_scanout = false;
1544
1545 void
1546 panfrost_flush(
1547 struct pipe_context *pipe,
1548 struct pipe_fence_handle **fence,
1549 unsigned flags)
1550 {
1551 struct panfrost_context *ctx = pan_context(pipe);
1552
1553 /* If there is nothing drawn, skip the frame */
1554 if (!ctx->draw_count && !ctx->frame_cleared) return;
1555
1556 if (!ctx->frame_cleared) {
1557 /* While there are draws, there was no clear. This is a partial
1558 * update, which needs to be handled via the "wallpaper"
1559 * method. We also need to fake a clear, just to get the
1560 * FRAGMENT job correct. */
1561
1562 panfrost_clear(&ctx->base, ctx->last_clear.buffers, ctx->last_clear.color, ctx->last_clear.depth, ctx->last_clear.stencil);
1563
1564 panfrost_draw_wallpaper(pipe);
1565 }
1566
1567 /* Frame clear handled, reset */
1568 ctx->frame_cleared = false;
1569
1570 /* Whether to stall the pipeline for immediately correct results */
1571 bool flush_immediate = flags & PIPE_FLUSH_END_OF_FRAME;
1572
1573 /* Submit the frame itself */
1574 panfrost_submit_frame(ctx, flush_immediate);
1575
1576 /* Prepare for the next frame */
1577 panfrost_invalidate_frame(ctx);
1578 }
1579
1580 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1581
1582 static int
1583 g2m_draw_mode(enum pipe_prim_type mode)
1584 {
1585 switch (mode) {
1586 DEFINE_CASE(POINTS);
1587 DEFINE_CASE(LINES);
1588 DEFINE_CASE(LINE_LOOP);
1589 DEFINE_CASE(LINE_STRIP);
1590 DEFINE_CASE(TRIANGLES);
1591 DEFINE_CASE(TRIANGLE_STRIP);
1592 DEFINE_CASE(TRIANGLE_FAN);
1593 DEFINE_CASE(QUADS);
1594 DEFINE_CASE(QUAD_STRIP);
1595 DEFINE_CASE(POLYGON);
1596
1597 default:
1598 printf("Illegal draw mode %d\n", mode);
1599 assert(0);
1600 return MALI_LINE_LOOP;
1601 }
1602 }
1603
1604 #undef DEFINE_CASE
1605
1606 static unsigned
1607 panfrost_translate_index_size(unsigned size)
1608 {
1609 switch (size) {
1610 case 1:
1611 return MALI_DRAW_INDEXED_UINT8;
1612
1613 case 2:
1614 return MALI_DRAW_INDEXED_UINT16;
1615
1616 case 4:
1617 return MALI_DRAW_INDEXED_UINT32;
1618
1619 default:
1620 printf("Unknown index size %d\n", size);
1621 assert(0);
1622 return 0;
1623 }
1624 }
1625
1626 static const uint8_t *
1627 panfrost_get_index_buffer_raw(const struct pipe_draw_info *info)
1628 {
1629 if (info->has_user_indices) {
1630 return (const uint8_t *) info->index.user;
1631 } else {
1632 struct panfrost_resource *rsrc = (struct panfrost_resource *) (info->index.resource);
1633 return (const uint8_t *) rsrc->bo->cpu[0];
1634 }
1635 }
1636
1637 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1638 * good for the duration of the draw (transient), could last longer */
1639
1640 static mali_ptr
1641 panfrost_get_index_buffer_mapped(struct panfrost_context *ctx, const struct pipe_draw_info *info)
1642 {
1643 struct panfrost_resource *rsrc = (struct panfrost_resource *) (info->index.resource);
1644
1645 off_t offset = info->start * info->index_size;
1646
1647 if (!info->has_user_indices) {
1648 /* Only resources can be directly mapped */
1649 return rsrc->bo->gpu[0] + offset;
1650 } else {
1651 /* Otherwise, we need to upload to transient memory */
1652 const uint8_t *ibuf8 = panfrost_get_index_buffer_raw(info);
1653 return panfrost_upload_transient(ctx, ibuf8 + offset, info->count * info->index_size);
1654 }
1655 }
1656
1657 static void
1658 panfrost_draw_vbo(
1659 struct pipe_context *pipe,
1660 const struct pipe_draw_info *info);
1661
1662 #define CALCULATE_MIN_MAX_INDEX(T, buffer, start, count) \
1663 for (unsigned _idx = (start); _idx < (start + count); ++_idx) { \
1664 T idx = buffer[_idx]; \
1665 if (idx > max_index) max_index = idx; \
1666 if (idx < min_index) min_index = idx; \
1667 }
1668
1669 static void
1670 panfrost_draw_vbo(
1671 struct pipe_context *pipe,
1672 const struct pipe_draw_info *info)
1673 {
1674 struct panfrost_context *ctx = pan_context(pipe);
1675
1676 ctx->payload_vertex.draw_start = info->start;
1677 ctx->payload_tiler.draw_start = info->start;
1678
1679 int mode = info->mode;
1680
1681 /* Fallback for unsupported modes */
1682
1683 if (!(ctx->draw_modes & mode)) {
1684 if (mode == PIPE_PRIM_QUADS && info->count == 4 && ctx->rasterizer && !ctx->rasterizer->base.flatshade) {
1685 mode = PIPE_PRIM_TRIANGLE_FAN;
1686 } else {
1687 if (info->count < 4) {
1688 /* Degenerate case? */
1689 return;
1690 }
1691
1692 util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base);
1693 util_primconvert_draw_vbo(ctx->primconvert, info);
1694 return;
1695 }
1696 }
1697
1698 ctx->payload_tiler.prefix.draw_mode = g2m_draw_mode(mode);
1699
1700 ctx->vertex_count = info->count;
1701
1702 /* For non-indexed draws, they're the same */
1703 unsigned invocation_count = ctx->vertex_count;
1704
1705 /* For higher amounts of vertices (greater than what fits in a 16-bit
1706 * short), the other value is needed, otherwise there will be bizarre
1707 * rendering artefacts. It's not clear what these values mean yet. */
1708
1709 ctx->payload_tiler.prefix.unknown_draw &= ~(0x3000 | 0x18000);
1710 ctx->payload_tiler.prefix.unknown_draw |= (mode == PIPE_PRIM_POINTS || ctx->vertex_count > 65535) ? 0x3000 : 0x18000;
1711
1712 if (info->index_size) {
1713 /* Calculate the min/max index used so we can figure out how
1714 * many times to invoke the vertex shader */
1715
1716 const uint8_t *ibuf8 = panfrost_get_index_buffer_raw(info);
1717
1718 int min_index = INT_MAX;
1719 int max_index = 0;
1720
1721 if (info->index_size == 1) {
1722 CALCULATE_MIN_MAX_INDEX(uint8_t, ibuf8, info->start, info->count);
1723 } else if (info->index_size == 2) {
1724 const uint16_t *ibuf16 = (const uint16_t *) ibuf8;
1725 CALCULATE_MIN_MAX_INDEX(uint16_t, ibuf16, info->start, info->count);
1726 } else if (info->index_size == 4) {
1727 const uint32_t *ibuf32 = (const uint32_t *) ibuf8;
1728 CALCULATE_MIN_MAX_INDEX(uint32_t, ibuf32, info->start, info->count);
1729 } else {
1730 assert(0);
1731 }
1732
1733 /* Make sure we didn't go crazy */
1734 assert(min_index < INT_MAX);
1735 assert(max_index > 0);
1736 assert(max_index > min_index);
1737
1738 /* Use the corresponding values */
1739 invocation_count = max_index - min_index + 1;
1740 ctx->payload_vertex.draw_start = min_index;
1741 ctx->payload_tiler.draw_start = min_index;
1742
1743 ctx->payload_tiler.prefix.negative_start = -min_index;
1744 ctx->payload_tiler.prefix.index_count = MALI_POSITIVE(info->count);
1745
1746 //assert(!info->restart_index); /* TODO: Research */
1747 assert(!info->index_bias);
1748 //assert(!info->min_index); /* TODO: Use value */
1749
1750 ctx->payload_tiler.prefix.unknown_draw |= panfrost_translate_index_size(info->index_size);
1751 ctx->payload_tiler.prefix.indices = panfrost_get_index_buffer_mapped(ctx, info);
1752 } else {
1753 /* Index count == vertex count, if no indexing is applied, as
1754 * if it is internally indexed in the expected order */
1755
1756 ctx->payload_tiler.prefix.negative_start = 0;
1757 ctx->payload_tiler.prefix.index_count = MALI_POSITIVE(ctx->vertex_count);
1758
1759 /* Reverse index state */
1760 ctx->payload_tiler.prefix.unknown_draw &= ~MALI_DRAW_INDEXED_UINT32;
1761 ctx->payload_tiler.prefix.indices = (uintptr_t) NULL;
1762 }
1763
1764 ctx->payload_vertex.prefix.invocation_count = MALI_POSITIVE(invocation_count);
1765 ctx->payload_tiler.prefix.invocation_count = MALI_POSITIVE(invocation_count);
1766
1767 /* Fire off the draw itself */
1768 panfrost_queue_draw(ctx);
1769 }
1770
1771 /* CSO state */
1772
1773 static void
1774 panfrost_generic_cso_delete(struct pipe_context *pctx, void *hwcso)
1775 {
1776 free(hwcso);
1777 }
1778
1779 static void
1780 panfrost_set_scissor(struct panfrost_context *ctx)
1781 {
1782 const struct pipe_scissor_state *ss = &ctx->scissor;
1783
1784 if (ss && ctx->rasterizer && ctx->rasterizer->base.scissor && 0) {
1785 ctx->viewport->viewport0[0] = ss->minx;
1786 ctx->viewport->viewport0[1] = ss->miny;
1787 ctx->viewport->viewport1[0] = MALI_POSITIVE(ss->maxx);
1788 ctx->viewport->viewport1[1] = MALI_POSITIVE(ss->maxy);
1789 } else {
1790 ctx->viewport->viewport0[0] = 0;
1791 ctx->viewport->viewport0[1] = 0;
1792 ctx->viewport->viewport1[0] = MALI_POSITIVE(ctx->pipe_framebuffer.width);
1793 ctx->viewport->viewport1[1] = MALI_POSITIVE(ctx->pipe_framebuffer.height);
1794 }
1795 }
1796
1797 static void *
1798 panfrost_create_rasterizer_state(
1799 struct pipe_context *pctx,
1800 const struct pipe_rasterizer_state *cso)
1801 {
1802 struct panfrost_rasterizer *so = CALLOC_STRUCT(panfrost_rasterizer);
1803
1804 so->base = *cso;
1805
1806 /* Bitmask, unknown meaning of the start value */
1807 so->tiler_gl_enables = is_t6xx ? 0x105 : 0x7;
1808
1809 so->tiler_gl_enables |= MALI_FRONT_FACE(
1810 cso->front_ccw ? MALI_CCW : MALI_CW);
1811
1812 if (cso->cull_face & PIPE_FACE_FRONT)
1813 so->tiler_gl_enables |= MALI_CULL_FACE_FRONT;
1814
1815 if (cso->cull_face & PIPE_FACE_BACK)
1816 so->tiler_gl_enables |= MALI_CULL_FACE_BACK;
1817
1818 return so;
1819 }
1820
1821 static void
1822 panfrost_bind_rasterizer_state(
1823 struct pipe_context *pctx,
1824 void *hwcso)
1825 {
1826 struct panfrost_context *ctx = pan_context(pctx);
1827 struct pipe_rasterizer_state *cso = hwcso;
1828
1829 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1830 if (!hwcso)
1831 return;
1832
1833 /* If scissor test has changed, we'll need to update that now */
1834 bool update_scissor = !ctx->rasterizer || ctx->rasterizer->base.scissor != cso->scissor;
1835
1836 ctx->rasterizer = hwcso;
1837
1838 /* Actualise late changes */
1839 if (update_scissor)
1840 panfrost_set_scissor(ctx);
1841
1842 ctx->dirty |= PAN_DIRTY_RASTERIZER;
1843 }
1844
1845 static void *
1846 panfrost_create_vertex_elements_state(
1847 struct pipe_context *pctx,
1848 unsigned num_elements,
1849 const struct pipe_vertex_element *elements)
1850 {
1851 struct panfrost_context *ctx = pan_context(pctx);
1852 struct panfrost_vertex_state *so = CALLOC_STRUCT(panfrost_vertex_state);
1853
1854 so->num_elements = num_elements;
1855 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
1856
1857 struct panfrost_transfer transfer = panfrost_allocate_chunk(ctx, sizeof(struct mali_attr_meta) * num_elements, HEAP_DESCRIPTOR);
1858 so->hw = (struct mali_attr_meta *) transfer.cpu;
1859 so->descriptor_ptr = transfer.gpu;
1860
1861 /* Allocate memory for the descriptor state */
1862
1863 for (int i = 0; i < num_elements; ++i) {
1864 so->hw[i].index = elements[i].vertex_buffer_index;
1865
1866 enum pipe_format fmt = elements[i].src_format;
1867 const struct util_format_description *desc = util_format_description(fmt);
1868 so->hw[i].unknown1 = 0x2;
1869 so->hw[i].swizzle = panfrost_get_default_swizzle(desc->nr_channels);
1870
1871 so->hw[i].format = panfrost_find_format(desc);
1872
1873 /* The field itself should probably be shifted over */
1874 so->hw[i].src_offset = elements[i].src_offset;
1875 }
1876
1877 return so;
1878 }
1879
1880 static void
1881 panfrost_bind_vertex_elements_state(
1882 struct pipe_context *pctx,
1883 void *hwcso)
1884 {
1885 struct panfrost_context *ctx = pan_context(pctx);
1886
1887 ctx->vertex = hwcso;
1888 ctx->dirty |= PAN_DIRTY_VERTEX;
1889 }
1890
1891 static void
1892 panfrost_delete_vertex_elements_state(struct pipe_context *pctx, void *hwcso)
1893 {
1894 struct panfrost_vertex_state *so = (struct panfrost_vertex_state *) hwcso;
1895 unsigned bytes = sizeof(struct mali_attr_meta) * so->num_elements;
1896 printf("Vertex elements delete leaks descriptor (%d bytes)\n", bytes);
1897 free(hwcso);
1898 }
1899
1900 static void *
1901 panfrost_create_shader_state(
1902 struct pipe_context *pctx,
1903 const struct pipe_shader_state *cso)
1904 {
1905 struct panfrost_shader_variants *so = CALLOC_STRUCT(panfrost_shader_variants);
1906 so->base = *cso;
1907
1908 /* Token deep copy to prevent memory corruption */
1909
1910 if (cso->type == PIPE_SHADER_IR_TGSI)
1911 so->base.tokens = tgsi_dup_tokens(so->base.tokens);
1912
1913 return so;
1914 }
1915
1916 static void
1917 panfrost_delete_shader_state(
1918 struct pipe_context *pctx,
1919 void *so)
1920 {
1921 struct panfrost_shader_variants *cso = (struct panfrost_shader_variants *) so;
1922
1923 if (cso->base.type == PIPE_SHADER_IR_TGSI) {
1924 printf("Deleting TGSI shader leaks duplicated tokens\n");
1925 }
1926
1927 unsigned leak = cso->variant_count * sizeof(struct mali_shader_meta);
1928 printf("Deleting shader state leaks descriptors (%d bytes), and shader bytecode\n", leak);
1929
1930 free(so);
1931 }
1932
1933 static void *
1934 panfrost_create_sampler_state(
1935 struct pipe_context *pctx,
1936 const struct pipe_sampler_state *cso)
1937 {
1938 struct panfrost_sampler_state *so = CALLOC_STRUCT(panfrost_sampler_state);
1939 so->base = *cso;
1940
1941 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1942
1943 struct mali_sampler_descriptor sampler_descriptor = {
1944 .filter_mode = MALI_TEX_MIN(translate_tex_filter(cso->min_img_filter))
1945 | MALI_TEX_MAG(translate_tex_filter(cso->mag_img_filter))
1946 | translate_mip_filter(cso->min_mip_filter)
1947 | 0x20,
1948
1949 .wrap_s = translate_tex_wrap(cso->wrap_s),
1950 .wrap_t = translate_tex_wrap(cso->wrap_t),
1951 .wrap_r = translate_tex_wrap(cso->wrap_r),
1952 .compare_func = panfrost_translate_alt_compare_func(cso->compare_func),
1953 .border_color = {
1954 cso->border_color.f[0],
1955 cso->border_color.f[1],
1956 cso->border_color.f[2],
1957 cso->border_color.f[3]
1958 },
1959 .min_lod = FIXED_16(0.0),
1960 .max_lod = FIXED_16(31.0),
1961 .unknown2 = 1,
1962 };
1963
1964 so->hw = sampler_descriptor;
1965
1966 return so;
1967 }
1968
1969 static void
1970 panfrost_bind_sampler_states(
1971 struct pipe_context *pctx,
1972 enum pipe_shader_type shader,
1973 unsigned start_slot, unsigned num_sampler,
1974 void **sampler)
1975 {
1976 assert(start_slot == 0);
1977
1978 struct panfrost_context *ctx = pan_context(pctx);
1979
1980 /* XXX: Should upload, not just copy? */
1981 ctx->sampler_count[shader] = num_sampler;
1982 memcpy(ctx->samplers[shader], sampler, num_sampler * sizeof (void *));
1983
1984 ctx->dirty |= PAN_DIRTY_SAMPLERS;
1985 }
1986
1987 static bool
1988 panfrost_variant_matches(struct panfrost_context *ctx, struct panfrost_shader_state *variant)
1989 {
1990 struct pipe_alpha_state *alpha = &ctx->depth_stencil->alpha;
1991
1992 if (alpha->enabled || variant->alpha_state.enabled) {
1993 /* Make sure enable state is at least the same */
1994 if (alpha->enabled != variant->alpha_state.enabled) {
1995 return false;
1996 }
1997
1998 /* Check that the contents of the test are the same */
1999 bool same_func = alpha->func == variant->alpha_state.func;
2000 bool same_ref = alpha->ref_value == variant->alpha_state.ref_value;
2001
2002 if (!(same_func && same_ref)) {
2003 return false;
2004 }
2005 }
2006 /* Otherwise, we're good to go */
2007 return true;
2008 }
2009
2010 static void
2011 panfrost_bind_fs_state(
2012 struct pipe_context *pctx,
2013 void *hwcso)
2014 {
2015 struct panfrost_context *ctx = pan_context(pctx);
2016
2017 ctx->fs = hwcso;
2018
2019 if (hwcso) {
2020 /* Match the appropriate variant */
2021
2022 signed variant = -1;
2023
2024 struct panfrost_shader_variants *variants = (struct panfrost_shader_variants *) hwcso;
2025
2026 for (unsigned i = 0; i < variants->variant_count; ++i) {
2027 if (panfrost_variant_matches(ctx, &variants->variants[i])) {
2028 variant = i;
2029 break;
2030 }
2031 }
2032
2033 if (variant == -1) {
2034 /* No variant matched, so create a new one */
2035 variant = variants->variant_count++;
2036 assert(variants->variant_count < MAX_SHADER_VARIANTS);
2037
2038 variants->variants[variant].base = hwcso;
2039 variants->variants[variant].alpha_state = ctx->depth_stencil->alpha;
2040
2041 /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
2042 struct panfrost_context *ctx = pan_context(pctx);
2043 struct panfrost_transfer transfer = panfrost_allocate_chunk(ctx, sizeof(struct mali_shader_meta), HEAP_DESCRIPTOR);
2044
2045 variants->variants[variant].tripipe = (struct mali_shader_meta *) transfer.cpu;
2046 variants->variants[variant].tripipe_gpu = transfer.gpu;
2047
2048 }
2049
2050 /* Select this variant */
2051 variants->active_variant = variant;
2052
2053 struct panfrost_shader_state *shader_state = &variants->variants[variant];
2054 assert(panfrost_variant_matches(ctx, shader_state));
2055
2056 /* Now we have a variant selected, so compile and go */
2057
2058 if (!shader_state->compiled) {
2059 panfrost_shader_compile(ctx, shader_state->tripipe, NULL, JOB_TYPE_TILER, shader_state);
2060 shader_state->compiled = true;
2061 }
2062 }
2063
2064 ctx->dirty |= PAN_DIRTY_FS;
2065 }
2066
2067 static void
2068 panfrost_bind_vs_state(
2069 struct pipe_context *pctx,
2070 void *hwcso)
2071 {
2072 struct panfrost_context *ctx = pan_context(pctx);
2073
2074 ctx->vs = hwcso;
2075
2076 if (hwcso) {
2077 if (!ctx->vs->variants[0].compiled) {
2078 ctx->vs->variants[0].base = hwcso;
2079
2080 /* TODO DRY from above */
2081 struct panfrost_transfer transfer = panfrost_allocate_chunk(ctx, sizeof(struct mali_shader_meta), HEAP_DESCRIPTOR);
2082 ctx->vs->variants[0].tripipe = (struct mali_shader_meta *) transfer.cpu;
2083 ctx->vs->variants[0].tripipe_gpu = transfer.gpu;
2084
2085 panfrost_shader_compile(ctx, ctx->vs->variants[0].tripipe, NULL, JOB_TYPE_VERTEX, &ctx->vs->variants[0]);
2086 ctx->vs->variants[0].compiled = true;
2087 }
2088 }
2089
2090 ctx->dirty |= PAN_DIRTY_VS;
2091 }
2092
2093 static void
2094 panfrost_set_vertex_buffers(
2095 struct pipe_context *pctx,
2096 unsigned start_slot,
2097 unsigned num_buffers,
2098 const struct pipe_vertex_buffer *buffers)
2099 {
2100 struct panfrost_context *ctx = pan_context(pctx);
2101 assert(num_buffers <= PIPE_MAX_ATTRIBS);
2102
2103 /* XXX: Dirty tracking? etc */
2104 if (buffers) {
2105 size_t sz = sizeof(buffers[0]) * num_buffers;
2106 ctx->vertex_buffers = malloc(sz);
2107 ctx->vertex_buffer_count = num_buffers;
2108 memcpy(ctx->vertex_buffers, buffers, sz);
2109 } else {
2110 if (ctx->vertex_buffers) {
2111 free(ctx->vertex_buffers);
2112 ctx->vertex_buffers = NULL;
2113 }
2114
2115 ctx->vertex_buffer_count = 0;
2116 }
2117 }
2118
2119 static void
2120 panfrost_set_constant_buffer(
2121 struct pipe_context *pctx,
2122 enum pipe_shader_type shader, uint index,
2123 const struct pipe_constant_buffer *buf)
2124 {
2125 struct panfrost_context *ctx = pan_context(pctx);
2126 struct panfrost_constant_buffer *pbuf = &ctx->constant_buffer[shader];
2127
2128 size_t sz = buf ? buf->buffer_size : 0;
2129
2130 /* Free previous buffer */
2131
2132 pbuf->dirty = true;
2133 pbuf->size = sz;
2134
2135 if (pbuf->buffer) {
2136 free(pbuf->buffer);
2137 pbuf->buffer = NULL;
2138 }
2139
2140 /* If unbinding, we're done */
2141
2142 if (!buf)
2143 return;
2144
2145 /* Multiple constant buffers not yet supported */
2146 assert(index == 0);
2147
2148 const uint8_t *cpu;
2149
2150 struct panfrost_resource *rsrc = (struct panfrost_resource *) (buf->buffer);
2151
2152 if (rsrc) {
2153 cpu = rsrc->bo->cpu[0];
2154 } else if (buf->user_buffer) {
2155 cpu = buf->user_buffer;
2156 } else {
2157 printf("No constant buffer?\n");
2158 return;
2159 }
2160
2161 /* Copy the constant buffer into the driver context for later upload */
2162
2163 pbuf->buffer = malloc(sz);
2164 memcpy(pbuf->buffer, cpu + buf->buffer_offset, sz);
2165 }
2166
2167 static void
2168 panfrost_set_stencil_ref(
2169 struct pipe_context *pctx,
2170 const struct pipe_stencil_ref *ref)
2171 {
2172 struct panfrost_context *ctx = pan_context(pctx);
2173 ctx->stencil_ref = *ref;
2174
2175 /* Shader core dirty */
2176 ctx->dirty |= PAN_DIRTY_FS;
2177 }
2178
2179 static struct pipe_sampler_view *
2180 panfrost_create_sampler_view(
2181 struct pipe_context *pctx,
2182 struct pipe_resource *texture,
2183 const struct pipe_sampler_view *template)
2184 {
2185 struct panfrost_sampler_view *so = CALLOC_STRUCT(panfrost_sampler_view);
2186 int bytes_per_pixel = util_format_get_blocksize(texture->format);
2187
2188 pipe_reference(NULL, &texture->reference);
2189
2190 struct panfrost_resource *prsrc = (struct panfrost_resource *) texture;
2191
2192 so->base = *template;
2193 so->base.texture = texture;
2194 so->base.reference.count = 1;
2195 so->base.context = pctx;
2196
2197 /* sampler_views correspond to texture descriptors, minus the texture
2198 * (data) itself. So, we serialise the descriptor here and cache it for
2199 * later. */
2200
2201 /* TODO: Other types of textures */
2202 assert(template->target == PIPE_TEXTURE_2D);
2203
2204 /* Make sure it's something with which we're familiar */
2205 assert(bytes_per_pixel >= 1 && bytes_per_pixel <= 4);
2206
2207 /* TODO: Detect from format better */
2208 const struct util_format_description *desc = util_format_description(prsrc->base.format);
2209
2210 unsigned char user_swizzle[4] = {
2211 template->swizzle_r,
2212 template->swizzle_g,
2213 template->swizzle_b,
2214 template->swizzle_a
2215 };
2216
2217 enum mali_format format = panfrost_find_format(desc);
2218
2219 struct mali_texture_descriptor texture_descriptor = {
2220 .width = MALI_POSITIVE(texture->width0),
2221 .height = MALI_POSITIVE(texture->height0),
2222 .depth = MALI_POSITIVE(texture->depth0),
2223
2224 /* TODO: Decode */
2225 .format = {
2226 .swizzle = panfrost_translate_swizzle_4(desc->swizzle),
2227 .format = format,
2228
2229 .usage1 = 0x0,
2230 .is_not_cubemap = 1,
2231
2232 /* 0x11 - regular texture 2d, uncompressed tiled */
2233 /* 0x12 - regular texture 2d, uncompressed linear */
2234 /* 0x1c - AFBC compressed (internally tiled, probably) texture 2D */
2235
2236 .usage2 = prsrc->bo->has_afbc ? 0x1c : (prsrc->bo->tiled ? 0x11 : 0x12),
2237 },
2238
2239 .swizzle = panfrost_translate_swizzle_4(user_swizzle)
2240 };
2241
2242 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2243 assert (template->u.tex.first_level == 0);
2244
2245 texture_descriptor.nr_mipmap_levels = template->u.tex.last_level - template->u.tex.first_level;
2246
2247 so->hw = texture_descriptor;
2248
2249 return (struct pipe_sampler_view *) so;
2250 }
2251
2252 static void
2253 panfrost_set_sampler_views(
2254 struct pipe_context *pctx,
2255 enum pipe_shader_type shader,
2256 unsigned start_slot, unsigned num_views,
2257 struct pipe_sampler_view **views)
2258 {
2259 struct panfrost_context *ctx = pan_context(pctx);
2260
2261 assert(start_slot == 0);
2262
2263 ctx->sampler_view_count[shader] = num_views;
2264 memcpy(ctx->sampler_views[shader], views, num_views * sizeof (void *));
2265
2266 ctx->dirty |= PAN_DIRTY_TEXTURES;
2267 }
2268
2269 static void
2270 panfrost_sampler_view_destroy(
2271 struct pipe_context *pctx,
2272 struct pipe_sampler_view *views)
2273 {
2274 //struct panfrost_context *ctx = pan_context(pctx);
2275
2276 /* TODO */
2277
2278 free(views);
2279 }
2280
2281 static void
2282 panfrost_set_framebuffer_state(struct pipe_context *pctx,
2283 const struct pipe_framebuffer_state *fb)
2284 {
2285 struct panfrost_context *ctx = pan_context(pctx);
2286
2287 /* Flush when switching away from an FBO */
2288
2289 if (!panfrost_is_scanout(ctx)) {
2290 panfrost_flush(pctx, NULL, 0);
2291 }
2292
2293 ctx->pipe_framebuffer.nr_cbufs = fb->nr_cbufs;
2294 ctx->pipe_framebuffer.samples = fb->samples;
2295 ctx->pipe_framebuffer.layers = fb->layers;
2296 ctx->pipe_framebuffer.width = fb->width;
2297 ctx->pipe_framebuffer.height = fb->height;
2298
2299 for (int i = 0; i < PIPE_MAX_COLOR_BUFS; i++) {
2300 struct pipe_surface *cb = i < fb->nr_cbufs ? fb->cbufs[i] : NULL;
2301
2302 /* check if changing cbuf */
2303 if (ctx->pipe_framebuffer.cbufs[i] == cb) continue;
2304
2305 if (cb && (i != 0)) {
2306 printf("XXX: Multiple render targets not supported before t7xx!\n");
2307 assert(0);
2308 }
2309
2310 /* assign new */
2311 pipe_surface_reference(&ctx->pipe_framebuffer.cbufs[i], cb);
2312
2313 if (!cb)
2314 continue;
2315
2316 if (require_sfbd)
2317 ctx->vt_framebuffer_sfbd = panfrost_emit_sfbd(ctx);
2318 else
2319 ctx->vt_framebuffer_mfbd = panfrost_emit_mfbd(ctx);
2320
2321 panfrost_attach_vt_framebuffer(ctx);
2322 panfrost_new_frag_framebuffer(ctx);
2323 panfrost_set_scissor(ctx);
2324
2325 struct panfrost_resource *tex = ((struct panfrost_resource *) ctx->pipe_framebuffer.cbufs[i]->texture);
2326 bool is_scanout = panfrost_is_scanout(ctx);
2327
2328 if (!is_scanout && !tex->bo->has_afbc) {
2329 /* The blob is aggressive about enabling AFBC. As such,
2330 * it's pretty much necessary to use it here, since we
2331 * have no traces of non-compressed FBO. */
2332
2333 panfrost_enable_afbc(ctx, tex, false);
2334 }
2335
2336 if (!is_scanout && !tex->bo->has_checksum) {
2337 /* Enable transaction elimination if we can */
2338 panfrost_enable_checksum(ctx, tex);
2339 }
2340 }
2341
2342 {
2343 struct pipe_surface *zb = fb->zsbuf;
2344
2345 if (ctx->pipe_framebuffer.zsbuf != zb) {
2346 pipe_surface_reference(&ctx->pipe_framebuffer.zsbuf, zb);
2347
2348 if (zb) {
2349 /* FBO has depth */
2350
2351 if (require_sfbd)
2352 ctx->vt_framebuffer_sfbd = panfrost_emit_sfbd(ctx);
2353 else
2354 ctx->vt_framebuffer_mfbd = panfrost_emit_mfbd(ctx);
2355
2356 panfrost_attach_vt_framebuffer(ctx);
2357 panfrost_new_frag_framebuffer(ctx);
2358 panfrost_set_scissor(ctx);
2359
2360 struct panfrost_resource *tex = ((struct panfrost_resource *) ctx->pipe_framebuffer.zsbuf->texture);
2361
2362 if (!tex->bo->has_afbc && !panfrost_is_scanout(ctx))
2363 panfrost_enable_afbc(ctx, tex, true);
2364 }
2365 }
2366 }
2367
2368 /* Force a clear XXX wrong? */
2369 if (ctx->last_clear.color)
2370 panfrost_clear(&ctx->base, ctx->last_clear.buffers, ctx->last_clear.color, ctx->last_clear.depth, ctx->last_clear.stencil);
2371 }
2372
2373 static void *
2374 panfrost_create_blend_state(struct pipe_context *pipe,
2375 const struct pipe_blend_state *blend)
2376 {
2377 struct panfrost_context *ctx = pan_context(pipe);
2378 struct panfrost_blend_state *so = CALLOC_STRUCT(panfrost_blend_state);
2379 so->base = *blend;
2380
2381 /* TODO: The following features are not yet implemented */
2382 assert(!blend->logicop_enable);
2383 assert(!blend->alpha_to_coverage);
2384 assert(!blend->alpha_to_one);
2385
2386 /* Compile the blend state, first as fixed-function if we can */
2387
2388 if (panfrost_make_fixed_blend_mode(&blend->rt[0], &so->equation, blend->rt[0].colormask, &ctx->blend_color))
2389 return so;
2390
2391 /* If we can't, compile a blend shader instead */
2392
2393 panfrost_make_blend_shader(ctx, so, &ctx->blend_color);
2394
2395 return so;
2396 }
2397
2398 static void
2399 panfrost_bind_blend_state(struct pipe_context *pipe,
2400 void *cso)
2401 {
2402 struct panfrost_context *ctx = pan_context(pipe);
2403 struct pipe_blend_state *blend = (struct pipe_blend_state *) cso;
2404 struct panfrost_blend_state *pblend = (struct panfrost_blend_state *) cso;
2405 ctx->blend = pblend;
2406
2407 if (!blend)
2408 return;
2409
2410 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_NO_DITHER, !blend->dither);
2411
2412 /* TODO: Attach color */
2413
2414 /* Shader itself is not dirty, but the shader core is */
2415 ctx->dirty |= PAN_DIRTY_FS;
2416 }
2417
2418 static void
2419 panfrost_delete_blend_state(struct pipe_context *pipe,
2420 void *blend)
2421 {
2422 struct panfrost_blend_state *so = (struct panfrost_blend_state *) blend;
2423
2424 if (so->has_blend_shader) {
2425 printf("Deleting blend state leak blend shaders bytecode\n");
2426 }
2427
2428 free(blend);
2429 }
2430
2431 static void
2432 panfrost_set_blend_color(struct pipe_context *pipe,
2433 const struct pipe_blend_color *blend_color)
2434 {
2435 struct panfrost_context *ctx = pan_context(pipe);
2436
2437 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2438
2439 if (blend_color) {
2440 ctx->blend_color = *blend_color;
2441
2442 /* The blend mode depends on the blend constant color, due to the
2443 * fixed/programmable split. So, we're forced to regenerate the blend
2444 * equation */
2445
2446 /* TODO: Attach color */
2447 }
2448 }
2449
2450 static void *
2451 panfrost_create_depth_stencil_state(struct pipe_context *pipe,
2452 const struct pipe_depth_stencil_alpha_state *depth_stencil)
2453 {
2454 return mem_dup(depth_stencil, sizeof(*depth_stencil));
2455 }
2456
2457 static void
2458 panfrost_bind_depth_stencil_state(struct pipe_context *pipe,
2459 void *cso)
2460 {
2461 struct panfrost_context *ctx = pan_context(pipe);
2462 struct pipe_depth_stencil_alpha_state *depth_stencil = cso;
2463 ctx->depth_stencil = depth_stencil;
2464
2465 if (!depth_stencil)
2466 return;
2467
2468 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2469 * emulated in the fragment shader */
2470
2471 if (depth_stencil->alpha.enabled) {
2472 /* We need to trigger a new shader (maybe) */
2473 ctx->base.bind_fs_state(&ctx->base, ctx->fs);
2474 }
2475
2476 /* Stencil state */
2477 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_STENCIL_TEST, depth_stencil->stencil[0].enabled); /* XXX: which one? */
2478
2479 panfrost_make_stencil_state(&depth_stencil->stencil[0], &ctx->fragment_shader_core.stencil_front);
2480 ctx->fragment_shader_core.stencil_mask_front = depth_stencil->stencil[0].writemask;
2481
2482 panfrost_make_stencil_state(&depth_stencil->stencil[1], &ctx->fragment_shader_core.stencil_back);
2483 ctx->fragment_shader_core.stencil_mask_back = depth_stencil->stencil[1].writemask;
2484
2485 /* Depth state (TODO: Refactor) */
2486 SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_DEPTH_TEST, depth_stencil->depth.enabled);
2487
2488 int func = depth_stencil->depth.enabled ? depth_stencil->depth.func : PIPE_FUNC_ALWAYS;
2489
2490 ctx->fragment_shader_core.unknown2_3 &= ~MALI_DEPTH_FUNC_MASK;
2491 ctx->fragment_shader_core.unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func));
2492
2493 /* Bounds test not implemented */
2494 assert(!depth_stencil->depth.bounds_test);
2495
2496 ctx->dirty |= PAN_DIRTY_FS;
2497 }
2498
2499 static void
2500 panfrost_delete_depth_stencil_state(struct pipe_context *pipe, void *depth)
2501 {
2502 free( depth );
2503 }
2504
2505 static void
2506 panfrost_set_sample_mask(struct pipe_context *pipe,
2507 unsigned sample_mask)
2508 {
2509 }
2510
2511 static void
2512 panfrost_set_clip_state(struct pipe_context *pipe,
2513 const struct pipe_clip_state *clip)
2514 {
2515 //struct panfrost_context *panfrost = pan_context(pipe);
2516 }
2517
2518 static void
2519 panfrost_set_viewport_states(struct pipe_context *pipe,
2520 unsigned start_slot,
2521 unsigned num_viewports,
2522 const struct pipe_viewport_state *viewports)
2523 {
2524 struct panfrost_context *ctx = pan_context(pipe);
2525
2526 assert(start_slot == 0);
2527 assert(num_viewports == 1);
2528
2529 ctx->pipe_viewport = *viewports;
2530
2531 #if 0
2532 /* TODO: What if not centered? */
2533 float w = abs(viewports->scale[0]) * 2.0;
2534 float h = abs(viewports->scale[1]) * 2.0;
2535
2536 ctx->viewport.viewport1[0] = MALI_POSITIVE((int) w);
2537 ctx->viewport.viewport1[1] = MALI_POSITIVE((int) h);
2538 #endif
2539 }
2540
2541 static void
2542 panfrost_set_scissor_states(struct pipe_context *pipe,
2543 unsigned start_slot,
2544 unsigned num_scissors,
2545 const struct pipe_scissor_state *scissors)
2546 {
2547 struct panfrost_context *ctx = pan_context(pipe);
2548
2549 assert(start_slot == 0);
2550 assert(num_scissors == 1);
2551
2552 ctx->scissor = *scissors;
2553
2554 panfrost_set_scissor(ctx);
2555 }
2556
2557 static void
2558 panfrost_set_polygon_stipple(struct pipe_context *pipe,
2559 const struct pipe_poly_stipple *stipple)
2560 {
2561 //struct panfrost_context *panfrost = pan_context(pipe);
2562 }
2563
2564 static void
2565 panfrost_set_active_query_state(struct pipe_context *pipe,
2566 boolean enable)
2567 {
2568 //struct panfrost_context *panfrost = pan_context(pipe);
2569 }
2570
2571 static void
2572 panfrost_destroy(struct pipe_context *pipe)
2573 {
2574 struct panfrost_context *panfrost = pan_context(pipe);
2575
2576 if (panfrost->blitter)
2577 util_blitter_destroy(panfrost->blitter);
2578 }
2579
2580 static struct pipe_query *
2581 panfrost_create_query(struct pipe_context *pipe,
2582 unsigned type,
2583 unsigned index)
2584 {
2585 struct panfrost_query *q = CALLOC_STRUCT(panfrost_query);
2586
2587 q->type = type;
2588 q->index = index;
2589
2590 return (struct pipe_query *) q;
2591 }
2592
2593 static void
2594 panfrost_destroy_query(struct pipe_context *pipe, struct pipe_query *q)
2595 {
2596 FREE(q);
2597 }
2598
2599 static boolean
2600 panfrost_begin_query(struct pipe_context *pipe, struct pipe_query *q)
2601 {
2602 struct panfrost_context *ctx = pan_context(pipe);
2603 struct panfrost_query *query = (struct panfrost_query *) q;
2604
2605 switch (query->type) {
2606 case PIPE_QUERY_OCCLUSION_COUNTER:
2607 case PIPE_QUERY_OCCLUSION_PREDICATE:
2608 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
2609 {
2610 /* Allocate a word for the query results to be stored */
2611 query->transfer = panfrost_allocate_chunk(ctx, sizeof(unsigned), HEAP_DESCRIPTOR);
2612
2613 ctx->occlusion_query = query;
2614
2615 break;
2616 }
2617
2618 default:
2619 fprintf(stderr, "Skipping query %d\n", query->type);
2620 break;
2621 }
2622
2623 return true;
2624 }
2625
2626 static bool
2627 panfrost_end_query(struct pipe_context *pipe, struct pipe_query *q)
2628 {
2629 struct panfrost_context *ctx = pan_context(pipe);
2630 ctx->occlusion_query = NULL;
2631 return true;
2632 }
2633
2634 static boolean
2635 panfrost_get_query_result(struct pipe_context *pipe,
2636 struct pipe_query *q,
2637 boolean wait,
2638 union pipe_query_result *vresult)
2639 {
2640 /* STUB */
2641 struct panfrost_query *query = (struct panfrost_query *) q;
2642
2643 /* We need to flush out the jobs to actually run the counter, TODO
2644 * check wait, TODO wallpaper after if needed */
2645
2646 panfrost_flush(pipe, NULL, PIPE_FLUSH_END_OF_FRAME);
2647
2648 switch (query->type) {
2649 case PIPE_QUERY_OCCLUSION_COUNTER:
2650 case PIPE_QUERY_OCCLUSION_PREDICATE:
2651 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
2652 /* Read back the query results */
2653 unsigned *result = (unsigned *) query->transfer.cpu;
2654 unsigned passed = *result;
2655
2656 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
2657 vresult->u64 = passed;
2658 } else {
2659 vresult->b = !!passed;
2660 }
2661
2662 break;
2663 }
2664 default:
2665 fprintf(stderr, "Skipped query get %d\n", query->type);
2666 break;
2667 }
2668
2669 return true;
2670 }
2671
2672 static void
2673 panfrost_setup_hardware(struct panfrost_context *ctx)
2674 {
2675 struct pipe_context *gallium = (struct pipe_context *) ctx;
2676 struct panfrost_screen *screen = pan_screen(gallium->screen);
2677
2678 for (int i = 0; i < ARRAY_SIZE(ctx->transient_pools); ++i) {
2679 /* Allocate the beginning of the transient pool */
2680 int entry_size = (1 << 22); /* 4MB */
2681
2682 ctx->transient_pools[i].entry_size = entry_size;
2683 ctx->transient_pools[i].entry_count = 1;
2684
2685 ctx->transient_pools[i].entries[0] = (struct panfrost_memory_entry *) pb_slab_alloc(&screen->slabs, entry_size, HEAP_TRANSIENT);
2686 }
2687
2688 screen->driver->allocate_slab(screen, &ctx->scratchpad, 64, false, 0, 0, 0);
2689 screen->driver->allocate_slab(screen, &ctx->varying_mem, 16384, false, 0, 0, 0);
2690 screen->driver->allocate_slab(screen, &ctx->shaders, 4096, true, PAN_ALLOCATE_EXECUTE, 0, 0);
2691 screen->driver->allocate_slab(screen, &ctx->tiler_heap, 32768, false, PAN_ALLOCATE_GROWABLE, 1, 128);
2692 screen->driver->allocate_slab(screen, &ctx->misc_0, 128, false, PAN_ALLOCATE_GROWABLE, 1, 128);
2693
2694 }
2695
2696 /* New context creation, which also does hardware initialisation since I don't
2697 * know the better way to structure this :smirk: */
2698
2699 struct pipe_context *
2700 panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags)
2701 {
2702 struct panfrost_context *ctx = CALLOC_STRUCT(panfrost_context);
2703 memset(ctx, 0, sizeof(*ctx));
2704 struct pipe_context *gallium = (struct pipe_context *) ctx;
2705
2706 gallium->screen = screen;
2707
2708 gallium->destroy = panfrost_destroy;
2709
2710 gallium->set_framebuffer_state = panfrost_set_framebuffer_state;
2711
2712 gallium->flush = panfrost_flush;
2713 gallium->clear = panfrost_clear;
2714 gallium->draw_vbo = panfrost_draw_vbo;
2715
2716 gallium->set_vertex_buffers = panfrost_set_vertex_buffers;
2717 gallium->set_constant_buffer = panfrost_set_constant_buffer;
2718
2719 gallium->set_stencil_ref = panfrost_set_stencil_ref;
2720
2721 gallium->create_sampler_view = panfrost_create_sampler_view;
2722 gallium->set_sampler_views = panfrost_set_sampler_views;
2723 gallium->sampler_view_destroy = panfrost_sampler_view_destroy;
2724
2725 gallium->create_rasterizer_state = panfrost_create_rasterizer_state;
2726 gallium->bind_rasterizer_state = panfrost_bind_rasterizer_state;
2727 gallium->delete_rasterizer_state = panfrost_generic_cso_delete;
2728
2729 gallium->create_vertex_elements_state = panfrost_create_vertex_elements_state;
2730 gallium->bind_vertex_elements_state = panfrost_bind_vertex_elements_state;
2731 gallium->delete_vertex_elements_state = panfrost_delete_vertex_elements_state;
2732
2733 gallium->create_fs_state = panfrost_create_shader_state;
2734 gallium->delete_fs_state = panfrost_delete_shader_state;
2735 gallium->bind_fs_state = panfrost_bind_fs_state;
2736
2737 gallium->create_vs_state = panfrost_create_shader_state;
2738 gallium->delete_vs_state = panfrost_delete_shader_state;
2739 gallium->bind_vs_state = panfrost_bind_vs_state;
2740
2741 gallium->create_sampler_state = panfrost_create_sampler_state;
2742 gallium->delete_sampler_state = panfrost_generic_cso_delete;
2743 gallium->bind_sampler_states = panfrost_bind_sampler_states;
2744
2745 gallium->create_blend_state = panfrost_create_blend_state;
2746 gallium->bind_blend_state = panfrost_bind_blend_state;
2747 gallium->delete_blend_state = panfrost_delete_blend_state;
2748
2749 gallium->set_blend_color = panfrost_set_blend_color;
2750
2751 gallium->create_depth_stencil_alpha_state = panfrost_create_depth_stencil_state;
2752 gallium->bind_depth_stencil_alpha_state = panfrost_bind_depth_stencil_state;
2753 gallium->delete_depth_stencil_alpha_state = panfrost_delete_depth_stencil_state;
2754
2755 gallium->set_sample_mask = panfrost_set_sample_mask;
2756
2757 gallium->set_clip_state = panfrost_set_clip_state;
2758 gallium->set_viewport_states = panfrost_set_viewport_states;
2759 gallium->set_scissor_states = panfrost_set_scissor_states;
2760 gallium->set_polygon_stipple = panfrost_set_polygon_stipple;
2761 gallium->set_active_query_state = panfrost_set_active_query_state;
2762
2763 gallium->create_query = panfrost_create_query;
2764 gallium->destroy_query = panfrost_destroy_query;
2765 gallium->begin_query = panfrost_begin_query;
2766 gallium->end_query = panfrost_end_query;
2767 gallium->get_query_result = panfrost_get_query_result;
2768
2769 panfrost_resource_context_init(gallium);
2770
2771 panfrost_setup_hardware(ctx);
2772
2773 /* XXX: leaks */
2774 gallium->stream_uploader = u_upload_create_default(gallium);
2775 gallium->const_uploader = gallium->stream_uploader;
2776 assert(gallium->stream_uploader);
2777
2778 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2779 ctx->draw_modes = (1 << (PIPE_PRIM_POLYGON + 1)) - 1;
2780
2781 ctx->primconvert = util_primconvert_create(gallium, ctx->draw_modes);
2782
2783 ctx->blitter = util_blitter_create(gallium);
2784 assert(ctx->blitter);
2785
2786 /* Prepare for render! */
2787
2788 panfrost_emit_vertex_payload(ctx);
2789 panfrost_emit_tiler_payload(ctx);
2790 panfrost_invalidate_frame(ctx);
2791 panfrost_viewport(ctx, 0.0, 1.0, 0, 0, ctx->pipe_framebuffer.width, ctx->pipe_framebuffer.height);
2792 panfrost_default_shader_backend(ctx);
2793 panfrost_generate_space_filler_indices();
2794
2795 return gallium;
2796 }