panfrost: XMLify invocations
[mesa.git] / src / gallium / drivers / panfrost / pan_context.c
1 /*
2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 */
26
27 #include <sys/poll.h>
28 #include <errno.h>
29
30 #include "pan_bo.h"
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
34
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
50
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
55 #include "pan_util.h"
56 #include "decode.h"
57 #include "util/pan_lower_framebuffer.h"
58
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch *batch, unsigned vertex_count)
61 {
62 struct panfrost_device *device = pan_device(batch->ctx->base.screen);
63 bool hierarchy = !(device->quirks & MIDGARD_NO_HIER_TILING);
64 struct midgard_tiler_descriptor t = {0};
65 unsigned height = batch->key.height;
66 unsigned width = batch->key.width;
67
68 t.hierarchy_mask =
69 panfrost_choose_hierarchy_mask(width, height, vertex_count, hierarchy);
70
71 /* Compute the polygon header size and use that to offset the body */
72
73 unsigned header_size = panfrost_tiler_header_size(
74 width, height, t.hierarchy_mask, hierarchy);
75
76 t.polygon_list_size = panfrost_tiler_full_size(
77 width, height, t.hierarchy_mask, hierarchy);
78
79 if (vertex_count) {
80 t.polygon_list = panfrost_batch_get_polygon_list(batch,
81 header_size +
82 t.polygon_list_size);
83
84
85 t.heap_start = device->tiler_heap->gpu;
86 t.heap_end = device->tiler_heap->gpu + device->tiler_heap->size;
87 } else {
88 struct panfrost_bo *tiler_dummy;
89
90 tiler_dummy = panfrost_batch_get_tiler_dummy(batch);
91 header_size = MALI_TILER_MINIMUM_HEADER_SIZE;
92
93 /* The tiler is disabled, so don't allow the tiler heap */
94 t.heap_start = tiler_dummy->gpu;
95 t.heap_end = t.heap_start;
96
97 /* Use a dummy polygon list */
98 t.polygon_list = tiler_dummy->gpu;
99
100 /* Disable the tiler */
101 if (hierarchy)
102 t.hierarchy_mask |= MALI_TILER_DISABLED;
103 else {
104 t.hierarchy_mask = MALI_TILER_USER;
105 t.polygon_list_size = MALI_TILER_MINIMUM_HEADER_SIZE + 4;
106
107 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
108 uint32_t *polygon_list_body = (uint32_t *) (tiler_dummy->cpu + header_size);
109 polygon_list_body[0] = 0xa0000000; /* TODO: Just that? */
110 }
111 }
112
113 t.polygon_list_body =
114 t.polygon_list + header_size;
115
116 return t;
117 }
118
119 static void
120 panfrost_clear(
121 struct pipe_context *pipe,
122 unsigned buffers,
123 const struct pipe_scissor_state *scissor_state,
124 const union pipe_color_union *color,
125 double depth, unsigned stencil)
126 {
127 struct panfrost_context *ctx = pan_context(pipe);
128
129 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
130 * the existing batch targeting this FBO has draws. We could probably
131 * avoid that by replacing plain clears by quad-draws with a specific
132 * color/depth/stencil value, thus avoiding the generation of extra
133 * fragment jobs.
134 */
135 struct panfrost_batch *batch = panfrost_get_fresh_batch_for_fbo(ctx);
136 panfrost_batch_clear(batch, buffers, color, depth, stencil);
137 }
138
139 bool
140 panfrost_writes_point_size(struct panfrost_context *ctx)
141 {
142 assert(ctx->shader[PIPE_SHADER_VERTEX]);
143 struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
144
145 return vs->writes_point_size && ctx->active_prim == PIPE_PRIM_POINTS;
146 }
147
148 /* The entire frame is in memory -- send it off to the kernel! */
149
150 void
151 panfrost_flush(
152 struct pipe_context *pipe,
153 struct pipe_fence_handle **fence,
154 unsigned flags)
155 {
156 struct panfrost_context *ctx = pan_context(pipe);
157 struct panfrost_device *dev = pan_device(pipe->screen);
158 uint32_t syncobj = 0;
159
160 if (fence)
161 drmSyncobjCreate(dev->fd, 0, &syncobj);
162
163 /* Submit all pending jobs */
164 panfrost_flush_all_batches(ctx, syncobj);
165
166 if (fence) {
167 struct panfrost_fence *f = panfrost_fence_create(ctx, syncobj);
168 pipe->screen->fence_reference(pipe->screen, fence, NULL);
169 *fence = (struct pipe_fence_handle *)f;
170 }
171
172 if (dev->debug & PAN_DBG_TRACE)
173 pandecode_next_frame();
174 }
175
176 static void
177 panfrost_texture_barrier(struct pipe_context *pipe, unsigned flags)
178 {
179 struct panfrost_context *ctx = pan_context(pipe);
180 panfrost_flush_all_batches(ctx, 0);
181 }
182
183 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
184
185 static int
186 pan_draw_mode(enum pipe_prim_type mode)
187 {
188 switch (mode) {
189 DEFINE_CASE(POINTS);
190 DEFINE_CASE(LINES);
191 DEFINE_CASE(LINE_LOOP);
192 DEFINE_CASE(LINE_STRIP);
193 DEFINE_CASE(TRIANGLES);
194 DEFINE_CASE(TRIANGLE_STRIP);
195 DEFINE_CASE(TRIANGLE_FAN);
196 DEFINE_CASE(QUADS);
197 DEFINE_CASE(QUAD_STRIP);
198 DEFINE_CASE(POLYGON);
199
200 default:
201 unreachable("Invalid draw mode");
202 }
203 }
204
205 #undef DEFINE_CASE
206
207 static bool
208 panfrost_scissor_culls_everything(struct panfrost_context *ctx)
209 {
210 const struct pipe_scissor_state *ss = &ctx->scissor;
211
212 /* Check if we're scissoring at all */
213
214 if (!ctx->rasterizer->base.scissor)
215 return false;
216
217 return (ss->minx == ss->maxx) || (ss->miny == ss->maxy);
218 }
219
220 /* Count generated primitives (when there is no geom/tess shaders) for
221 * transform feedback */
222
223 static void
224 panfrost_statistics_record(
225 struct panfrost_context *ctx,
226 const struct pipe_draw_info *info)
227 {
228 if (!ctx->active_queries)
229 return;
230
231 uint32_t prims = u_prims_for_vertices(info->mode, info->count);
232 ctx->prims_generated += prims;
233
234 if (!ctx->streamout.num_targets)
235 return;
236
237 ctx->tf_prims_generated += prims;
238 }
239
240 static void
241 panfrost_update_streamout_offsets(struct panfrost_context *ctx)
242 {
243 for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) {
244 unsigned count;
245
246 count = u_stream_outputs_for_vertices(ctx->active_prim,
247 ctx->vertex_count);
248 ctx->streamout.offsets[i] += count;
249 }
250 }
251
252 static inline void
253 pan_emit_draw_descs(struct panfrost_batch *batch,
254 struct MALI_DRAW *d, enum pipe_shader_type st)
255 {
256 d->offset_start = batch->ctx->offset_start;
257 d->instances = batch->ctx->instance_count > 1 ?
258 batch->ctx->padded_count : 1;
259
260 d->uniform_buffers = panfrost_emit_const_buf(batch, st, &d->push_uniforms);
261 d->textures = panfrost_emit_texture_descriptors(batch, st);
262 d->samplers = panfrost_emit_sampler_descriptors(batch, st);
263 }
264
265 static enum mali_index_type
266 panfrost_translate_index_size(unsigned size)
267 {
268 switch (size) {
269 case 1: return MALI_INDEX_TYPE_UINT8;
270 case 2: return MALI_INDEX_TYPE_UINT16;
271 case 4: return MALI_INDEX_TYPE_UINT32;
272 default: unreachable("Invalid index size");
273 }
274 }
275
276 static void
277 panfrost_draw_vbo(
278 struct pipe_context *pipe,
279 const struct pipe_draw_info *info)
280 {
281 struct panfrost_context *ctx = pan_context(pipe);
282 struct panfrost_device *device = pan_device(ctx->base.screen);
283
284 /* First of all, check the scissor to see if anything is drawn at all.
285 * If it's not, we drop the draw (mostly a conformance issue;
286 * well-behaved apps shouldn't hit this) */
287
288 if (panfrost_scissor_culls_everything(ctx))
289 return;
290
291 int mode = info->mode;
292
293 /* Fallback unsupported restart index */
294 unsigned primitive_index = (1 << (info->index_size * 8)) - 1;
295
296 if (info->primitive_restart && info->index_size
297 && info->restart_index != primitive_index) {
298 util_draw_vbo_without_prim_restart(pipe, info);
299 return;
300 }
301
302 /* Fallback for unsupported modes */
303
304 assert(ctx->rasterizer != NULL);
305
306 if (!(ctx->draw_modes & (1 << mode))) {
307 if (info->count < 4) {
308 /* Degenerate case? */
309 return;
310 }
311
312 util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base);
313 util_primconvert_draw_vbo(ctx->primconvert, info);
314 return;
315 }
316
317 /* Now that we have a guaranteed terminating path, find the job. */
318
319 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
320 panfrost_batch_set_requirements(batch);
321
322 /* Take into account a negative bias */
323 ctx->vertex_count = info->count + abs(info->index_bias);
324 ctx->instance_count = info->instance_count;
325 ctx->active_prim = info->mode;
326
327 struct mali_vertex_tiler_prefix vertex_prefix = { 0 }, tiler_prefix = { 0 };
328 struct mali_draw_packed vertex_postfix, tiler_postfix;
329 struct mali_primitive_packed primitive;
330 struct mali_invocation_packed invocation;
331 union midgard_primitive_size primitive_size;
332 unsigned vertex_count = ctx->vertex_count;
333
334 mali_ptr shared_mem = (device->quirks & IS_BIFROST) ?
335 panfrost_vt_emit_shared_memory(batch) :
336 panfrost_batch_reserve_framebuffer(batch);
337
338 struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
339 unsigned min_index = 0, max_index = 0;
340
341 pan_pack(&primitive, PRIMITIVE, cfg) {
342 cfg.draw_mode = pan_draw_mode(mode);
343 cfg.point_size_array = panfrost_writes_point_size(ctx);
344 cfg.first_provoking_vertex = rast->flatshade_first;
345 cfg.primitive_restart = info->primitive_restart;
346 cfg.unknown_3 = 6;
347
348 if (info->index_size) {
349 cfg.index_type = panfrost_translate_index_size(info->index_size);
350 cfg.indices = panfrost_get_index_buffer_bounded(ctx, info,
351 &min_index, &max_index);
352
353 /* Use the corresponding values */
354 vertex_count = max_index - min_index + 1;
355 ctx->offset_start = min_index + info->index_bias;
356
357 cfg.base_vertex_offset = -min_index;
358 cfg.index_count = info->count;
359 } else {
360 ctx->offset_start = info->start;
361 cfg.index_count = ctx->vertex_count;
362 }
363 }
364
365 vertex_prefix.primitive.opaque[0] = (5) << 26; /* XXX */
366 memcpy(&tiler_prefix.primitive, &primitive, sizeof(primitive));
367
368 /* Encode the padded vertex count */
369
370 if (info->instance_count > 1)
371 ctx->padded_count = panfrost_padded_vertex_count(vertex_count);
372 else
373 ctx->padded_count = vertex_count;
374
375 panfrost_statistics_record(ctx, info);
376
377 panfrost_pack_work_groups_compute(&invocation,
378 1, vertex_count, info->instance_count,
379 1, 1, 1, true);
380
381 vertex_prefix.invocation = invocation;
382 tiler_prefix.invocation = invocation;
383
384 /* Emit all sort of descriptors. */
385 mali_ptr varyings = 0, vs_vary = 0, fs_vary = 0, pos = 0, psiz = 0;
386
387 panfrost_emit_varying_descriptor(batch,
388 ctx->padded_count *
389 ctx->instance_count,
390 &vs_vary, &fs_vary, &varyings,
391 &pos, &psiz);
392
393 pan_pack(&vertex_postfix, DRAW, cfg) {
394 cfg.unknown_1 = (device->quirks & IS_BIFROST) ? 0x2 : 0x6;
395 cfg.state = panfrost_emit_compute_shader_meta(batch, PIPE_SHADER_VERTEX);
396 cfg.attributes = panfrost_emit_vertex_data(batch, &cfg.attribute_buffers);
397 cfg.varyings = vs_vary;
398 cfg.varying_buffers = varyings;
399 cfg.shared = shared_mem;
400 pan_emit_draw_descs(batch, &cfg, PIPE_SHADER_VERTEX);
401 }
402
403 pan_pack(&tiler_postfix, DRAW, cfg) {
404 cfg.unknown_1 = (device->quirks & IS_BIFROST) ? 0x3 : 0x7;
405 cfg.front_face_ccw = rast->front_ccw;
406 cfg.cull_front_face = rast->cull_face & PIPE_FACE_FRONT;
407 cfg.cull_back_face = rast->cull_face & PIPE_FACE_BACK;
408 cfg.position = pos;
409 cfg.state = panfrost_emit_frag_shader_meta(batch);
410 cfg.viewport = panfrost_emit_viewport(batch);
411 cfg.varyings = fs_vary;
412 cfg.varying_buffers = varyings;
413 cfg.shared = shared_mem;
414
415 pan_emit_draw_descs(batch, &cfg, PIPE_SHADER_FRAGMENT);
416
417 if (ctx->occlusion_query) {
418 cfg.occlusion_query = MALI_OCCLUSION_MODE_PREDICATE;
419 cfg.occlusion = ctx->occlusion_query->bo->gpu;
420 panfrost_batch_add_bo(ctx->batch, ctx->occlusion_query->bo,
421 PAN_BO_ACCESS_SHARED |
422 PAN_BO_ACCESS_RW |
423 PAN_BO_ACCESS_FRAGMENT);
424 }
425 }
426
427 primitive_size.pointer = psiz;
428 panfrost_vt_update_primitive_size(ctx, info->mode == PIPE_PRIM_POINTS, &primitive_size);
429
430 /* Fire off the draw itself */
431 panfrost_emit_vertex_tiler_jobs(batch, &vertex_prefix, &vertex_postfix,
432 &tiler_prefix, &tiler_postfix,
433 &primitive_size);
434
435 /* Adjust the batch stack size based on the new shader stack sizes. */
436 panfrost_batch_adjust_stack_size(batch);
437
438 /* Increment transform feedback offsets */
439 panfrost_update_streamout_offsets(ctx);
440 }
441
442 /* CSO state */
443
444 static void
445 panfrost_generic_cso_delete(struct pipe_context *pctx, void *hwcso)
446 {
447 free(hwcso);
448 }
449
450 static void *
451 panfrost_create_rasterizer_state(
452 struct pipe_context *pctx,
453 const struct pipe_rasterizer_state *cso)
454 {
455 struct panfrost_rasterizer *so = CALLOC_STRUCT(panfrost_rasterizer);
456
457 so->base = *cso;
458
459 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
460 assert(cso->offset_clamp == 0.0);
461
462 return so;
463 }
464
465 static void
466 panfrost_bind_rasterizer_state(
467 struct pipe_context *pctx,
468 void *hwcso)
469 {
470 struct panfrost_context *ctx = pan_context(pctx);
471 ctx->rasterizer = hwcso;
472 }
473
474 static void *
475 panfrost_create_vertex_elements_state(
476 struct pipe_context *pctx,
477 unsigned num_elements,
478 const struct pipe_vertex_element *elements)
479 {
480 struct panfrost_vertex_state *so = CALLOC_STRUCT(panfrost_vertex_state);
481 struct panfrost_device *dev = pan_device(pctx->screen);
482
483 so->num_elements = num_elements;
484 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
485
486 for (int i = 0; i < num_elements; ++i) {
487 enum pipe_format fmt = elements[i].src_format;
488 const struct util_format_description *desc = util_format_description(fmt);
489 unsigned swizzle = 0;
490 if (dev->quirks & HAS_SWIZZLES)
491 swizzle = panfrost_translate_swizzle_4(desc->swizzle);
492 else
493 swizzle = panfrost_bifrost_swizzle(desc->nr_channels);
494
495 enum mali_format hw_format = panfrost_pipe_format_table[desc->format].hw;
496 so->formats[i] = (hw_format << 12) | swizzle;
497 assert(hw_format);
498 }
499
500 /* Let's also prepare vertex builtins */
501 if (dev->quirks & HAS_SWIZZLES)
502 so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
503 else
504 so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
505
506 if (dev->quirks & HAS_SWIZZLES)
507 so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
508 else
509 so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
510
511 return so;
512 }
513
514 static void
515 panfrost_bind_vertex_elements_state(
516 struct pipe_context *pctx,
517 void *hwcso)
518 {
519 struct panfrost_context *ctx = pan_context(pctx);
520 ctx->vertex = hwcso;
521 }
522
523 static void *
524 panfrost_create_shader_state(
525 struct pipe_context *pctx,
526 const struct pipe_shader_state *cso,
527 enum pipe_shader_type stage)
528 {
529 struct panfrost_shader_variants *so = CALLOC_STRUCT(panfrost_shader_variants);
530 struct panfrost_device *dev = pan_device(pctx->screen);
531 so->base = *cso;
532
533 /* Token deep copy to prevent memory corruption */
534
535 if (cso->type == PIPE_SHADER_IR_TGSI)
536 so->base.tokens = tgsi_dup_tokens(so->base.tokens);
537
538 /* Precompile for shader-db if we need to */
539 if (unlikely((dev->debug & PAN_DBG_PRECOMPILE) && cso->type == PIPE_SHADER_IR_NIR)) {
540 struct panfrost_context *ctx = pan_context(pctx);
541
542 struct panfrost_shader_state state = { 0 };
543 uint64_t outputs_written;
544
545 panfrost_shader_compile(ctx, PIPE_SHADER_IR_NIR,
546 so->base.ir.nir,
547 tgsi_processor_to_shader_stage(stage),
548 &state, &outputs_written);
549 }
550
551 return so;
552 }
553
554 static void
555 panfrost_delete_shader_state(
556 struct pipe_context *pctx,
557 void *so)
558 {
559 struct panfrost_shader_variants *cso = (struct panfrost_shader_variants *) so;
560
561 if (cso->base.type == PIPE_SHADER_IR_TGSI) {
562 /* TODO: leaks TGSI tokens! */
563 }
564
565 for (unsigned i = 0; i < cso->variant_count; ++i) {
566 struct panfrost_shader_state *shader_state = &cso->variants[i];
567 panfrost_bo_unreference(shader_state->bo);
568
569 if (shader_state->upload.rsrc)
570 pipe_resource_reference(&shader_state->upload.rsrc, NULL);
571
572 shader_state->bo = NULL;
573 }
574 free(cso->variants);
575
576
577 free(so);
578 }
579
580 static void *
581 panfrost_create_sampler_state(
582 struct pipe_context *pctx,
583 const struct pipe_sampler_state *cso)
584 {
585 struct panfrost_sampler_state *so = CALLOC_STRUCT(panfrost_sampler_state);
586 struct panfrost_device *device = pan_device(pctx->screen);
587
588 so->base = *cso;
589
590 if (device->quirks & IS_BIFROST)
591 panfrost_sampler_desc_init_bifrost(cso, (struct mali_bifrost_sampler_packed *) &so->hw);
592 else
593 panfrost_sampler_desc_init(cso, &so->hw);
594
595 return so;
596 }
597
598 static void
599 panfrost_bind_sampler_states(
600 struct pipe_context *pctx,
601 enum pipe_shader_type shader,
602 unsigned start_slot, unsigned num_sampler,
603 void **sampler)
604 {
605 assert(start_slot == 0);
606
607 struct panfrost_context *ctx = pan_context(pctx);
608
609 /* XXX: Should upload, not just copy? */
610 ctx->sampler_count[shader] = num_sampler;
611 memcpy(ctx->samplers[shader], sampler, num_sampler * sizeof (void *));
612 }
613
614 static bool
615 panfrost_variant_matches(
616 struct panfrost_context *ctx,
617 struct panfrost_shader_state *variant,
618 enum pipe_shader_type type)
619 {
620 struct panfrost_device *dev = pan_device(ctx->base.screen);
621
622 if (variant->outputs_read) {
623 struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
624
625 unsigned i;
626 BITSET_FOREACH_SET(i, &variant->outputs_read, 8) {
627 enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
628
629 if ((fb->nr_cbufs > i) && fb->cbufs[i])
630 fmt = fb->cbufs[i]->format;
631
632 const struct util_format_description *desc =
633 util_format_description(fmt);
634
635 if (pan_format_class_load(desc, dev->quirks) == PAN_FORMAT_NATIVE)
636 fmt = PIPE_FORMAT_NONE;
637
638 if (variant->rt_formats[i] != fmt)
639 return false;
640 }
641 }
642
643 /* Otherwise, we're good to go */
644 return true;
645 }
646
647 /**
648 * Fix an uncompiled shader's stream output info, and produce a bitmask
649 * of which VARYING_SLOT_* are captured for stream output.
650 *
651 * Core Gallium stores output->register_index as a "slot" number, where
652 * slots are assigned consecutively to all outputs in info->outputs_written.
653 * This naive packing of outputs doesn't work for us - we too have slots,
654 * but the layout is defined by the VUE map, which we won't have until we
655 * compile a specific shader variant. So, we remap these and simply store
656 * VARYING_SLOT_* in our copy's output->register_index fields.
657 *
658 * We then produce a bitmask of outputs which are used for SO.
659 *
660 * Implementation from iris.
661 */
662
663 static uint64_t
664 update_so_info(struct pipe_stream_output_info *so_info,
665 uint64_t outputs_written)
666 {
667 uint64_t so_outputs = 0;
668 uint8_t reverse_map[64] = {0};
669 unsigned slot = 0;
670
671 while (outputs_written)
672 reverse_map[slot++] = u_bit_scan64(&outputs_written);
673
674 for (unsigned i = 0; i < so_info->num_outputs; i++) {
675 struct pipe_stream_output *output = &so_info->output[i];
676
677 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
678 output->register_index = reverse_map[output->register_index];
679
680 so_outputs |= 1ull << output->register_index;
681 }
682
683 return so_outputs;
684 }
685
686 static void
687 panfrost_bind_shader_state(
688 struct pipe_context *pctx,
689 void *hwcso,
690 enum pipe_shader_type type)
691 {
692 struct panfrost_context *ctx = pan_context(pctx);
693 struct panfrost_device *dev = pan_device(ctx->base.screen);
694 ctx->shader[type] = hwcso;
695
696 if (!hwcso) return;
697
698 /* Match the appropriate variant */
699
700 signed variant = -1;
701 struct panfrost_shader_variants *variants = (struct panfrost_shader_variants *) hwcso;
702
703 for (unsigned i = 0; i < variants->variant_count; ++i) {
704 if (panfrost_variant_matches(ctx, &variants->variants[i], type)) {
705 variant = i;
706 break;
707 }
708 }
709
710 if (variant == -1) {
711 /* No variant matched, so create a new one */
712 variant = variants->variant_count++;
713
714 if (variants->variant_count > variants->variant_space) {
715 unsigned old_space = variants->variant_space;
716
717 variants->variant_space *= 2;
718 if (variants->variant_space == 0)
719 variants->variant_space = 1;
720
721 /* Arbitrary limit to stop runaway programs from
722 * creating an unbounded number of shader variants. */
723 assert(variants->variant_space < 1024);
724
725 unsigned msize = sizeof(struct panfrost_shader_state);
726 variants->variants = realloc(variants->variants,
727 variants->variant_space * msize);
728
729 memset(&variants->variants[old_space], 0,
730 (variants->variant_space - old_space) * msize);
731 }
732
733 struct panfrost_shader_state *v =
734 &variants->variants[variant];
735
736 if (type == PIPE_SHADER_FRAGMENT) {
737 struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
738 for (unsigned i = 0; i < fb->nr_cbufs; ++i) {
739 enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
740
741 if ((fb->nr_cbufs > i) && fb->cbufs[i])
742 fmt = fb->cbufs[i]->format;
743
744 const struct util_format_description *desc =
745 util_format_description(fmt);
746
747 if (pan_format_class_load(desc, dev->quirks) == PAN_FORMAT_NATIVE)
748 fmt = PIPE_FORMAT_NONE;
749
750 v->rt_formats[i] = fmt;
751 }
752 }
753 }
754
755 /* Select this variant */
756 variants->active_variant = variant;
757
758 struct panfrost_shader_state *shader_state = &variants->variants[variant];
759 assert(panfrost_variant_matches(ctx, shader_state, type));
760
761 /* We finally have a variant, so compile it */
762
763 if (!shader_state->compiled) {
764 uint64_t outputs_written = 0;
765
766 panfrost_shader_compile(ctx, variants->base.type,
767 variants->base.type == PIPE_SHADER_IR_NIR ?
768 variants->base.ir.nir :
769 variants->base.tokens,
770 tgsi_processor_to_shader_stage(type),
771 shader_state,
772 &outputs_written);
773
774 shader_state->compiled = true;
775
776 /* Fixup the stream out information, since what Gallium returns
777 * normally is mildly insane */
778
779 shader_state->stream_output = variants->base.stream_output;
780 shader_state->so_mask =
781 update_so_info(&shader_state->stream_output, outputs_written);
782 }
783 }
784
785 static void *
786 panfrost_create_vs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
787 {
788 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
789 }
790
791 static void *
792 panfrost_create_fs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
793 {
794 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
795 }
796
797 static void
798 panfrost_bind_vs_state(struct pipe_context *pctx, void *hwcso)
799 {
800 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
801 }
802
803 static void
804 panfrost_bind_fs_state(struct pipe_context *pctx, void *hwcso)
805 {
806 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
807 }
808
809 static void
810 panfrost_set_vertex_buffers(
811 struct pipe_context *pctx,
812 unsigned start_slot,
813 unsigned num_buffers,
814 const struct pipe_vertex_buffer *buffers)
815 {
816 struct panfrost_context *ctx = pan_context(pctx);
817
818 util_set_vertex_buffers_mask(ctx->vertex_buffers, &ctx->vb_mask, buffers, start_slot, num_buffers);
819 }
820
821 static void
822 panfrost_set_constant_buffer(
823 struct pipe_context *pctx,
824 enum pipe_shader_type shader, uint index,
825 const struct pipe_constant_buffer *buf)
826 {
827 struct panfrost_context *ctx = pan_context(pctx);
828 struct panfrost_constant_buffer *pbuf = &ctx->constant_buffer[shader];
829
830 util_copy_constant_buffer(&pbuf->cb[index], buf);
831
832 unsigned mask = (1 << index);
833
834 if (unlikely(!buf)) {
835 pbuf->enabled_mask &= ~mask;
836 pbuf->dirty_mask &= ~mask;
837 return;
838 }
839
840 pbuf->enabled_mask |= mask;
841 pbuf->dirty_mask |= mask;
842 }
843
844 static void
845 panfrost_set_stencil_ref(
846 struct pipe_context *pctx,
847 const struct pipe_stencil_ref *ref)
848 {
849 struct panfrost_context *ctx = pan_context(pctx);
850 ctx->stencil_ref = *ref;
851 }
852
853 void
854 panfrost_create_sampler_view_bo(struct panfrost_sampler_view *so,
855 struct pipe_context *pctx,
856 struct pipe_resource *texture)
857 {
858 struct panfrost_device *device = pan_device(pctx->screen);
859 struct panfrost_resource *prsrc = (struct panfrost_resource *)texture;
860 enum pipe_format format = so->base.format;
861 assert(prsrc->bo);
862
863 /* Format to access the stencil portion of a Z32_S8 texture */
864 if (format == PIPE_FORMAT_X32_S8X24_UINT) {
865 assert(prsrc->separate_stencil);
866 texture = &prsrc->separate_stencil->base;
867 prsrc = (struct panfrost_resource *)texture;
868 format = texture->format;
869 }
870
871 const struct util_format_description *desc = util_format_description(format);
872
873 bool fake_rgtc = !panfrost_supports_compressed_format(device, MALI_BC4_UNORM);
874
875 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC && fake_rgtc) {
876 if (desc->is_snorm)
877 format = PIPE_FORMAT_R8G8B8A8_SNORM;
878 else
879 format = PIPE_FORMAT_R8G8B8A8_UNORM;
880 desc = util_format_description(format);
881 }
882
883 so->texture_bo = prsrc->bo->gpu;
884 so->modifier = prsrc->modifier;
885
886 unsigned char user_swizzle[4] = {
887 so->base.swizzle_r,
888 so->base.swizzle_g,
889 so->base.swizzle_b,
890 so->base.swizzle_a
891 };
892
893 /* In the hardware, array_size refers specifically to array textures,
894 * whereas in Gallium, it also covers cubemaps */
895
896 unsigned array_size = texture->array_size;
897 unsigned depth = texture->depth0;
898
899 if (so->base.target == PIPE_TEXTURE_CUBE) {
900 /* TODO: Cubemap arrays */
901 assert(array_size == 6);
902 array_size /= 6;
903 }
904
905 /* MSAA only supported for 2D textures (and 2D texture arrays via an
906 * extension currently unimplemented */
907
908 if (so->base.target == PIPE_TEXTURE_2D) {
909 assert(depth == 1);
910 depth = texture->nr_samples;
911 } else {
912 /* MSAA only supported for 2D textures */
913 assert(texture->nr_samples <= 1);
914 }
915
916 enum mali_texture_dimension type =
917 panfrost_translate_texture_dimension(so->base.target);
918
919 if (device->quirks & IS_BIFROST) {
920 unsigned char composed_swizzle[4];
921 util_format_compose_swizzles(desc->swizzle, user_swizzle, composed_swizzle);
922
923 unsigned size = panfrost_estimate_texture_payload_size(
924 so->base.u.tex.first_level,
925 so->base.u.tex.last_level,
926 so->base.u.tex.first_layer,
927 so->base.u.tex.last_layer,
928 texture->nr_samples,
929 type, prsrc->modifier);
930
931 so->bo = panfrost_bo_create(device, size, 0);
932
933 panfrost_new_texture_bifrost(
934 &so->bifrost_descriptor,
935 texture->width0, texture->height0,
936 depth, array_size,
937 format,
938 type, prsrc->modifier,
939 so->base.u.tex.first_level,
940 so->base.u.tex.last_level,
941 so->base.u.tex.first_layer,
942 so->base.u.tex.last_layer,
943 texture->nr_samples,
944 prsrc->cubemap_stride,
945 panfrost_translate_swizzle_4(composed_swizzle),
946 prsrc->bo->gpu,
947 prsrc->slices,
948 so->bo);
949 } else {
950 unsigned size = panfrost_estimate_texture_payload_size(
951 so->base.u.tex.first_level,
952 so->base.u.tex.last_level,
953 so->base.u.tex.first_layer,
954 so->base.u.tex.last_layer,
955 texture->nr_samples,
956 type, prsrc->modifier);
957 size += MALI_MIDGARD_TEXTURE_LENGTH;
958
959 so->bo = panfrost_bo_create(device, size, 0);
960
961 panfrost_new_texture(
962 so->bo->cpu,
963 texture->width0, texture->height0,
964 depth, array_size,
965 format,
966 type, prsrc->modifier,
967 so->base.u.tex.first_level,
968 so->base.u.tex.last_level,
969 so->base.u.tex.first_layer,
970 so->base.u.tex.last_layer,
971 texture->nr_samples,
972 prsrc->cubemap_stride,
973 panfrost_translate_swizzle_4(user_swizzle),
974 prsrc->bo->gpu,
975 prsrc->slices);
976 }
977 }
978
979 static struct pipe_sampler_view *
980 panfrost_create_sampler_view(
981 struct pipe_context *pctx,
982 struct pipe_resource *texture,
983 const struct pipe_sampler_view *template)
984 {
985 struct panfrost_sampler_view *so = rzalloc(pctx, struct panfrost_sampler_view);
986
987 pipe_reference(NULL, &texture->reference);
988
989 so->base = *template;
990 so->base.texture = texture;
991 so->base.reference.count = 1;
992 so->base.context = pctx;
993
994 panfrost_create_sampler_view_bo(so, pctx, texture);
995
996 return (struct pipe_sampler_view *) so;
997 }
998
999 static void
1000 panfrost_set_sampler_views(
1001 struct pipe_context *pctx,
1002 enum pipe_shader_type shader,
1003 unsigned start_slot, unsigned num_views,
1004 struct pipe_sampler_view **views)
1005 {
1006 struct panfrost_context *ctx = pan_context(pctx);
1007 unsigned new_nr = 0;
1008 unsigned i;
1009
1010 assert(start_slot == 0);
1011
1012 for (i = 0; i < num_views; ++i) {
1013 if (views[i])
1014 new_nr = i + 1;
1015 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
1016 views[i]);
1017 }
1018
1019 for (; i < ctx->sampler_view_count[shader]; i++) {
1020 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
1021 NULL);
1022 }
1023 ctx->sampler_view_count[shader] = new_nr;
1024 }
1025
1026 static void
1027 panfrost_sampler_view_destroy(
1028 struct pipe_context *pctx,
1029 struct pipe_sampler_view *pview)
1030 {
1031 struct panfrost_sampler_view *view = (struct panfrost_sampler_view *) pview;
1032
1033 pipe_resource_reference(&pview->texture, NULL);
1034 panfrost_bo_unreference(view->bo);
1035 ralloc_free(view);
1036 }
1037
1038 static void
1039 panfrost_set_shader_buffers(
1040 struct pipe_context *pctx,
1041 enum pipe_shader_type shader,
1042 unsigned start, unsigned count,
1043 const struct pipe_shader_buffer *buffers,
1044 unsigned writable_bitmask)
1045 {
1046 struct panfrost_context *ctx = pan_context(pctx);
1047
1048 util_set_shader_buffers_mask(ctx->ssbo[shader], &ctx->ssbo_mask[shader],
1049 buffers, start, count);
1050 }
1051
1052 static void
1053 panfrost_set_framebuffer_state(struct pipe_context *pctx,
1054 const struct pipe_framebuffer_state *fb)
1055 {
1056 struct panfrost_context *ctx = pan_context(pctx);
1057
1058 util_copy_framebuffer_state(&ctx->pipe_framebuffer, fb);
1059 ctx->batch = NULL;
1060
1061 /* We may need to generate a new variant if the fragment shader is
1062 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1063 struct panfrost_shader_variants *fs = ctx->shader[PIPE_SHADER_FRAGMENT];
1064
1065 if (fs && fs->variant_count && fs->variants[fs->active_variant].outputs_read)
1066 ctx->base.bind_fs_state(&ctx->base, fs);
1067 }
1068
1069 static inline unsigned
1070 pan_pipe_to_stencil_op(enum pipe_stencil_op in)
1071 {
1072 switch (in) {
1073 case PIPE_STENCIL_OP_KEEP: return MALI_STENCIL_OP_KEEP;
1074 case PIPE_STENCIL_OP_ZERO: return MALI_STENCIL_OP_ZERO;
1075 case PIPE_STENCIL_OP_REPLACE: return MALI_STENCIL_OP_REPLACE;
1076 case PIPE_STENCIL_OP_INCR: return MALI_STENCIL_OP_INCR_SAT;
1077 case PIPE_STENCIL_OP_DECR: return MALI_STENCIL_OP_DECR_SAT;
1078 case PIPE_STENCIL_OP_INCR_WRAP: return MALI_STENCIL_OP_INCR_WRAP;
1079 case PIPE_STENCIL_OP_DECR_WRAP: return MALI_STENCIL_OP_DECR_WRAP;
1080 case PIPE_STENCIL_OP_INVERT: return MALI_STENCIL_OP_INVERT;
1081 default: unreachable("Invalid stencil op");
1082 }
1083 }
1084
1085 static inline void
1086 pan_pipe_to_stencil(const struct pipe_stencil_state *in, void *out)
1087 {
1088 pan_pack(out, STENCIL, cfg) {
1089 cfg.mask = in->valuemask;
1090 cfg.compare_function = panfrost_translate_compare_func(in->func);
1091 cfg.stencil_fail = pan_pipe_to_stencil_op(in->fail_op);
1092 cfg.depth_fail = pan_pipe_to_stencil_op(in->zfail_op);
1093 cfg.depth_pass = pan_pipe_to_stencil_op(in->zpass_op);
1094 }
1095 }
1096
1097 static void *
1098 panfrost_create_depth_stencil_state(struct pipe_context *pipe,
1099 const struct pipe_depth_stencil_alpha_state *zsa)
1100 {
1101 struct panfrost_zsa_state *so = CALLOC_STRUCT(panfrost_zsa_state);
1102 so->base = *zsa;
1103
1104 pan_pipe_to_stencil(&zsa->stencil[0], &so->stencil_front);
1105 so->stencil_mask_front = zsa->stencil[0].writemask;
1106
1107 if (zsa->stencil[1].enabled) {
1108 pan_pipe_to_stencil(&zsa->stencil[1], &so->stencil_back);
1109 so->stencil_mask_back = zsa->stencil[1].writemask;
1110 } else {
1111 so->stencil_back = so->stencil_front;
1112 so->stencil_mask_back = so->stencil_mask_front;
1113 }
1114
1115 /* Alpha lowered by frontend */
1116 assert(!zsa->alpha.enabled);
1117
1118 /* TODO: Bounds test should be easy */
1119 assert(!zsa->depth.bounds_test);
1120
1121 return so;
1122 }
1123
1124 static void
1125 panfrost_bind_depth_stencil_state(struct pipe_context *pipe,
1126 void *cso)
1127 {
1128 struct panfrost_context *ctx = pan_context(pipe);
1129 ctx->depth_stencil = cso;
1130 }
1131
1132 static void
1133 panfrost_delete_depth_stencil_state(struct pipe_context *pipe, void *depth)
1134 {
1135 free( depth );
1136 }
1137
1138 static void
1139 panfrost_set_sample_mask(struct pipe_context *pipe,
1140 unsigned sample_mask)
1141 {
1142 struct panfrost_context *ctx = pan_context(pipe);
1143 ctx->sample_mask = sample_mask;
1144 }
1145
1146 static void
1147 panfrost_set_min_samples(struct pipe_context *pipe,
1148 unsigned min_samples)
1149 {
1150 struct panfrost_context *ctx = pan_context(pipe);
1151 ctx->min_samples = min_samples;
1152 }
1153
1154
1155 static void
1156 panfrost_set_clip_state(struct pipe_context *pipe,
1157 const struct pipe_clip_state *clip)
1158 {
1159 //struct panfrost_context *panfrost = pan_context(pipe);
1160 }
1161
1162 static void
1163 panfrost_set_viewport_states(struct pipe_context *pipe,
1164 unsigned start_slot,
1165 unsigned num_viewports,
1166 const struct pipe_viewport_state *viewports)
1167 {
1168 struct panfrost_context *ctx = pan_context(pipe);
1169
1170 assert(start_slot == 0);
1171 assert(num_viewports == 1);
1172
1173 ctx->pipe_viewport = *viewports;
1174 }
1175
1176 static void
1177 panfrost_set_scissor_states(struct pipe_context *pipe,
1178 unsigned start_slot,
1179 unsigned num_scissors,
1180 const struct pipe_scissor_state *scissors)
1181 {
1182 struct panfrost_context *ctx = pan_context(pipe);
1183
1184 assert(start_slot == 0);
1185 assert(num_scissors == 1);
1186
1187 ctx->scissor = *scissors;
1188 }
1189
1190 static void
1191 panfrost_set_polygon_stipple(struct pipe_context *pipe,
1192 const struct pipe_poly_stipple *stipple)
1193 {
1194 //struct panfrost_context *panfrost = pan_context(pipe);
1195 }
1196
1197 static void
1198 panfrost_set_active_query_state(struct pipe_context *pipe,
1199 bool enable)
1200 {
1201 struct panfrost_context *ctx = pan_context(pipe);
1202 ctx->active_queries = enable;
1203 }
1204
1205 static void
1206 panfrost_destroy(struct pipe_context *pipe)
1207 {
1208 struct panfrost_context *panfrost = pan_context(pipe);
1209
1210 if (panfrost->blitter)
1211 util_blitter_destroy(panfrost->blitter);
1212
1213 if (panfrost->blitter_wallpaper)
1214 util_blitter_destroy(panfrost->blitter_wallpaper);
1215
1216 util_unreference_framebuffer_state(&panfrost->pipe_framebuffer);
1217 u_upload_destroy(pipe->stream_uploader);
1218 u_upload_destroy(panfrost->state_uploader);
1219
1220 ralloc_free(pipe);
1221 }
1222
1223 static struct pipe_query *
1224 panfrost_create_query(struct pipe_context *pipe,
1225 unsigned type,
1226 unsigned index)
1227 {
1228 struct panfrost_query *q = rzalloc(pipe, struct panfrost_query);
1229
1230 q->type = type;
1231 q->index = index;
1232
1233 return (struct pipe_query *) q;
1234 }
1235
1236 static void
1237 panfrost_destroy_query(struct pipe_context *pipe, struct pipe_query *q)
1238 {
1239 struct panfrost_query *query = (struct panfrost_query *) q;
1240
1241 if (query->bo) {
1242 panfrost_bo_unreference(query->bo);
1243 query->bo = NULL;
1244 }
1245
1246 ralloc_free(q);
1247 }
1248
1249 static bool
1250 panfrost_begin_query(struct pipe_context *pipe, struct pipe_query *q)
1251 {
1252 struct panfrost_context *ctx = pan_context(pipe);
1253 struct panfrost_query *query = (struct panfrost_query *) q;
1254
1255 switch (query->type) {
1256 case PIPE_QUERY_OCCLUSION_COUNTER:
1257 case PIPE_QUERY_OCCLUSION_PREDICATE:
1258 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1259 /* Allocate a bo for the query results to be stored */
1260 if (!query->bo) {
1261 query->bo = panfrost_bo_create(
1262 pan_device(ctx->base.screen),
1263 sizeof(unsigned), 0);
1264 }
1265
1266 unsigned *result = (unsigned *)query->bo->cpu;
1267 *result = 0; /* Default to 0 if nothing at all drawn. */
1268 ctx->occlusion_query = query;
1269 break;
1270
1271 /* Geometry statistics are computed in the driver. XXX: geom/tess
1272 * shaders.. */
1273
1274 case PIPE_QUERY_PRIMITIVES_GENERATED:
1275 query->start = ctx->prims_generated;
1276 break;
1277 case PIPE_QUERY_PRIMITIVES_EMITTED:
1278 query->start = ctx->tf_prims_generated;
1279 break;
1280
1281 default:
1282 /* TODO: timestamp queries, etc? */
1283 break;
1284 }
1285
1286 return true;
1287 }
1288
1289 static bool
1290 panfrost_end_query(struct pipe_context *pipe, struct pipe_query *q)
1291 {
1292 struct panfrost_context *ctx = pan_context(pipe);
1293 struct panfrost_query *query = (struct panfrost_query *) q;
1294
1295 switch (query->type) {
1296 case PIPE_QUERY_OCCLUSION_COUNTER:
1297 case PIPE_QUERY_OCCLUSION_PREDICATE:
1298 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1299 ctx->occlusion_query = NULL;
1300 break;
1301 case PIPE_QUERY_PRIMITIVES_GENERATED:
1302 query->end = ctx->prims_generated;
1303 break;
1304 case PIPE_QUERY_PRIMITIVES_EMITTED:
1305 query->end = ctx->tf_prims_generated;
1306 break;
1307 }
1308
1309 return true;
1310 }
1311
1312 static bool
1313 panfrost_get_query_result(struct pipe_context *pipe,
1314 struct pipe_query *q,
1315 bool wait,
1316 union pipe_query_result *vresult)
1317 {
1318 struct panfrost_query *query = (struct panfrost_query *) q;
1319 struct panfrost_context *ctx = pan_context(pipe);
1320
1321
1322 switch (query->type) {
1323 case PIPE_QUERY_OCCLUSION_COUNTER:
1324 case PIPE_QUERY_OCCLUSION_PREDICATE:
1325 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1326 panfrost_flush_batches_accessing_bo(ctx, query->bo, false);
1327 panfrost_bo_wait(query->bo, INT64_MAX, false);
1328
1329 /* Read back the query results */
1330 unsigned *result = (unsigned *) query->bo->cpu;
1331 unsigned passed = *result;
1332
1333 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
1334 vresult->u64 = passed;
1335 } else {
1336 vresult->b = !!passed;
1337 }
1338
1339 break;
1340
1341 case PIPE_QUERY_PRIMITIVES_GENERATED:
1342 case PIPE_QUERY_PRIMITIVES_EMITTED:
1343 panfrost_flush_all_batches(ctx, 0);
1344 vresult->u64 = query->end - query->start;
1345 break;
1346
1347 default:
1348 /* TODO: more queries */
1349 break;
1350 }
1351
1352 return true;
1353 }
1354
1355 static struct pipe_stream_output_target *
1356 panfrost_create_stream_output_target(struct pipe_context *pctx,
1357 struct pipe_resource *prsc,
1358 unsigned buffer_offset,
1359 unsigned buffer_size)
1360 {
1361 struct pipe_stream_output_target *target;
1362
1363 target = rzalloc(pctx, struct pipe_stream_output_target);
1364
1365 if (!target)
1366 return NULL;
1367
1368 pipe_reference_init(&target->reference, 1);
1369 pipe_resource_reference(&target->buffer, prsc);
1370
1371 target->context = pctx;
1372 target->buffer_offset = buffer_offset;
1373 target->buffer_size = buffer_size;
1374
1375 return target;
1376 }
1377
1378 static void
1379 panfrost_stream_output_target_destroy(struct pipe_context *pctx,
1380 struct pipe_stream_output_target *target)
1381 {
1382 pipe_resource_reference(&target->buffer, NULL);
1383 ralloc_free(target);
1384 }
1385
1386 static void
1387 panfrost_set_stream_output_targets(struct pipe_context *pctx,
1388 unsigned num_targets,
1389 struct pipe_stream_output_target **targets,
1390 const unsigned *offsets)
1391 {
1392 struct panfrost_context *ctx = pan_context(pctx);
1393 struct panfrost_streamout *so = &ctx->streamout;
1394
1395 assert(num_targets <= ARRAY_SIZE(so->targets));
1396
1397 for (unsigned i = 0; i < num_targets; i++) {
1398 if (offsets[i] != -1)
1399 so->offsets[i] = offsets[i];
1400
1401 pipe_so_target_reference(&so->targets[i], targets[i]);
1402 }
1403
1404 for (unsigned i = 0; i < so->num_targets; i++)
1405 pipe_so_target_reference(&so->targets[i], NULL);
1406
1407 so->num_targets = num_targets;
1408 }
1409
1410 struct pipe_context *
1411 panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags)
1412 {
1413 struct panfrost_context *ctx = rzalloc(screen, struct panfrost_context);
1414 struct pipe_context *gallium = (struct pipe_context *) ctx;
1415 struct panfrost_device *dev = pan_device(screen);
1416
1417 gallium->screen = screen;
1418
1419 gallium->destroy = panfrost_destroy;
1420
1421 gallium->set_framebuffer_state = panfrost_set_framebuffer_state;
1422
1423 gallium->flush = panfrost_flush;
1424 gallium->clear = panfrost_clear;
1425 gallium->draw_vbo = panfrost_draw_vbo;
1426 gallium->texture_barrier = panfrost_texture_barrier;
1427
1428 gallium->set_vertex_buffers = panfrost_set_vertex_buffers;
1429 gallium->set_constant_buffer = panfrost_set_constant_buffer;
1430 gallium->set_shader_buffers = panfrost_set_shader_buffers;
1431
1432 gallium->set_stencil_ref = panfrost_set_stencil_ref;
1433
1434 gallium->create_sampler_view = panfrost_create_sampler_view;
1435 gallium->set_sampler_views = panfrost_set_sampler_views;
1436 gallium->sampler_view_destroy = panfrost_sampler_view_destroy;
1437
1438 gallium->create_rasterizer_state = panfrost_create_rasterizer_state;
1439 gallium->bind_rasterizer_state = panfrost_bind_rasterizer_state;
1440 gallium->delete_rasterizer_state = panfrost_generic_cso_delete;
1441
1442 gallium->create_vertex_elements_state = panfrost_create_vertex_elements_state;
1443 gallium->bind_vertex_elements_state = panfrost_bind_vertex_elements_state;
1444 gallium->delete_vertex_elements_state = panfrost_generic_cso_delete;
1445
1446 gallium->create_fs_state = panfrost_create_fs_state;
1447 gallium->delete_fs_state = panfrost_delete_shader_state;
1448 gallium->bind_fs_state = panfrost_bind_fs_state;
1449
1450 gallium->create_vs_state = panfrost_create_vs_state;
1451 gallium->delete_vs_state = panfrost_delete_shader_state;
1452 gallium->bind_vs_state = panfrost_bind_vs_state;
1453
1454 gallium->create_sampler_state = panfrost_create_sampler_state;
1455 gallium->delete_sampler_state = panfrost_generic_cso_delete;
1456 gallium->bind_sampler_states = panfrost_bind_sampler_states;
1457
1458 gallium->create_depth_stencil_alpha_state = panfrost_create_depth_stencil_state;
1459 gallium->bind_depth_stencil_alpha_state = panfrost_bind_depth_stencil_state;
1460 gallium->delete_depth_stencil_alpha_state = panfrost_delete_depth_stencil_state;
1461
1462 gallium->set_sample_mask = panfrost_set_sample_mask;
1463 gallium->set_min_samples = panfrost_set_min_samples;
1464
1465 gallium->set_clip_state = panfrost_set_clip_state;
1466 gallium->set_viewport_states = panfrost_set_viewport_states;
1467 gallium->set_scissor_states = panfrost_set_scissor_states;
1468 gallium->set_polygon_stipple = panfrost_set_polygon_stipple;
1469 gallium->set_active_query_state = panfrost_set_active_query_state;
1470
1471 gallium->create_query = panfrost_create_query;
1472 gallium->destroy_query = panfrost_destroy_query;
1473 gallium->begin_query = panfrost_begin_query;
1474 gallium->end_query = panfrost_end_query;
1475 gallium->get_query_result = panfrost_get_query_result;
1476
1477 gallium->create_stream_output_target = panfrost_create_stream_output_target;
1478 gallium->stream_output_target_destroy = panfrost_stream_output_target_destroy;
1479 gallium->set_stream_output_targets = panfrost_set_stream_output_targets;
1480
1481 panfrost_resource_context_init(gallium);
1482 panfrost_blend_context_init(gallium);
1483 panfrost_compute_context_init(gallium);
1484
1485 gallium->stream_uploader = u_upload_create_default(gallium);
1486 gallium->const_uploader = gallium->stream_uploader;
1487
1488 ctx->state_uploader = u_upload_create(gallium, 4096,
1489 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_DYNAMIC, 0);
1490
1491 /* All of our GPUs support ES mode. Midgard supports additionally
1492 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1493
1494 ctx->draw_modes = (1 << (PIPE_PRIM_QUADS + 1)) - 1;
1495
1496 if (!(dev->quirks & IS_BIFROST)) {
1497 ctx->draw_modes |= (1 << PIPE_PRIM_QUAD_STRIP);
1498 ctx->draw_modes |= (1 << PIPE_PRIM_POLYGON);
1499 }
1500
1501 ctx->primconvert = util_primconvert_create(gallium, ctx->draw_modes);
1502
1503 ctx->blitter = util_blitter_create(gallium);
1504 ctx->blitter_wallpaper = util_blitter_create(gallium);
1505
1506 assert(ctx->blitter);
1507 assert(ctx->blitter_wallpaper);
1508
1509 /* Prepare for render! */
1510
1511 panfrost_batch_init(ctx);
1512
1513 if (!(dev->quirks & IS_BIFROST)) {
1514 for (unsigned c = 0; c < PIPE_MAX_COLOR_BUFS; ++c)
1515 ctx->blit_blend.rt[c].shaders = _mesa_hash_table_u64_create(ctx);
1516 }
1517
1518 /* By default mask everything on */
1519 ctx->sample_mask = ~0;
1520 ctx->active_queries = true;
1521
1522 return gallium;
1523 }