2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_format.h"
34 #include "util/macros.h"
35 #include "util/u_format.h"
36 #include "util/u_inlines.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_memory.h"
39 #include "util/u_vbuf.h"
40 #include "util/half_float.h"
41 #include "util/u_helpers.h"
42 #include "util/u_format.h"
43 #include "util/u_prim.h"
44 #include "util/u_prim_restart.h"
45 #include "indices/u_primconvert.h"
46 #include "tgsi/tgsi_parse.h"
47 #include "tgsi/tgsi_from_mesa.h"
48 #include "util/u_math.h"
50 #include "pan_screen.h"
51 #include "pan_blending.h"
52 #include "pan_blend_shaders.h"
55 /* Framebuffer descriptor */
57 static struct midgard_tiler_descriptor
58 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
60 struct panfrost_context
*ctx
= batch
->ctx
;
61 struct midgard_tiler_descriptor t
= {};
62 unsigned height
= batch
->key
.height
;
63 unsigned width
= batch
->key
.width
;
66 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
68 /* Compute the polygon header size and use that to offset the body */
70 unsigned header_size
= panfrost_tiler_header_size(
71 width
, height
, t
.hierarchy_mask
);
73 t
.polygon_list_size
= panfrost_tiler_full_size(
74 width
, height
, t
.hierarchy_mask
);
78 if (t
.hierarchy_mask
) {
79 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
84 /* Allow the entire tiler heap */
85 t
.heap_start
= ctx
->tiler_heap
->gpu
;
86 t
.heap_end
= ctx
->tiler_heap
->gpu
+ ctx
->tiler_heap
->size
;
88 /* The tiler is disabled, so don't allow the tiler heap */
89 t
.heap_start
= ctx
->tiler_heap
->gpu
;
90 t
.heap_end
= t
.heap_start
;
92 /* Use a dummy polygon list */
93 t
.polygon_list
= ctx
->tiler_dummy
->gpu
;
95 /* Disable the tiler */
96 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
100 t
.polygon_list
+ header_size
;
105 struct mali_single_framebuffer
106 panfrost_emit_sfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
108 struct panfrost_context
*ctx
= batch
->ctx
;
109 unsigned width
= batch
->key
.width
;
110 unsigned height
= batch
->key
.height
;
112 struct mali_single_framebuffer framebuffer
= {
113 .width
= MALI_POSITIVE(width
),
114 .height
= MALI_POSITIVE(height
),
116 .format
= 0x30000000,
117 .clear_flags
= 0x1000,
118 .unknown_address_0
= ctx
->scratchpad
->gpu
,
119 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
),
125 struct bifrost_framebuffer
126 panfrost_emit_mfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
128 struct panfrost_context
*ctx
= batch
->ctx
;
129 unsigned width
= batch
->key
.width
;
130 unsigned height
= batch
->key
.height
;
132 struct bifrost_framebuffer framebuffer
= {
133 .unk0
= 0x1e5, /* 1e4 if no spill */
134 .width1
= MALI_POSITIVE(width
),
135 .height1
= MALI_POSITIVE(height
),
136 .width2
= MALI_POSITIVE(width
),
137 .height2
= MALI_POSITIVE(height
),
141 .rt_count_1
= MALI_POSITIVE(batch
->key
.nr_cbufs
),
146 .scratchpad
= ctx
->scratchpad
->gpu
,
147 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
)
155 struct pipe_context
*pipe
,
157 const union pipe_color_union
*color
,
158 double depth
, unsigned stencil
)
160 struct panfrost_context
*ctx
= pan_context(pipe
);
161 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
163 panfrost_batch_add_fbo_bos(batch
);
164 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
168 panfrost_attach_vt_mfbd(struct panfrost_batch
*batch
)
170 struct bifrost_framebuffer mfbd
= panfrost_emit_mfbd(batch
, ~0);
172 return panfrost_upload_transient(batch
, &mfbd
, sizeof(mfbd
)) | MALI_MFBD
;
176 panfrost_attach_vt_sfbd(struct panfrost_batch
*batch
)
178 struct mali_single_framebuffer sfbd
= panfrost_emit_sfbd(batch
, ~0);
180 return panfrost_upload_transient(batch
, &sfbd
, sizeof(sfbd
)) | MALI_SFBD
;
184 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
186 /* Skip the attach if we can */
188 if (ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
) {
189 assert(ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
193 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
194 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
196 if (!batch
->framebuffer
)
197 batch
->framebuffer
= screen
->require_sfbd
?
198 panfrost_attach_vt_sfbd(batch
) :
199 panfrost_attach_vt_mfbd(batch
);
201 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
202 ctx
->payloads
[i
].postfix
.framebuffer
= batch
->framebuffer
;
205 /* Reset per-frame context, called on context initialisation as well as after
206 * flushing a frame */
209 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
211 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
212 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
215 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
218 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
220 /* TODO: When does this need to be handled? */
221 ctx
->active_queries
= true;
224 /* In practice, every field of these payloads should be configurable
225 * arbitrarily, which means these functions are basically catch-all's for
226 * as-of-yet unwavering unknowns */
229 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
231 /* 0x2 bit clear on 32-bit T6XX */
233 struct midgard_payload_vertex_tiler payload
= {
234 .gl_enables
= 0x4 | 0x2,
237 /* Vertex and compute are closely coupled, so share a payload */
239 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
240 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
244 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
246 struct midgard_payload_vertex_tiler payload
= {
248 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
252 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
256 translate_tex_wrap(enum pipe_tex_wrap w
)
259 case PIPE_TEX_WRAP_REPEAT
:
260 return MALI_WRAP_REPEAT
;
262 /* TODO: lower GL_CLAMP? */
263 case PIPE_TEX_WRAP_CLAMP
:
264 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
265 return MALI_WRAP_CLAMP_TO_EDGE
;
267 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
268 return MALI_WRAP_CLAMP_TO_BORDER
;
270 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
271 return MALI_WRAP_MIRRORED_REPEAT
;
274 unreachable("Invalid wrap");
279 panfrost_translate_compare_func(enum pipe_compare_func in
)
282 case PIPE_FUNC_NEVER
:
283 return MALI_FUNC_NEVER
;
286 return MALI_FUNC_LESS
;
288 case PIPE_FUNC_EQUAL
:
289 return MALI_FUNC_EQUAL
;
291 case PIPE_FUNC_LEQUAL
:
292 return MALI_FUNC_LEQUAL
;
294 case PIPE_FUNC_GREATER
:
295 return MALI_FUNC_GREATER
;
297 case PIPE_FUNC_NOTEQUAL
:
298 return MALI_FUNC_NOTEQUAL
;
300 case PIPE_FUNC_GEQUAL
:
301 return MALI_FUNC_GEQUAL
;
303 case PIPE_FUNC_ALWAYS
:
304 return MALI_FUNC_ALWAYS
;
307 unreachable("Invalid func");
312 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
315 case PIPE_FUNC_NEVER
:
316 return MALI_ALT_FUNC_NEVER
;
319 return MALI_ALT_FUNC_LESS
;
321 case PIPE_FUNC_EQUAL
:
322 return MALI_ALT_FUNC_EQUAL
;
324 case PIPE_FUNC_LEQUAL
:
325 return MALI_ALT_FUNC_LEQUAL
;
327 case PIPE_FUNC_GREATER
:
328 return MALI_ALT_FUNC_GREATER
;
330 case PIPE_FUNC_NOTEQUAL
:
331 return MALI_ALT_FUNC_NOTEQUAL
;
333 case PIPE_FUNC_GEQUAL
:
334 return MALI_ALT_FUNC_GEQUAL
;
336 case PIPE_FUNC_ALWAYS
:
337 return MALI_ALT_FUNC_ALWAYS
;
340 unreachable("Invalid alt func");
345 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
348 case PIPE_STENCIL_OP_KEEP
:
349 return MALI_STENCIL_KEEP
;
351 case PIPE_STENCIL_OP_ZERO
:
352 return MALI_STENCIL_ZERO
;
354 case PIPE_STENCIL_OP_REPLACE
:
355 return MALI_STENCIL_REPLACE
;
357 case PIPE_STENCIL_OP_INCR
:
358 return MALI_STENCIL_INCR
;
360 case PIPE_STENCIL_OP_DECR
:
361 return MALI_STENCIL_DECR
;
363 case PIPE_STENCIL_OP_INCR_WRAP
:
364 return MALI_STENCIL_INCR_WRAP
;
366 case PIPE_STENCIL_OP_DECR_WRAP
:
367 return MALI_STENCIL_DECR_WRAP
;
369 case PIPE_STENCIL_OP_INVERT
:
370 return MALI_STENCIL_INVERT
;
373 unreachable("Invalid stencil op");
378 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
380 out
->ref
= 0; /* Gallium gets it from elsewhere */
382 out
->mask
= in
->valuemask
;
383 out
->func
= panfrost_translate_compare_func(in
->func
);
384 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
385 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
386 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
390 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
392 struct mali_shader_meta shader
= {
393 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
395 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
396 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
399 /* unknown2_4 has 0x10 bit set on T6XX. We don't know why this is
400 * required (independent of 32-bit/64-bit descriptors), or why it's not
401 * used on later GPU revisions. Otherwise, all shader jobs fault on
402 * these earlier chips (perhaps this is a chicken bit of some kind).
403 * More investigation is needed. */
406 shader
.unknown2_4
|= 0x10;
409 struct pipe_stencil_state default_stencil
= {
411 .func
= PIPE_FUNC_ALWAYS
,
412 .fail_op
= MALI_STENCIL_KEEP
,
413 .zfail_op
= MALI_STENCIL_KEEP
,
414 .zpass_op
= MALI_STENCIL_KEEP
,
419 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
420 shader
.stencil_mask_front
= default_stencil
.writemask
;
422 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
423 shader
.stencil_mask_back
= default_stencil
.writemask
;
425 if (default_stencil
.enabled
)
426 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
428 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
431 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
432 * graphics command stream. It should be called once per draw, accordding to
433 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
434 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
437 struct panfrost_transfer
438 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
440 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
441 struct mali_job_descriptor_header job
= {
442 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
443 .job_descriptor_size
= 1,
446 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
448 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sizeof(job
) + sizeof(*payload
));
449 memcpy(transfer
.cpu
, &job
, sizeof(job
));
450 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
455 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
457 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
458 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
460 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
464 panfrost_writes_point_size(struct panfrost_context
*ctx
)
466 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
467 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
469 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
472 /* Stage the attribute descriptors so we can adjust src_offset
473 * to let BOs align nicely */
476 panfrost_stage_attributes(struct panfrost_context
*ctx
)
478 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
479 struct panfrost_vertex_state
*so
= ctx
->vertex
;
481 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
482 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
483 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
485 /* Copy as-is for the first pass */
486 memcpy(target
, so
->hw
, sz
);
488 /* Fixup offsets for the second pass. Recall that the hardware
489 * calculates attribute addresses as:
491 * addr = base + (stride * vtx) + src_offset;
493 * However, on Mali, base must be aligned to 64-bytes, so we
496 * base' = base & ~63 = base - (base & 63)
498 * To compensate when using base' (see emit_vertex_data), we have
499 * to adjust src_offset by the masked off piece:
501 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
502 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
503 * = base + (stride * vtx) + src_offset
509 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
511 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
512 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
513 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
514 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
516 /* Adjust by the masked off bits of the offset */
517 target
[i
].src_offset
+= (addr
& 63);
519 /* Also, somewhat obscurely per-instance data needs to be
520 * offset in response to a delayed start in an indexed draw */
522 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
523 target
[i
].src_offset
-= buf
->stride
* start
;
529 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
533 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
535 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
536 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
538 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
541 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
542 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
544 struct panfrost_transfer transfer
=
545 panfrost_allocate_transient(batch
, transfer_size
);
547 struct mali_sampler_descriptor
*desc
=
548 (struct mali_sampler_descriptor
*) transfer
.cpu
;
550 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
551 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
553 upload
= transfer
.gpu
;
556 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
560 static enum mali_texture_layout
561 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
563 /* TODO: other linear depth textures */
564 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
566 switch (rsrc
->layout
) {
568 return MALI_TEXTURE_AFBC
;
571 return MALI_TEXTURE_TILED
;
573 return is_depth
? MALI_TEXTURE_TILED
: MALI_TEXTURE_LINEAR
;
575 unreachable("Invalid texture layout");
581 struct panfrost_context
*ctx
,
582 struct panfrost_sampler_view
*view
)
587 struct pipe_sampler_view
*pview
= &view
->base
;
588 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
590 /* Do we interleave an explicit stride with every element? */
592 bool has_manual_stride
= view
->manual_stride
;
594 /* For easy access */
596 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
597 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
598 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
599 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
600 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
602 /* Lower-bit is set when sampling from colour AFBC */
603 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
604 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
605 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
607 /* Add the BO to the job so it's retained until the job is done. */
608 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
609 panfrost_batch_add_bo(batch
, rsrc
->bo
);
611 /* Add the usage flags in, since they can change across the CSO
612 * lifetime due to layout switches */
614 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
615 view
->hw
.format
.manual_stride
= has_manual_stride
;
617 /* Inject the addresses in, interleaving mip levels, cube faces, and
618 * strides in that order */
622 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
623 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
625 view
->hw
.payload
[idx
++] =
626 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
628 if (has_manual_stride
) {
629 view
->hw
.payload
[idx
++] =
630 rsrc
->slices
[l
].stride
;
635 return panfrost_upload_transient(batch
, &view
->hw
,
636 sizeof(struct mali_texture_descriptor
));
640 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
642 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
644 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
645 mali_ptr trampoline
= 0;
647 if (ctx
->sampler_view_count
[t
]) {
648 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
650 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
652 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
654 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
657 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
661 struct sysval_uniform
{
670 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
671 struct sysval_uniform
*uniform
)
673 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
675 uniform
->f
[0] = vp
->scale
[0];
676 uniform
->f
[1] = vp
->scale
[1];
677 uniform
->f
[2] = vp
->scale
[2];
680 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
681 struct sysval_uniform
*uniform
)
683 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
685 uniform
->f
[0] = vp
->translate
[0];
686 uniform
->f
[1] = vp
->translate
[1];
687 uniform
->f
[2] = vp
->translate
[2];
690 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
691 enum pipe_shader_type st
,
692 unsigned int sysvalid
,
693 struct sysval_uniform
*uniform
)
695 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
696 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
697 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
698 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
701 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
704 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
705 tex
->u
.tex
.first_level
);
708 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
709 tex
->u
.tex
.first_level
);
712 uniform
->i
[dim
] = tex
->texture
->array_size
;
715 static void panfrost_upload_ssbo_sysval(
716 struct panfrost_context
*ctx
,
717 enum pipe_shader_type st
,
719 struct sysval_uniform
*uniform
)
721 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
722 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
724 /* Compute address */
725 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
726 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
728 panfrost_batch_add_bo(batch
, bo
);
730 /* Upload address and size as sysval */
731 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
732 uniform
->u
[2] = sb
.buffer_size
;
735 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
736 struct sysval_uniform
*uniform
)
738 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
739 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
740 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
743 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
744 struct panfrost_shader_state
*ss
,
745 enum pipe_shader_type st
)
747 struct sysval_uniform
*uniforms
= (void *)buf
;
749 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
750 int sysval
= ss
->sysval
[i
];
752 switch (PAN_SYSVAL_TYPE(sysval
)) {
753 case PAN_SYSVAL_VIEWPORT_SCALE
:
754 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
756 case PAN_SYSVAL_VIEWPORT_OFFSET
:
757 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
759 case PAN_SYSVAL_TEXTURE_SIZE
:
760 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
763 case PAN_SYSVAL_SSBO
:
764 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
767 case PAN_SYSVAL_NUM_WORK_GROUPS
:
768 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
778 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
780 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
781 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
784 return rsrc
->bo
->cpu
;
785 else if (cb
->user_buffer
)
786 return cb
->user_buffer
;
788 unreachable("No constant buffer");
792 panfrost_map_constant_buffer_gpu(
793 struct panfrost_context
*ctx
,
794 struct panfrost_constant_buffer
*buf
,
797 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
798 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
799 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
802 panfrost_batch_add_bo(batch
, rsrc
->bo
);
803 return rsrc
->bo
->gpu
;
804 } else if (cb
->user_buffer
) {
805 return panfrost_upload_transient(batch
, cb
->user_buffer
, cb
->buffer_size
);
807 unreachable("No constant buffer");
811 /* Compute number of UBOs active (more specifically, compute the highest UBO
812 * number addressable -- if there are gaps, include them in the count anyway).
813 * We always include UBO #0 in the count, since we *need* uniforms enabled for
817 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
819 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
820 return 32 - __builtin_clz(mask
);
823 /* Fixes up a shader state with current state, returning a GPU address to the
827 panfrost_patch_shader_state(
828 struct panfrost_context
*ctx
,
829 struct panfrost_shader_state
*ss
,
830 enum pipe_shader_type stage
,
833 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
834 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
836 ss
->tripipe
->midgard1
.flags
= 0x220;
838 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
839 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
841 /* We can't reuse over frames; that's not safe. The descriptor must be
842 * transient uploaded */
845 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
847 return panfrost_upload_transient(batch
, ss
->tripipe
,
848 sizeof(struct mali_shader_meta
));
851 /* If we don't need an upload, don't bother */
857 panfrost_patch_shader_state_compute(
858 struct panfrost_context
*ctx
,
859 enum pipe_shader_type stage
,
862 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
865 ctx
->payloads
[stage
].postfix
._shader_upper
= 0;
869 struct panfrost_shader_state
*s
= &all
->variants
[all
->active_variant
];
871 ctx
->payloads
[stage
].postfix
._shader_upper
=
872 panfrost_patch_shader_state(ctx
, s
, stage
, should_upload
) >> 4;
875 /* Go through dirty flags and actualise them in the cmdstream. */
878 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
880 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
881 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
883 panfrost_batch_add_fbo_bos(batch
);
884 panfrost_attach_vt_framebuffer(ctx
);
886 if (with_vertex_data
) {
887 panfrost_emit_vertex_data(batch
);
889 /* Varyings emitted for -all- geometry */
890 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
891 panfrost_emit_varying_descriptor(ctx
, total_count
);
894 bool msaa
= ctx
->rasterizer
->base
.multisample
;
896 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
897 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
899 /* TODO: Sample size */
900 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
901 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
904 panfrost_batch_set_requirements(batch
);
906 if (ctx
->occlusion_query
) {
907 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
908 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
911 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_VERTEX
, true);
912 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_COMPUTE
, true);
914 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
915 /* Check if we need to link the gl_PointSize varying */
916 if (!panfrost_writes_point_size(ctx
)) {
917 /* If the size is constant, write it out. Otherwise,
918 * don't touch primitive_size (since we would clobber
919 * the pointer there) */
921 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
925 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
926 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
927 ctx
->dirty
|= PAN_DIRTY_FS
;
929 if (ctx
->dirty
& PAN_DIRTY_FS
) {
930 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
931 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
933 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
935 panfrost_batch_add_bo(batch
, variant
->bo
);
937 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
940 COPY(attribute_count
);
944 COPY(midgard1
.uniform_count
);
945 COPY(midgard1
.uniform_buffer_count
);
946 COPY(midgard1
.work_count
);
947 COPY(midgard1
.flags
);
948 COPY(midgard1
.unknown2
);
952 /* Get blending setup */
953 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
955 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
957 for (unsigned c
= 0; c
< rt_count
; ++c
)
958 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
960 /* If there is a blend shader, work registers are shared. XXX: opt */
962 for (unsigned c
= 0; c
< rt_count
; ++c
) {
963 if (blend
[c
].is_shader
)
964 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
967 /* Set late due to depending on render state */
968 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
970 /* Depending on whether it's legal to in the given shader, we
971 * try to enable early-z testing (or forward-pixel kill?) */
973 if (!variant
->can_discard
)
974 flags
|= MALI_EARLY_Z
;
976 /* Any time texturing is used, derivatives are implicitly
977 * calculated, so we need to enable helper invocations */
979 if (variant
->helper_invocations
)
980 flags
|= MALI_HELPER_INVOCATIONS
;
982 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
984 /* Assign the stencil refs late */
986 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
987 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
988 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
990 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
991 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
993 /* CAN_DISCARD should be set if the fragment shader possibly
994 * contains a 'discard' instruction. It is likely this is
995 * related to optimizations related to forward-pixel kill, as
996 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
997 * thing?" by Peter Harris
1000 if (variant
->can_discard
) {
1001 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1002 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1005 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1006 * *also* copied to the blend_meta appended (by convention),
1007 * but this is the field actually read by the hardware. (Or
1008 * maybe both are read...?) */
1010 if (blend
[0].is_shader
) {
1011 ctx
->fragment_shader_core
.blend
.shader
=
1012 blend
[0].shader
.bo
->gpu
| blend
[0].shader
.first_tag
;
1014 ctx
->fragment_shader_core
.blend
.shader
= 0;
1017 if (screen
->require_sfbd
) {
1018 /* When only a single render target platform is used, the blend
1019 * information is inside the shader meta itself. We
1020 * additionally need to signal CAN_DISCARD for nontrivial blend
1021 * modes (so we're able to read back the destination buffer) */
1023 if (!blend
[0].is_shader
) {
1024 ctx
->fragment_shader_core
.blend
.equation
=
1025 *blend
[0].equation
.equation
;
1026 ctx
->fragment_shader_core
.blend
.constant
=
1027 blend
[0].equation
.constant
;
1030 if (!blend
[0].no_blending
) {
1031 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1035 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1036 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1037 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1039 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1041 if (!screen
->require_sfbd
) {
1042 /* Additional blend descriptor tacked on for jobs using MFBD */
1044 struct midgard_blend_rt rts
[4];
1046 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1047 unsigned blend_count
= 0x200;
1049 if (blend
[i
].is_shader
) {
1050 /* For a blend shader, the bottom nibble corresponds to
1051 * the number of work registers used, which signals the
1052 * -existence- of a blend shader */
1054 assert(blend
[i
].shader
.work_count
>= 2);
1055 blend_count
|= MIN2(blend
[i
].shader
.work_count
, 3);
1057 /* Otherwise, the bottom bit simply specifies if
1058 * blending (anything other than REPLACE) is enabled */
1060 if (!blend
[i
].no_blending
)
1066 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1067 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1068 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1070 rts
[i
].flags
= blend_count
;
1073 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1075 if (!ctx
->blend
->base
.dither
)
1076 rts
[i
].flags
|= MALI_BLEND_NO_DITHER
;
1078 /* TODO: sRGB in blend shaders is currently
1079 * unimplemented. Contact me (Alyssa) if you're
1080 * interested in working on this. We have
1081 * native Midgard ops for helping here, but
1082 * they're not well-understood yet. */
1084 assert(!(is_srgb
&& blend
[i
].is_shader
));
1086 if (blend
[i
].is_shader
) {
1087 rts
[i
].blend
.shader
= blend
[i
].shader
.bo
->gpu
| blend
[i
].shader
.first_tag
;
1089 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1090 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1094 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1098 /* We stage to transient, so always dirty.. */
1100 panfrost_stage_attributes(ctx
);
1102 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1103 panfrost_upload_sampler_descriptors(ctx
);
1105 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1106 panfrost_upload_texture_descriptors(ctx
);
1108 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1110 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1111 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1116 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1118 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1120 panfrost_batch_add_bo(batch
, ss
->bo
);
1122 /* Uniforms are implicitly UBO #0 */
1123 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1125 /* Allocate room for the sysval and the uniforms */
1126 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1127 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1128 size_t size
= sys_size
+ uniform_size
;
1129 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1131 /* Upload sysvals requested by the shader */
1132 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1134 /* Upload uniforms */
1136 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1137 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1141 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1143 struct mali_vertex_tiler_postfix
*postfix
=
1144 &ctx
->payloads
[i
].postfix
;
1146 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1149 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1150 assert(ubo_count
>= 1);
1152 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1153 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1155 /* Upload uniforms as a UBO */
1156 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1157 ubos
[0].ptr
= transfer
.gpu
>> 2;
1159 /* The rest are honest-to-goodness UBOs */
1161 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1162 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1164 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1165 bool empty
= usz
== 0;
1167 if (!enabled
|| empty
) {
1168 /* Stub out disabled UBOs to catch accesses */
1171 ubos
[ubo
].ptr
= 0xDEAD0000;
1175 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, buf
, ubo
);
1177 unsigned bytes_per_field
= 16;
1178 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1179 unsigned fields
= aligned
/ bytes_per_field
;
1181 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1182 ubos
[ubo
].ptr
= gpu
>> 2;
1185 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1186 postfix
->uniforms
= transfer
.gpu
;
1187 postfix
->uniform_buffers
= ubufs
;
1189 buf
->dirty_mask
= 0;
1192 /* TODO: Upload the viewport somewhere more appropriate */
1194 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1195 * (somewhat) asymmetric ints. */
1196 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1198 struct mali_viewport view
= {
1199 /* By default, do no viewport clipping, i.e. clip to (-inf,
1200 * inf) in each direction. Clipping to the viewport in theory
1201 * should work, but in practice causes issues when we're not
1202 * explicitly trying to scissor */
1204 .clip_minx
= -INFINITY
,
1205 .clip_miny
= -INFINITY
,
1206 .clip_maxx
= INFINITY
,
1207 .clip_maxy
= INFINITY
,
1210 /* Always scissor to the viewport by default. */
1211 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1212 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1214 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1215 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1217 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1218 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1220 /* Apply the scissor test */
1222 unsigned minx
, miny
, maxx
, maxy
;
1224 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1225 minx
= MAX2(ss
->minx
, vp_minx
);
1226 miny
= MAX2(ss
->miny
, vp_miny
);
1227 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1228 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1236 /* Hardware needs the min/max to be strictly ordered, so flip if we
1237 * need to. The viewport transformation in the vertex shader will
1238 * handle the negatives if we don't */
1241 unsigned temp
= miny
;
1247 unsigned temp
= minx
;
1258 /* Clamp to the framebuffer size as a last check */
1260 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1261 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1263 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1264 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1266 /* Update the job, unless we're doing wallpapering (whose lack of
1267 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1268 * just... be faster :) */
1270 if (!ctx
->wallpaper_batch
)
1271 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1275 view
.viewport0
[0] = minx
;
1276 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1278 view
.viewport0
[1] = miny
;
1279 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1281 view
.clip_minz
= minz
;
1282 view
.clip_maxz
= maxz
;
1284 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1285 panfrost_upload_transient(batch
,
1287 sizeof(struct mali_viewport
));
1292 /* Corresponds to exactly one draw, but does not submit anything */
1295 panfrost_queue_draw(struct panfrost_context
*ctx
)
1297 /* Handle dirty flags now */
1298 panfrost_emit_for_draw(ctx
, true);
1300 /* If rasterizer discard is enable, only submit the vertex */
1302 bool rasterizer_discard
= ctx
->rasterizer
1303 && ctx
->rasterizer
->base
.rasterizer_discard
;
1305 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1306 struct panfrost_transfer tiler
;
1308 if (!rasterizer_discard
)
1309 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1311 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1313 if (rasterizer_discard
)
1314 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1315 else if (ctx
->wallpaper_batch
)
1316 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1318 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1321 /* The entire frame is in memory -- send it off to the kernel! */
1325 struct pipe_context
*pipe
,
1326 struct pipe_fence_handle
**fence
,
1329 struct panfrost_context
*ctx
= pan_context(pipe
);
1330 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1332 /* Submit the frame itself */
1333 panfrost_batch_submit(batch
);
1336 struct panfrost_fence
*f
= panfrost_fence_create(ctx
);
1337 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1338 *fence
= (struct pipe_fence_handle
*)f
;
1342 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1345 g2m_draw_mode(enum pipe_prim_type mode
)
1348 DEFINE_CASE(POINTS
);
1350 DEFINE_CASE(LINE_LOOP
);
1351 DEFINE_CASE(LINE_STRIP
);
1352 DEFINE_CASE(TRIANGLES
);
1353 DEFINE_CASE(TRIANGLE_STRIP
);
1354 DEFINE_CASE(TRIANGLE_FAN
);
1356 DEFINE_CASE(QUAD_STRIP
);
1357 DEFINE_CASE(POLYGON
);
1360 unreachable("Invalid draw mode");
1367 panfrost_translate_index_size(unsigned size
)
1371 return MALI_DRAW_INDEXED_UINT8
;
1374 return MALI_DRAW_INDEXED_UINT16
;
1377 return MALI_DRAW_INDEXED_UINT32
;
1380 unreachable("Invalid index size");
1384 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1385 * good for the duration of the draw (transient), could last longer */
1388 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1390 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1392 off_t offset
= info
->start
* info
->index_size
;
1393 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1395 if (!info
->has_user_indices
) {
1396 /* Only resources can be directly mapped */
1397 panfrost_batch_add_bo(batch
, rsrc
->bo
);
1398 return rsrc
->bo
->gpu
+ offset
;
1400 /* Otherwise, we need to upload to transient memory */
1401 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1402 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1407 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1409 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1411 /* Check if we're scissoring at all */
1413 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1416 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1419 /* Count generated primitives (when there is no geom/tess shaders) for
1420 * transform feedback */
1423 panfrost_statistics_record(
1424 struct panfrost_context
*ctx
,
1425 const struct pipe_draw_info
*info
)
1427 if (!ctx
->active_queries
)
1430 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1431 ctx
->prims_generated
+= prims
;
1433 if (!ctx
->streamout
.num_targets
)
1436 ctx
->tf_prims_generated
+= prims
;
1441 struct pipe_context
*pipe
,
1442 const struct pipe_draw_info
*info
)
1444 struct panfrost_context
*ctx
= pan_context(pipe
);
1446 /* First of all, check the scissor to see if anything is drawn at all.
1447 * If it's not, we drop the draw (mostly a conformance issue;
1448 * well-behaved apps shouldn't hit this) */
1450 if (panfrost_scissor_culls_everything(ctx
))
1453 int mode
= info
->mode
;
1455 /* Fallback unsupported restart index */
1456 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1458 if (info
->primitive_restart
&& info
->index_size
1459 && info
->restart_index
!= primitive_index
) {
1460 util_draw_vbo_without_prim_restart(pipe
, info
);
1464 /* Fallback for unsupported modes */
1466 assert(ctx
->rasterizer
!= NULL
);
1468 if (!(ctx
->draw_modes
& (1 << mode
))) {
1469 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1470 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1472 if (info
->count
< 4) {
1473 /* Degenerate case? */
1477 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1478 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1483 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1484 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1486 /* Now that we have a guaranteed terminating path, find the job.
1487 * Assignment commented out to prevent unused warning */
1489 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1491 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1493 /* Take into account a negative bias */
1494 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1495 ctx
->instance_count
= info
->instance_count
;
1496 ctx
->active_prim
= info
->mode
;
1498 /* For non-indexed draws, they're the same */
1499 unsigned vertex_count
= ctx
->vertex_count
;
1501 unsigned draw_flags
= 0;
1503 /* The draw flags interpret how primitive size is interpreted */
1505 if (panfrost_writes_point_size(ctx
))
1506 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1508 if (info
->primitive_restart
)
1509 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1511 /* For higher amounts of vertices (greater than what fits in a 16-bit
1512 * short), the other value is needed, otherwise there will be bizarre
1513 * rendering artefacts. It's not clear what these values mean yet. This
1514 * change is also needed for instancing and sometimes points (perhaps
1515 * related to dynamically setting gl_PointSize) */
1517 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1518 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1519 bool instanced
= ctx
->instance_count
> 1;
1521 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1523 /* This doesn't make much sense */
1524 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1525 draw_flags
|= 0x800;
1528 panfrost_statistics_record(ctx
, info
);
1530 if (info
->index_size
) {
1531 /* Calculate the min/max index used so we can figure out how
1532 * many times to invoke the vertex shader */
1534 /* Fetch / calculate index bounds */
1535 unsigned min_index
= 0, max_index
= 0;
1537 if (info
->max_index
== ~0u) {
1538 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1540 min_index
= info
->min_index
;
1541 max_index
= info
->max_index
;
1544 /* Use the corresponding values */
1545 vertex_count
= max_index
- min_index
+ 1;
1546 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1547 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1549 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1550 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1552 //assert(!info->restart_index); /* TODO: Research */
1554 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1555 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1557 /* Index count == vertex count, if no indexing is applied, as
1558 * if it is internally indexed in the expected order */
1560 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1561 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1563 /* Reverse index state */
1564 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1567 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1568 * vertex_count, 1) */
1570 panfrost_pack_work_groups_fused(
1571 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1572 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1573 1, vertex_count
, info
->instance_count
,
1576 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1578 /* Encode the padded vertex count */
1580 if (info
->instance_count
> 1) {
1581 /* Triangles have non-even vertex counts so they change how
1582 * padding works internally */
1585 mode
== PIPE_PRIM_TRIANGLES
||
1586 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1587 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1589 struct pan_shift_odd so
=
1590 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1592 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= so
.shift
;
1593 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= so
.shift
;
1595 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= so
.odd
;
1596 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= so
.odd
;
1598 ctx
->padded_count
= pan_expand_shift_odd(so
);
1600 ctx
->padded_count
= ctx
->vertex_count
;
1602 /* Reset instancing state */
1603 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1604 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1605 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1606 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1609 /* Fire off the draw itself */
1610 panfrost_queue_draw(ctx
);
1612 /* Increment transform feedback offsets */
1614 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1615 unsigned output_count
= u_stream_outputs_for_vertices(
1616 ctx
->active_prim
, ctx
->vertex_count
);
1618 ctx
->streamout
.offsets
[i
] += output_count
;
1625 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1631 panfrost_create_rasterizer_state(
1632 struct pipe_context
*pctx
,
1633 const struct pipe_rasterizer_state
*cso
)
1635 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1639 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1640 so
->tiler_gl_enables
= 0x7;
1643 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1645 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1646 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1648 if (cso
->cull_face
& PIPE_FACE_BACK
)
1649 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1655 panfrost_bind_rasterizer_state(
1656 struct pipe_context
*pctx
,
1659 struct panfrost_context
*ctx
= pan_context(pctx
);
1661 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1665 ctx
->rasterizer
= hwcso
;
1666 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1668 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1669 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1671 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1672 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1674 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1676 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1677 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1679 /* Point sprites are emulated */
1681 struct panfrost_shader_state
*variant
=
1682 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1684 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1685 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1689 panfrost_create_vertex_elements_state(
1690 struct pipe_context
*pctx
,
1691 unsigned num_elements
,
1692 const struct pipe_vertex_element
*elements
)
1694 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1696 so
->num_elements
= num_elements
;
1697 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1699 for (int i
= 0; i
< num_elements
; ++i
) {
1700 so
->hw
[i
].index
= i
;
1702 enum pipe_format fmt
= elements
[i
].src_format
;
1703 const struct util_format_description
*desc
= util_format_description(fmt
);
1704 so
->hw
[i
].unknown1
= 0x2;
1705 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1707 so
->hw
[i
].format
= panfrost_find_format(desc
);
1709 /* The field itself should probably be shifted over */
1710 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1717 panfrost_bind_vertex_elements_state(
1718 struct pipe_context
*pctx
,
1721 struct panfrost_context
*ctx
= pan_context(pctx
);
1723 ctx
->vertex
= hwcso
;
1724 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1728 panfrost_create_shader_state(
1729 struct pipe_context
*pctx
,
1730 const struct pipe_shader_state
*cso
)
1732 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1735 /* Token deep copy to prevent memory corruption */
1737 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1738 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1744 panfrost_delete_shader_state(
1745 struct pipe_context
*pctx
,
1748 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1750 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1751 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1754 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1755 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1756 panfrost_bo_unreference(shader_state
->bo
);
1757 shader_state
->bo
= NULL
;
1764 panfrost_create_sampler_state(
1765 struct pipe_context
*pctx
,
1766 const struct pipe_sampler_state
*cso
)
1768 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1771 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1773 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1774 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1775 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1777 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1778 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1779 unsigned mip_filter
= mip_linear
?
1780 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1781 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1783 struct mali_sampler_descriptor sampler_descriptor
= {
1784 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1785 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1786 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1787 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1788 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1790 cso
->border_color
.f
[0],
1791 cso
->border_color
.f
[1],
1792 cso
->border_color
.f
[2],
1793 cso
->border_color
.f
[3]
1795 .min_lod
= FIXED_16(cso
->min_lod
),
1796 .max_lod
= FIXED_16(cso
->max_lod
),
1797 .seamless_cube_map
= cso
->seamless_cube_map
,
1800 /* If necessary, we disable mipmapping in the sampler descriptor by
1801 * clamping the LOD as tight as possible (from 0 to epsilon,
1802 * essentially -- remember these are fixed point numbers, so
1805 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1806 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1808 /* Enforce that there is something in the middle by adding epsilon*/
1810 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1811 sampler_descriptor
.max_lod
++;
1814 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1816 so
->hw
= sampler_descriptor
;
1822 panfrost_bind_sampler_states(
1823 struct pipe_context
*pctx
,
1824 enum pipe_shader_type shader
,
1825 unsigned start_slot
, unsigned num_sampler
,
1828 assert(start_slot
== 0);
1830 struct panfrost_context
*ctx
= pan_context(pctx
);
1832 /* XXX: Should upload, not just copy? */
1833 ctx
->sampler_count
[shader
] = num_sampler
;
1834 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1836 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1840 panfrost_variant_matches(
1841 struct panfrost_context
*ctx
,
1842 struct panfrost_shader_state
*variant
,
1843 enum pipe_shader_type type
)
1845 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1846 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1848 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1850 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1851 /* Make sure enable state is at least the same */
1852 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1856 /* Check that the contents of the test are the same */
1857 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1858 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1860 if (!(same_func
&& same_ref
)) {
1865 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1866 variant
->point_sprite_mask
)) {
1867 /* Ensure the same varyings are turned to point sprites */
1868 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1871 /* Ensure the orientation is correct */
1873 rasterizer
->sprite_coord_mode
==
1874 PIPE_SPRITE_COORD_UPPER_LEFT
;
1876 if (variant
->point_sprite_upper_left
!= upper_left
)
1880 /* Otherwise, we're good to go */
1885 * Fix an uncompiled shader's stream output info, and produce a bitmask
1886 * of which VARYING_SLOT_* are captured for stream output.
1888 * Core Gallium stores output->register_index as a "slot" number, where
1889 * slots are assigned consecutively to all outputs in info->outputs_written.
1890 * This naive packing of outputs doesn't work for us - we too have slots,
1891 * but the layout is defined by the VUE map, which we won't have until we
1892 * compile a specific shader variant. So, we remap these and simply store
1893 * VARYING_SLOT_* in our copy's output->register_index fields.
1895 * We then produce a bitmask of outputs which are used for SO.
1897 * Implementation from iris.
1901 update_so_info(struct pipe_stream_output_info
*so_info
,
1902 uint64_t outputs_written
)
1904 uint64_t so_outputs
= 0;
1905 uint8_t reverse_map
[64] = {};
1908 while (outputs_written
)
1909 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1911 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1912 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1914 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1915 output
->register_index
= reverse_map
[output
->register_index
];
1917 so_outputs
|= 1ull << output
->register_index
;
1924 panfrost_bind_shader_state(
1925 struct pipe_context
*pctx
,
1927 enum pipe_shader_type type
)
1929 struct panfrost_context
*ctx
= pan_context(pctx
);
1931 ctx
->shader
[type
] = hwcso
;
1933 if (type
== PIPE_SHADER_FRAGMENT
)
1934 ctx
->dirty
|= PAN_DIRTY_FS
;
1936 ctx
->dirty
|= PAN_DIRTY_VS
;
1940 /* Match the appropriate variant */
1942 signed variant
= -1;
1943 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1945 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1946 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1952 if (variant
== -1) {
1953 /* No variant matched, so create a new one */
1954 variant
= variants
->variant_count
++;
1955 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1957 struct panfrost_shader_state
*v
=
1958 &variants
->variants
[variant
];
1960 if (type
== PIPE_SHADER_FRAGMENT
) {
1961 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1963 if (ctx
->rasterizer
) {
1964 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1965 v
->point_sprite_upper_left
=
1966 ctx
->rasterizer
->base
.sprite_coord_mode
==
1967 PIPE_SPRITE_COORD_UPPER_LEFT
;
1971 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1975 /* Select this variant */
1976 variants
->active_variant
= variant
;
1978 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1979 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1981 /* We finally have a variant, so compile it */
1983 if (!shader_state
->compiled
) {
1984 uint64_t outputs_written
= 0;
1986 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
1987 variants
->base
.type
,
1988 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
1989 variants
->base
.ir
.nir
:
1990 variants
->base
.tokens
,
1991 tgsi_processor_to_shader_stage(type
), shader_state
,
1994 shader_state
->compiled
= true;
1996 /* Fixup the stream out information, since what Gallium returns
1997 * normally is mildly insane */
1999 shader_state
->stream_output
= variants
->base
.stream_output
;
2000 shader_state
->so_mask
=
2001 update_so_info(&shader_state
->stream_output
, outputs_written
);
2006 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2008 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2012 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2014 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2018 panfrost_set_vertex_buffers(
2019 struct pipe_context
*pctx
,
2020 unsigned start_slot
,
2021 unsigned num_buffers
,
2022 const struct pipe_vertex_buffer
*buffers
)
2024 struct panfrost_context
*ctx
= pan_context(pctx
);
2026 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2030 panfrost_set_constant_buffer(
2031 struct pipe_context
*pctx
,
2032 enum pipe_shader_type shader
, uint index
,
2033 const struct pipe_constant_buffer
*buf
)
2035 struct panfrost_context
*ctx
= pan_context(pctx
);
2036 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2038 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2040 unsigned mask
= (1 << index
);
2042 if (unlikely(!buf
)) {
2043 pbuf
->enabled_mask
&= ~mask
;
2044 pbuf
->dirty_mask
&= ~mask
;
2048 pbuf
->enabled_mask
|= mask
;
2049 pbuf
->dirty_mask
|= mask
;
2053 panfrost_set_stencil_ref(
2054 struct pipe_context
*pctx
,
2055 const struct pipe_stencil_ref
*ref
)
2057 struct panfrost_context
*ctx
= pan_context(pctx
);
2058 ctx
->stencil_ref
= *ref
;
2060 /* Shader core dirty */
2061 ctx
->dirty
|= PAN_DIRTY_FS
;
2064 static enum mali_texture_type
2065 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2069 case PIPE_TEXTURE_1D
:
2070 case PIPE_TEXTURE_1D_ARRAY
:
2073 case PIPE_TEXTURE_2D
:
2074 case PIPE_TEXTURE_2D_ARRAY
:
2075 case PIPE_TEXTURE_RECT
:
2078 case PIPE_TEXTURE_3D
:
2081 case PIPE_TEXTURE_CUBE
:
2082 case PIPE_TEXTURE_CUBE_ARRAY
:
2083 return MALI_TEX_CUBE
;
2086 unreachable("Unknown target");
2090 static struct pipe_sampler_view
*
2091 panfrost_create_sampler_view(
2092 struct pipe_context
*pctx
,
2093 struct pipe_resource
*texture
,
2094 const struct pipe_sampler_view
*template)
2096 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2097 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2099 pipe_reference(NULL
, &texture
->reference
);
2101 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2104 so
->base
= *template;
2105 so
->base
.texture
= texture
;
2106 so
->base
.reference
.count
= 1;
2107 so
->base
.context
= pctx
;
2109 /* sampler_views correspond to texture descriptors, minus the texture
2110 * (data) itself. So, we serialise the descriptor here and cache it for
2113 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2115 unsigned char user_swizzle
[4] = {
2116 template->swizzle_r
,
2117 template->swizzle_g
,
2118 template->swizzle_b
,
2122 enum mali_format format
= panfrost_find_format(desc
);
2124 /* Check if we need to set a custom stride by computing the "expected"
2125 * stride and comparing it to what the BO actually wants. Only applies
2126 * to linear textures, since tiled/compressed textures have strict
2127 * alignment requirements for their strides as it is */
2129 unsigned first_level
= template->u
.tex
.first_level
;
2130 unsigned last_level
= template->u
.tex
.last_level
;
2132 if (prsrc
->layout
== PAN_LINEAR
) {
2133 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2134 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2135 unsigned width
= u_minify(texture
->width0
, l
);
2136 unsigned comp_stride
= width
* bytes_per_pixel
;
2138 if (comp_stride
!= actual_stride
) {
2139 so
->manual_stride
= true;
2145 /* In the hardware, array_size refers specifically to array textures,
2146 * whereas in Gallium, it also covers cubemaps */
2148 unsigned array_size
= texture
->array_size
;
2150 if (template->target
== PIPE_TEXTURE_CUBE
) {
2151 /* TODO: Cubemap arrays */
2152 assert(array_size
== 6);
2156 struct mali_texture_descriptor texture_descriptor
= {
2157 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2158 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2159 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2160 .array_size
= MALI_POSITIVE(array_size
),
2163 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2165 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2166 .type
= panfrost_translate_texture_type(template->target
),
2170 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2173 texture_descriptor
.levels
= last_level
- first_level
;
2175 so
->hw
= texture_descriptor
;
2177 return (struct pipe_sampler_view
*) so
;
2181 panfrost_set_sampler_views(
2182 struct pipe_context
*pctx
,
2183 enum pipe_shader_type shader
,
2184 unsigned start_slot
, unsigned num_views
,
2185 struct pipe_sampler_view
**views
)
2187 struct panfrost_context
*ctx
= pan_context(pctx
);
2189 assert(start_slot
== 0);
2191 unsigned new_nr
= 0;
2192 for (unsigned i
= 0; i
< num_views
; ++i
) {
2197 ctx
->sampler_view_count
[shader
] = new_nr
;
2198 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2200 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2204 panfrost_sampler_view_destroy(
2205 struct pipe_context
*pctx
,
2206 struct pipe_sampler_view
*view
)
2208 pipe_resource_reference(&view
->texture
, NULL
);
2213 panfrost_set_shader_buffers(
2214 struct pipe_context
*pctx
,
2215 enum pipe_shader_type shader
,
2216 unsigned start
, unsigned count
,
2217 const struct pipe_shader_buffer
*buffers
,
2218 unsigned writable_bitmask
)
2220 struct panfrost_context
*ctx
= pan_context(pctx
);
2222 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2223 buffers
, start
, count
);
2226 /* Hints that a framebuffer should use AFBC where possible */
2230 struct panfrost_screen
*screen
,
2231 const struct pipe_framebuffer_state
*fb
)
2233 /* AFBC implemenation incomplete; hide it */
2234 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2236 /* Hint AFBC to the resources bound to each color buffer */
2238 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2239 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2240 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2241 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2244 /* Also hint it to the depth buffer */
2247 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2248 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2253 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2254 const struct pipe_framebuffer_state
*fb
)
2256 struct panfrost_context
*ctx
= pan_context(pctx
);
2258 /* Flush when switching framebuffers, but not if the framebuffer
2259 * state is being restored by u_blitter
2262 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
2263 bool is_scanout
= panfrost_batch_is_scanout(batch
);
2264 bool has_draws
= batch
->last_job
.gpu
;
2266 /* Bail out early when the current and new states are the same. */
2267 if (util_framebuffer_state_equal(&ctx
->pipe_framebuffer
, fb
))
2270 /* The wallpaper logic sets a new FB state before doing the blit and
2271 * restore the old one when it's done. Those FB states are reported to
2272 * be different because the surface they are pointing to are different,
2273 * but those surfaces actually point to the same cbufs/zbufs. In that
2274 * case we definitely don't want new FB descs to be emitted/attached
2275 * since the job is expected to be flushed just after the blit is done,
2276 * so let's just copy the new state and return here.
2278 if (ctx
->wallpaper_batch
) {
2279 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2283 if (!is_scanout
|| has_draws
)
2284 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2286 assert(!ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
&&
2287 !ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
2289 /* Invalidate the FBO job cache since we've just been assigned a new
2294 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2296 /* Given that we're rendering, we'd love to have compression */
2297 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
2299 panfrost_hint_afbc(screen
, &ctx
->pipe_framebuffer
);
2300 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
2301 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
2305 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2306 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2308 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2312 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2315 struct panfrost_context
*ctx
= pan_context(pipe
);
2316 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2317 ctx
->depth_stencil
= depth_stencil
;
2322 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2323 * emulated in the fragment shader */
2325 if (depth_stencil
->alpha
.enabled
) {
2326 /* We need to trigger a new shader (maybe) */
2327 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2331 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2333 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2334 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2336 /* If back-stencil is not enabled, use the front values */
2337 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2338 unsigned back_index
= back_enab
? 1 : 0;
2340 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2341 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2343 /* Depth state (TODO: Refactor) */
2344 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2346 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2348 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2349 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2351 /* Bounds test not implemented */
2352 assert(!depth_stencil
->depth
.bounds_test
);
2354 ctx
->dirty
|= PAN_DIRTY_FS
;
2358 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2364 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2365 unsigned sample_mask
)
2370 panfrost_set_clip_state(struct pipe_context
*pipe
,
2371 const struct pipe_clip_state
*clip
)
2373 //struct panfrost_context *panfrost = pan_context(pipe);
2377 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2378 unsigned start_slot
,
2379 unsigned num_viewports
,
2380 const struct pipe_viewport_state
*viewports
)
2382 struct panfrost_context
*ctx
= pan_context(pipe
);
2384 assert(start_slot
== 0);
2385 assert(num_viewports
== 1);
2387 ctx
->pipe_viewport
= *viewports
;
2391 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2392 unsigned start_slot
,
2393 unsigned num_scissors
,
2394 const struct pipe_scissor_state
*scissors
)
2396 struct panfrost_context
*ctx
= pan_context(pipe
);
2398 assert(start_slot
== 0);
2399 assert(num_scissors
== 1);
2401 ctx
->scissor
= *scissors
;
2405 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2406 const struct pipe_poly_stipple
*stipple
)
2408 //struct panfrost_context *panfrost = pan_context(pipe);
2412 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2415 struct panfrost_context
*ctx
= pan_context(pipe
);
2416 ctx
->active_queries
= enable
;
2420 panfrost_destroy(struct pipe_context
*pipe
)
2422 struct panfrost_context
*panfrost
= pan_context(pipe
);
2424 if (panfrost
->blitter
)
2425 util_blitter_destroy(panfrost
->blitter
);
2427 if (panfrost
->blitter_wallpaper
)
2428 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2430 panfrost_bo_unreference(panfrost
->scratchpad
);
2431 panfrost_bo_unreference(panfrost
->tiler_heap
);
2432 panfrost_bo_unreference(panfrost
->tiler_dummy
);
2437 static struct pipe_query
*
2438 panfrost_create_query(struct pipe_context
*pipe
,
2442 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2447 return (struct pipe_query
*) q
;
2451 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2457 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2459 struct panfrost_context
*ctx
= pan_context(pipe
);
2460 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2461 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
2463 switch (query
->type
) {
2464 case PIPE_QUERY_OCCLUSION_COUNTER
:
2465 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2466 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2467 /* Allocate a word for the query results to be stored */
2468 query
->transfer
= panfrost_allocate_transient(batch
, sizeof(unsigned));
2469 ctx
->occlusion_query
= query
;
2472 /* Geometry statistics are computed in the driver. XXX: geom/tess
2475 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2476 query
->start
= ctx
->prims_generated
;
2478 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2479 query
->start
= ctx
->tf_prims_generated
;
2483 fprintf(stderr
, "Skipping query %u\n", query
->type
);
2491 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2493 struct panfrost_context
*ctx
= pan_context(pipe
);
2494 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2496 switch (query
->type
) {
2497 case PIPE_QUERY_OCCLUSION_COUNTER
:
2498 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2499 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2500 ctx
->occlusion_query
= NULL
;
2502 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2503 query
->end
= ctx
->prims_generated
;
2505 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2506 query
->end
= ctx
->tf_prims_generated
;
2514 panfrost_get_query_result(struct pipe_context
*pipe
,
2515 struct pipe_query
*q
,
2517 union pipe_query_result
*vresult
)
2519 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2522 switch (query
->type
) {
2523 case PIPE_QUERY_OCCLUSION_COUNTER
:
2524 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2525 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2527 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2529 /* Read back the query results */
2530 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2531 unsigned passed
= *result
;
2533 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2534 vresult
->u64
= passed
;
2536 vresult
->b
= !!passed
;
2541 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2542 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2543 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2544 vresult
->u64
= query
->end
- query
->start
;
2548 DBG("Skipped query get %u\n", query
->type
);
2555 static struct pipe_stream_output_target
*
2556 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2557 struct pipe_resource
*prsc
,
2558 unsigned buffer_offset
,
2559 unsigned buffer_size
)
2561 struct pipe_stream_output_target
*target
;
2563 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2568 pipe_reference_init(&target
->reference
, 1);
2569 pipe_resource_reference(&target
->buffer
, prsc
);
2571 target
->context
= pctx
;
2572 target
->buffer_offset
= buffer_offset
;
2573 target
->buffer_size
= buffer_size
;
2579 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2580 struct pipe_stream_output_target
*target
)
2582 pipe_resource_reference(&target
->buffer
, NULL
);
2583 ralloc_free(target
);
2587 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2588 unsigned num_targets
,
2589 struct pipe_stream_output_target
**targets
,
2590 const unsigned *offsets
)
2592 struct panfrost_context
*ctx
= pan_context(pctx
);
2593 struct panfrost_streamout
*so
= &ctx
->streamout
;
2595 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2597 for (unsigned i
= 0; i
< num_targets
; i
++) {
2598 if (offsets
[i
] != -1)
2599 so
->offsets
[i
] = offsets
[i
];
2601 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2604 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2605 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2607 so
->num_targets
= num_targets
;
2611 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2613 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2614 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2616 ctx
->scratchpad
= panfrost_bo_create(screen
, 64 * 4 * 4096, 0);
2617 ctx
->tiler_heap
= panfrost_bo_create(screen
, 4096 * 4096,
2620 ctx
->tiler_dummy
= panfrost_bo_create(screen
, 4096,
2622 assert(ctx
->scratchpad
&& ctx
->tiler_heap
&& ctx
->tiler_dummy
);
2625 /* New context creation, which also does hardware initialisation since I don't
2626 * know the better way to structure this :smirk: */
2628 struct pipe_context
*
2629 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2631 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2632 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2633 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2635 ctx
->is_t6xx
= pscreen
->gpu_id
< 0x0700; /* Literally, "earlier than T700" */
2637 gallium
->screen
= screen
;
2639 gallium
->destroy
= panfrost_destroy
;
2641 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2643 gallium
->flush
= panfrost_flush
;
2644 gallium
->clear
= panfrost_clear
;
2645 gallium
->draw_vbo
= panfrost_draw_vbo
;
2647 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2648 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2649 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2651 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2653 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2654 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2655 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2657 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2658 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2659 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2661 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2662 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2663 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2665 gallium
->create_fs_state
= panfrost_create_shader_state
;
2666 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2667 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2669 gallium
->create_vs_state
= panfrost_create_shader_state
;
2670 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2671 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2673 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2674 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2675 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2677 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2678 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2679 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2681 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2683 gallium
->set_clip_state
= panfrost_set_clip_state
;
2684 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2685 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2686 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2687 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2689 gallium
->create_query
= panfrost_create_query
;
2690 gallium
->destroy_query
= panfrost_destroy_query
;
2691 gallium
->begin_query
= panfrost_begin_query
;
2692 gallium
->end_query
= panfrost_end_query
;
2693 gallium
->get_query_result
= panfrost_get_query_result
;
2695 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2696 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2697 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2699 panfrost_resource_context_init(gallium
);
2700 panfrost_blend_context_init(gallium
);
2701 panfrost_compute_context_init(gallium
);
2705 ret
= drmSyncobjCreate(pscreen
->fd
, DRM_SYNCOBJ_CREATE_SIGNALED
,
2709 panfrost_setup_hardware(ctx
);
2712 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2713 gallium
->const_uploader
= gallium
->stream_uploader
;
2714 assert(gallium
->stream_uploader
);
2716 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2717 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2719 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2721 ctx
->blitter
= util_blitter_create(gallium
);
2722 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2724 assert(ctx
->blitter
);
2725 assert(ctx
->blitter_wallpaper
);
2727 /* Prepare for render! */
2729 panfrost_batch_init(ctx
);
2730 panfrost_emit_vertex_payload(ctx
);
2731 panfrost_emit_tiler_payload(ctx
);
2732 panfrost_invalidate_frame(ctx
);
2733 panfrost_default_shader_backend(ctx
);