2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "pan_context.h"
31 #include "pan_format.h"
33 #include "util/macros.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_upload_mgr.h"
37 #include "util/u_memory.h"
38 #include "util/u_vbuf.h"
39 #include "util/half_float.h"
40 #include "util/u_helpers.h"
41 #include "util/u_format.h"
42 #include "util/u_prim.h"
43 #include "util/u_prim_restart.h"
44 #include "indices/u_primconvert.h"
45 #include "tgsi/tgsi_parse.h"
46 #include "tgsi/tgsi_from_mesa.h"
47 #include "util/u_math.h"
49 #include "pan_screen.h"
50 #include "pan_blending.h"
51 #include "pan_blend_shaders.h"
54 /* Framebuffer descriptor */
56 static struct midgard_tiler_descriptor
57 panfrost_emit_midg_tiler(
58 struct panfrost_context
*ctx
,
61 unsigned vertex_count
)
63 struct midgard_tiler_descriptor t
= {};
64 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
67 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
69 /* Compute the polygon header size and use that to offset the body */
71 unsigned header_size
= panfrost_tiler_header_size(
72 width
, height
, t
.hierarchy_mask
);
74 t
.polygon_list_size
= panfrost_tiler_full_size(
75 width
, height
, t
.hierarchy_mask
);
79 if (t
.hierarchy_mask
) {
80 t
.polygon_list
= panfrost_job_get_polygon_list(batch
,
81 header_size
+ t
.polygon_list_size
);
84 /* Allow the entire tiler heap */
85 t
.heap_start
= ctx
->tiler_heap
.bo
->gpu
;
87 ctx
->tiler_heap
.bo
->gpu
+ ctx
->tiler_heap
.bo
->size
;
89 /* The tiler is disabled, so don't allow the tiler heap */
90 t
.heap_start
= ctx
->tiler_heap
.bo
->gpu
;
91 t
.heap_end
= t
.heap_start
;
93 /* Use a dummy polygon list */
94 t
.polygon_list
= ctx
->tiler_dummy
.bo
->gpu
;
96 /* Disable the tiler */
97 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
100 t
.polygon_list_body
=
101 t
.polygon_list
+ header_size
;
106 struct mali_single_framebuffer
107 panfrost_emit_sfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
109 unsigned width
= ctx
->pipe_framebuffer
.width
;
110 unsigned height
= ctx
->pipe_framebuffer
.height
;
112 struct mali_single_framebuffer framebuffer
= {
113 .width
= MALI_POSITIVE(width
),
114 .height
= MALI_POSITIVE(height
),
116 .format
= 0x30000000,
117 .clear_flags
= 0x1000,
118 .unknown_address_0
= ctx
->scratchpad
.bo
->gpu
,
119 .tiler
= panfrost_emit_midg_tiler(ctx
,
120 width
, height
, vertex_count
),
126 struct bifrost_framebuffer
127 panfrost_emit_mfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
129 unsigned width
= ctx
->pipe_framebuffer
.width
;
130 unsigned height
= ctx
->pipe_framebuffer
.height
;
132 struct bifrost_framebuffer framebuffer
= {
133 .unk0
= 0x1e5, /* 1e4 if no spill */
134 .width1
= MALI_POSITIVE(width
),
135 .height1
= MALI_POSITIVE(height
),
136 .width2
= MALI_POSITIVE(width
),
137 .height2
= MALI_POSITIVE(height
),
141 .rt_count_1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.nr_cbufs
),
146 .scratchpad
= ctx
->scratchpad
.bo
->gpu
,
147 .tiler
= panfrost_emit_midg_tiler(ctx
,
148 width
, height
, vertex_count
)
154 /* Are we currently rendering to the screen (rather than an FBO)? */
157 panfrost_is_scanout(struct panfrost_context
*ctx
)
159 /* If there is no color buffer, it's an FBO */
160 if (ctx
->pipe_framebuffer
.nr_cbufs
!= 1)
163 /* If we're too early that no framebuffer was sent, it's scanout */
164 if (!ctx
->pipe_framebuffer
.cbufs
[0])
167 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
168 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
169 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
174 struct pipe_context
*pipe
,
176 const union pipe_color_union
*color
,
177 double depth
, unsigned stencil
)
179 struct panfrost_context
*ctx
= pan_context(pipe
);
180 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
182 panfrost_job_clear(ctx
, job
, buffers
, color
, depth
, stencil
);
186 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
188 struct bifrost_framebuffer mfbd
= panfrost_emit_mfbd(ctx
, ~0);
190 return panfrost_upload_transient(ctx
, &mfbd
, sizeof(mfbd
)) | MALI_MFBD
;
194 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
196 struct mali_single_framebuffer sfbd
= panfrost_emit_sfbd(ctx
, ~0);
198 return panfrost_upload_transient(ctx
, &sfbd
, sizeof(sfbd
)) | MALI_SFBD
;
202 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
204 /* Skip the attach if we can */
206 if (ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
) {
207 assert(ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
211 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
212 mali_ptr framebuffer
= screen
->require_sfbd
?
213 panfrost_attach_vt_sfbd(ctx
) :
214 panfrost_attach_vt_mfbd(ctx
);
216 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
217 ctx
->payloads
[i
].postfix
.framebuffer
= framebuffer
;
220 /* Reset per-frame context, called on context initialisation as well as after
221 * flushing a frame */
224 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
226 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
227 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
230 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
233 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
235 /* TODO: When does this need to be handled? */
236 ctx
->active_queries
= true;
239 /* In practice, every field of these payloads should be configurable
240 * arbitrarily, which means these functions are basically catch-all's for
241 * as-of-yet unwavering unknowns */
244 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
246 /* 0x2 bit clear on 32-bit T6XX */
248 struct midgard_payload_vertex_tiler payload
= {
249 .gl_enables
= 0x4 | 0x2,
252 /* Vertex and compute are closely coupled, so share a payload */
254 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
255 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
259 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
261 struct midgard_payload_vertex_tiler payload
= {
263 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
267 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
271 translate_tex_wrap(enum pipe_tex_wrap w
)
274 case PIPE_TEX_WRAP_REPEAT
:
275 return MALI_WRAP_REPEAT
;
277 /* TODO: lower GL_CLAMP? */
278 case PIPE_TEX_WRAP_CLAMP
:
279 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
280 return MALI_WRAP_CLAMP_TO_EDGE
;
282 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
283 return MALI_WRAP_CLAMP_TO_BORDER
;
285 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
286 return MALI_WRAP_MIRRORED_REPEAT
;
289 unreachable("Invalid wrap");
294 panfrost_translate_compare_func(enum pipe_compare_func in
)
297 case PIPE_FUNC_NEVER
:
298 return MALI_FUNC_NEVER
;
301 return MALI_FUNC_LESS
;
303 case PIPE_FUNC_EQUAL
:
304 return MALI_FUNC_EQUAL
;
306 case PIPE_FUNC_LEQUAL
:
307 return MALI_FUNC_LEQUAL
;
309 case PIPE_FUNC_GREATER
:
310 return MALI_FUNC_GREATER
;
312 case PIPE_FUNC_NOTEQUAL
:
313 return MALI_FUNC_NOTEQUAL
;
315 case PIPE_FUNC_GEQUAL
:
316 return MALI_FUNC_GEQUAL
;
318 case PIPE_FUNC_ALWAYS
:
319 return MALI_FUNC_ALWAYS
;
322 unreachable("Invalid func");
327 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
330 case PIPE_FUNC_NEVER
:
331 return MALI_ALT_FUNC_NEVER
;
334 return MALI_ALT_FUNC_LESS
;
336 case PIPE_FUNC_EQUAL
:
337 return MALI_ALT_FUNC_EQUAL
;
339 case PIPE_FUNC_LEQUAL
:
340 return MALI_ALT_FUNC_LEQUAL
;
342 case PIPE_FUNC_GREATER
:
343 return MALI_ALT_FUNC_GREATER
;
345 case PIPE_FUNC_NOTEQUAL
:
346 return MALI_ALT_FUNC_NOTEQUAL
;
348 case PIPE_FUNC_GEQUAL
:
349 return MALI_ALT_FUNC_GEQUAL
;
351 case PIPE_FUNC_ALWAYS
:
352 return MALI_ALT_FUNC_ALWAYS
;
355 unreachable("Invalid alt func");
360 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
363 case PIPE_STENCIL_OP_KEEP
:
364 return MALI_STENCIL_KEEP
;
366 case PIPE_STENCIL_OP_ZERO
:
367 return MALI_STENCIL_ZERO
;
369 case PIPE_STENCIL_OP_REPLACE
:
370 return MALI_STENCIL_REPLACE
;
372 case PIPE_STENCIL_OP_INCR
:
373 return MALI_STENCIL_INCR
;
375 case PIPE_STENCIL_OP_DECR
:
376 return MALI_STENCIL_DECR
;
378 case PIPE_STENCIL_OP_INCR_WRAP
:
379 return MALI_STENCIL_INCR_WRAP
;
381 case PIPE_STENCIL_OP_DECR_WRAP
:
382 return MALI_STENCIL_DECR_WRAP
;
384 case PIPE_STENCIL_OP_INVERT
:
385 return MALI_STENCIL_INVERT
;
388 unreachable("Invalid stencil op");
393 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
395 out
->ref
= 0; /* Gallium gets it from elsewhere */
397 out
->mask
= in
->valuemask
;
398 out
->func
= panfrost_translate_compare_func(in
->func
);
399 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
400 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
401 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
405 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
407 struct mali_shader_meta shader
= {
408 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
410 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
411 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
414 /* unknown2_4 has 0x10 bit set on T6XX. We don't know why this is
415 * required (independent of 32-bit/64-bit descriptors), or why it's not
416 * used on later GPU revisions. Otherwise, all shader jobs fault on
417 * these earlier chips (perhaps this is a chicken bit of some kind).
418 * More investigation is needed. */
421 shader
.unknown2_4
|= 0x10;
424 struct pipe_stencil_state default_stencil
= {
426 .func
= PIPE_FUNC_ALWAYS
,
427 .fail_op
= MALI_STENCIL_KEEP
,
428 .zfail_op
= MALI_STENCIL_KEEP
,
429 .zpass_op
= MALI_STENCIL_KEEP
,
434 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
435 shader
.stencil_mask_front
= default_stencil
.writemask
;
437 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
438 shader
.stencil_mask_back
= default_stencil
.writemask
;
440 if (default_stencil
.enabled
)
441 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
443 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
446 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
447 * graphics command stream. It should be called once per draw, accordding to
448 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
449 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
452 struct panfrost_transfer
453 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
455 struct mali_job_descriptor_header job
= {
456 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
457 .job_descriptor_size
= 1,
460 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
462 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
463 memcpy(transfer
.cpu
, &job
, sizeof(job
));
464 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
469 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
471 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
472 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
474 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
478 panfrost_writes_point_size(struct panfrost_context
*ctx
)
480 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
481 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
483 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
486 /* Stage the attribute descriptors so we can adjust src_offset
487 * to let BOs align nicely */
490 panfrost_stage_attributes(struct panfrost_context
*ctx
)
492 struct panfrost_vertex_state
*so
= ctx
->vertex
;
494 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
495 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
496 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
498 /* Copy as-is for the first pass */
499 memcpy(target
, so
->hw
, sz
);
501 /* Fixup offsets for the second pass. Recall that the hardware
502 * calculates attribute addresses as:
504 * addr = base + (stride * vtx) + src_offset;
506 * However, on Mali, base must be aligned to 64-bytes, so we
509 * base' = base & ~63 = base - (base & 63)
511 * To compensate when using base' (see emit_vertex_data), we have
512 * to adjust src_offset by the masked off piece:
514 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
515 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
516 * = base + (stride * vtx) + src_offset
522 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
524 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
525 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
526 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
527 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
529 /* Adjust by the masked off bits of the offset */
530 target
[i
].src_offset
+= (addr
& 63);
532 /* Also, somewhat obscurely per-instance data needs to be
533 * offset in response to a delayed start in an indexed draw */
535 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
536 target
[i
].src_offset
-= buf
->stride
* start
;
542 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
546 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
548 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
550 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
553 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
554 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
556 struct panfrost_transfer transfer
=
557 panfrost_allocate_transient(ctx
, transfer_size
);
559 struct mali_sampler_descriptor
*desc
=
560 (struct mali_sampler_descriptor
*) transfer
.cpu
;
562 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
563 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
565 upload
= transfer
.gpu
;
568 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
572 static enum mali_texture_layout
573 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
575 /* TODO: other linear depth textures */
576 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
578 switch (rsrc
->layout
) {
580 return MALI_TEXTURE_AFBC
;
583 return MALI_TEXTURE_TILED
;
585 return is_depth
? MALI_TEXTURE_TILED
: MALI_TEXTURE_LINEAR
;
587 unreachable("Invalid texture layout");
593 struct panfrost_context
*ctx
,
594 struct panfrost_sampler_view
*view
)
599 struct pipe_sampler_view
*pview
= &view
->base
;
600 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
602 /* Do we interleave an explicit stride with every element? */
604 bool has_manual_stride
= view
->manual_stride
;
606 /* For easy access */
608 assert(pview
->target
!= PIPE_BUFFER
);
609 unsigned first_level
= pview
->u
.tex
.first_level
;
610 unsigned last_level
= pview
->u
.tex
.last_level
;
611 unsigned first_layer
= pview
->u
.tex
.first_layer
;
612 unsigned last_layer
= pview
->u
.tex
.last_layer
;
614 /* Lower-bit is set when sampling from colour AFBC */
615 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
616 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
617 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
619 /* Add the BO to the job so it's retained until the job is done. */
620 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
621 panfrost_job_add_bo(job
, rsrc
->bo
);
623 /* Add the usage flags in, since they can change across the CSO
624 * lifetime due to layout switches */
626 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
627 view
->hw
.format
.manual_stride
= has_manual_stride
;
629 /* Inject the addresses in, interleaving mip levels, cube faces, and
630 * strides in that order */
634 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
635 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
637 view
->hw
.payload
[idx
++] =
638 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
640 if (has_manual_stride
) {
641 view
->hw
.payload
[idx
++] =
642 rsrc
->slices
[l
].stride
;
647 return panfrost_upload_transient(ctx
, &view
->hw
,
648 sizeof(struct mali_texture_descriptor
));
652 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
654 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
655 mali_ptr trampoline
= 0;
657 if (ctx
->sampler_view_count
[t
]) {
658 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
660 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
662 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
664 trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
667 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
671 struct sysval_uniform
{
680 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
681 struct sysval_uniform
*uniform
)
683 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
685 uniform
->f
[0] = vp
->scale
[0];
686 uniform
->f
[1] = vp
->scale
[1];
687 uniform
->f
[2] = vp
->scale
[2];
690 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
691 struct sysval_uniform
*uniform
)
693 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
695 uniform
->f
[0] = vp
->translate
[0];
696 uniform
->f
[1] = vp
->translate
[1];
697 uniform
->f
[2] = vp
->translate
[2];
700 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
701 enum pipe_shader_type st
,
702 unsigned int sysvalid
,
703 struct sysval_uniform
*uniform
)
705 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
706 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
707 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
708 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
711 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
714 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
715 tex
->u
.tex
.first_level
);
718 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
719 tex
->u
.tex
.first_level
);
722 uniform
->i
[dim
] = tex
->texture
->array_size
;
725 static void panfrost_upload_ssbo_sysval(
726 struct panfrost_context
*ctx
,
727 enum pipe_shader_type st
,
729 struct sysval_uniform
*uniform
)
731 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
732 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
734 /* Compute address */
735 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
736 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
738 panfrost_job_add_bo(batch
, bo
);
740 /* Upload address and size as sysval */
741 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
742 uniform
->u
[2] = sb
.buffer_size
;
745 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
746 struct sysval_uniform
*uniform
)
748 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
749 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
750 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
753 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
754 struct panfrost_shader_state
*ss
,
755 enum pipe_shader_type st
)
757 struct sysval_uniform
*uniforms
= (void *)buf
;
759 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
760 int sysval
= ss
->sysval
[i
];
762 switch (PAN_SYSVAL_TYPE(sysval
)) {
763 case PAN_SYSVAL_VIEWPORT_SCALE
:
764 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
766 case PAN_SYSVAL_VIEWPORT_OFFSET
:
767 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
769 case PAN_SYSVAL_TEXTURE_SIZE
:
770 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
773 case PAN_SYSVAL_SSBO
:
774 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
777 case PAN_SYSVAL_NUM_WORK_GROUPS
:
778 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
788 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
790 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
791 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
794 return rsrc
->bo
->cpu
;
795 else if (cb
->user_buffer
)
796 return cb
->user_buffer
;
798 unreachable("No constant buffer");
802 panfrost_map_constant_buffer_gpu(
803 struct panfrost_context
*ctx
,
804 struct panfrost_constant_buffer
*buf
,
807 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
808 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
811 return rsrc
->bo
->gpu
;
812 else if (cb
->user_buffer
)
813 return panfrost_upload_transient(ctx
, cb
->user_buffer
, cb
->buffer_size
);
815 unreachable("No constant buffer");
818 /* Compute number of UBOs active (more specifically, compute the highest UBO
819 * number addressable -- if there are gaps, include them in the count anyway).
820 * We always include UBO #0 in the count, since we *need* uniforms enabled for
824 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
826 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
827 return 32 - __builtin_clz(mask
);
830 /* Fixes up a shader state with current state, returning a GPU address to the
834 panfrost_patch_shader_state(
835 struct panfrost_context
*ctx
,
836 struct panfrost_shader_state
*ss
,
837 enum pipe_shader_type stage
,
840 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
841 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
843 ss
->tripipe
->midgard1
.flags
= 0x220;
845 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
846 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
848 /* We can't reuse over frames; that's not safe. The descriptor must be
849 * transient uploaded */
852 return panfrost_upload_transient(ctx
,
854 sizeof(struct mali_shader_meta
));
857 /* If we don't need an upload, don't bother */
863 panfrost_patch_shader_state_compute(
864 struct panfrost_context
*ctx
,
865 enum pipe_shader_type stage
,
868 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
871 ctx
->payloads
[stage
].postfix
._shader_upper
= 0;
875 struct panfrost_shader_state
*s
= &all
->variants
[all
->active_variant
];
877 ctx
->payloads
[stage
].postfix
._shader_upper
=
878 panfrost_patch_shader_state(ctx
, s
, stage
, should_upload
) >> 4;
881 /* Go through dirty flags and actualise them in the cmdstream. */
884 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
886 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
887 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
889 panfrost_attach_vt_framebuffer(ctx
);
891 if (with_vertex_data
) {
892 panfrost_emit_vertex_data(job
);
894 /* Varyings emitted for -all- geometry */
895 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
896 panfrost_emit_varying_descriptor(ctx
, total_count
);
899 bool msaa
= ctx
->rasterizer
->base
.multisample
;
901 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
902 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
904 /* TODO: Sample size */
905 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
906 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
909 panfrost_job_set_requirements(ctx
, job
);
911 if (ctx
->occlusion_query
) {
912 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
913 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
916 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_VERTEX
, true);
917 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_COMPUTE
, true);
919 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
920 /* Check if we need to link the gl_PointSize varying */
921 if (!panfrost_writes_point_size(ctx
)) {
922 /* If the size is constant, write it out. Otherwise,
923 * don't touch primitive_size (since we would clobber
924 * the pointer there) */
926 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
930 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
931 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
932 ctx
->dirty
|= PAN_DIRTY_FS
;
934 if (ctx
->dirty
& PAN_DIRTY_FS
) {
935 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
936 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
938 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
940 panfrost_job_add_bo(job
, variant
->bo
);
942 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
945 COPY(attribute_count
);
950 COPY(midgard1
.uniform_count
);
951 COPY(midgard1
.uniform_buffer_count
);
952 COPY(midgard1
.work_count
);
953 COPY(midgard1
.flags
);
954 COPY(midgard1
.unknown2
);
958 /* Get blending setup */
959 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
961 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
963 for (unsigned c
= 0; c
< rt_count
; ++c
)
964 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
966 /* If there is a blend shader, work registers are shared. XXX: opt */
968 for (unsigned c
= 0; c
< rt_count
; ++c
) {
969 if (blend
[c
].is_shader
)
970 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
973 /* Set late due to depending on render state */
974 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
976 /* Depending on whether it's legal to in the given shader, we
977 * try to enable early-z testing (or forward-pixel kill?) */
979 if (!variant
->can_discard
)
980 flags
|= MALI_EARLY_Z
;
982 /* Any time texturing is used, derivatives are implicitly
983 * calculated, so we need to enable helper invocations */
985 if (variant
->helper_invocations
)
986 flags
|= MALI_HELPER_INVOCATIONS
;
988 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
990 /* Assign the stencil refs late */
992 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
993 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
994 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
996 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
997 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
999 /* CAN_DISCARD should be set if the fragment shader possibly
1000 * contains a 'discard' instruction. It is likely this is
1001 * related to optimizations related to forward-pixel kill, as
1002 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1003 * thing?" by Peter Harris
1006 if (variant
->can_discard
) {
1007 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1008 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1011 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1012 * *also* copied to the blend_meta appended (by convention),
1013 * but this is the field actually read by the hardware. (Or
1014 * maybe both are read...?) */
1016 if (blend
[0].is_shader
) {
1017 ctx
->fragment_shader_core
.blend
.shader
=
1018 blend
[0].shader
.bo
->gpu
| blend
[0].shader
.first_tag
;
1020 ctx
->fragment_shader_core
.blend
.shader
= 0;
1023 if (screen
->require_sfbd
) {
1024 /* When only a single render target platform is used, the blend
1025 * information is inside the shader meta itself. We
1026 * additionally need to signal CAN_DISCARD for nontrivial blend
1027 * modes (so we're able to read back the destination buffer) */
1029 if (!blend
[0].is_shader
) {
1030 ctx
->fragment_shader_core
.blend
.equation
=
1031 *blend
[0].equation
.equation
;
1032 ctx
->fragment_shader_core
.blend
.constant
=
1033 blend
[0].equation
.constant
;
1036 if (!blend
[0].no_blending
) {
1037 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1041 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1042 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1043 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1045 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1047 if (!screen
->require_sfbd
) {
1048 /* Additional blend descriptor tacked on for jobs using MFBD */
1050 struct midgard_blend_rt rts
[4];
1052 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1053 unsigned blend_count
= 0x200;
1055 if (blend
[i
].is_shader
) {
1056 /* For a blend shader, the bottom nibble corresponds to
1057 * the number of work registers used, which signals the
1058 * -existence- of a blend shader */
1060 assert(blend
[i
].shader
.work_count
>= 2);
1061 blend_count
|= MIN2(blend
[i
].shader
.work_count
, 3);
1063 /* Otherwise, the bottom bit simply specifies if
1064 * blending (anything other than REPLACE) is enabled */
1066 if (!blend
[i
].no_blending
)
1072 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1073 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1074 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1076 rts
[i
].flags
= blend_count
;
1079 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1081 if (!ctx
->blend
->base
.dither
)
1082 rts
[i
].flags
|= MALI_BLEND_NO_DITHER
;
1084 /* TODO: sRGB in blend shaders is currently
1085 * unimplemented. Contact me (Alyssa) if you're
1086 * interested in working on this. We have
1087 * native Midgard ops for helping here, but
1088 * they're not well-understood yet. */
1090 assert(!(is_srgb
&& blend
[i
].is_shader
));
1092 if (blend
[i
].is_shader
) {
1093 rts
[i
].blend
.shader
= blend
[i
].shader
.bo
->gpu
| blend
[i
].shader
.first_tag
;
1095 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1096 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1100 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1104 /* We stage to transient, so always dirty.. */
1106 panfrost_stage_attributes(ctx
);
1108 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1109 panfrost_upload_sampler_descriptors(ctx
);
1111 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1112 panfrost_upload_texture_descriptors(ctx
);
1114 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1116 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1117 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1122 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1124 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1126 /* Uniforms are implicitly UBO #0 */
1127 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1129 /* Allocate room for the sysval and the uniforms */
1130 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1131 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1132 size_t size
= sys_size
+ uniform_size
;
1133 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1135 /* Upload sysvals requested by the shader */
1136 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1138 /* Upload uniforms */
1140 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1141 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1145 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1147 struct mali_vertex_tiler_postfix
*postfix
=
1148 &ctx
->payloads
[i
].postfix
;
1150 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1153 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1154 assert(ubo_count
>= 1);
1156 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1157 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1159 /* Upload uniforms as a UBO */
1160 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1161 ubos
[0].ptr
= transfer
.gpu
>> 2;
1163 /* The rest are honest-to-goodness UBOs */
1165 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1166 size_t sz
= buf
->cb
[ubo
].buffer_size
;
1168 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1169 bool empty
= sz
== 0;
1171 if (!enabled
|| empty
) {
1172 /* Stub out disabled UBOs to catch accesses */
1175 ubos
[ubo
].ptr
= 0xDEAD0000;
1179 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, buf
, ubo
);
1181 unsigned bytes_per_field
= 16;
1182 unsigned aligned
= ALIGN_POT(sz
, bytes_per_field
);
1183 unsigned fields
= aligned
/ bytes_per_field
;
1185 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1186 ubos
[ubo
].ptr
= gpu
>> 2;
1189 mali_ptr ubufs
= panfrost_upload_transient(ctx
, ubos
, sz
);
1190 postfix
->uniforms
= transfer
.gpu
;
1191 postfix
->uniform_buffers
= ubufs
;
1193 buf
->dirty_mask
= 0;
1196 /* TODO: Upload the viewport somewhere more appropriate */
1198 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1199 * (somewhat) asymmetric ints. */
1200 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1202 struct mali_viewport view
= {
1203 /* By default, do no viewport clipping, i.e. clip to (-inf,
1204 * inf) in each direction. Clipping to the viewport in theory
1205 * should work, but in practice causes issues when we're not
1206 * explicitly trying to scissor */
1208 .clip_minx
= -INFINITY
,
1209 .clip_miny
= -INFINITY
,
1210 .clip_maxx
= INFINITY
,
1211 .clip_maxy
= INFINITY
,
1217 /* Always scissor to the viewport by default. */
1218 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1219 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1221 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1222 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1224 /* Apply the scissor test */
1226 unsigned minx
, miny
, maxx
, maxy
;
1228 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1229 minx
= MAX2(ss
->minx
, vp_minx
);
1230 miny
= MAX2(ss
->miny
, vp_miny
);
1231 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1232 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1240 /* Hardware needs the min/max to be strictly ordered, so flip if we
1241 * need to. The viewport transformation in the vertex shader will
1242 * handle the negatives if we don't */
1245 unsigned temp
= miny
;
1251 unsigned temp
= minx
;
1256 /* Clamp to the framebuffer size as a last check */
1258 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1259 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1261 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1262 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1264 /* Update the job, unless we're doing wallpapering (whose lack of
1265 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1266 * just... be faster :) */
1268 if (!ctx
->wallpaper_batch
)
1269 panfrost_job_union_scissor(job
, minx
, miny
, maxx
, maxy
);
1273 view
.viewport0
[0] = minx
;
1274 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1276 view
.viewport0
[1] = miny
;
1277 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1279 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1280 panfrost_upload_transient(ctx
,
1282 sizeof(struct mali_viewport
));
1287 /* Corresponds to exactly one draw, but does not submit anything */
1290 panfrost_queue_draw(struct panfrost_context
*ctx
)
1292 /* Handle dirty flags now */
1293 panfrost_emit_for_draw(ctx
, true);
1295 /* If rasterizer discard is enable, only submit the vertex */
1297 bool rasterizer_discard
= ctx
->rasterizer
1298 && ctx
->rasterizer
->base
.rasterizer_discard
;
1300 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1301 struct panfrost_transfer tiler
;
1303 if (!rasterizer_discard
)
1304 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1306 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1308 if (rasterizer_discard
)
1309 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1310 else if (ctx
->wallpaper_batch
)
1311 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1313 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1316 /* The entire frame is in memory -- send it off to the kernel! */
1319 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1320 struct pipe_fence_handle
**fence
,
1321 struct panfrost_job
*job
)
1323 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1324 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1326 panfrost_job_submit(ctx
, job
);
1328 /* If visual, we can stall a frame */
1330 if (!flush_immediate
)
1331 panfrost_drm_force_flush_fragment(ctx
, fence
);
1333 screen
->last_fragment_flushed
= false;
1334 screen
->last_job
= job
;
1336 /* If readback, flush now (hurts the pipelined performance) */
1337 if (flush_immediate
)
1338 panfrost_drm_force_flush_fragment(ctx
, fence
);
1342 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1344 struct panfrost_context
*ctx
= pan_context(pipe
);
1346 /* Nothing to reload? TODO: MRT wallpapers */
1347 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1350 /* Check if the buffer has any content on it worth preserving */
1352 struct pipe_surface
*surf
= ctx
->pipe_framebuffer
.cbufs
[0];
1353 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1354 unsigned level
= surf
->u
.tex
.level
;
1356 if (!rsrc
->slices
[level
].initialized
)
1359 /* Save the batch */
1360 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1362 ctx
->wallpaper_batch
= batch
;
1364 /* Clamp the rendering area to the damage extent. The
1365 * KHR_partial_update() spec states that trying to render outside of
1366 * the damage region is "undefined behavior", so we should be safe.
1368 unsigned damage_width
= (rsrc
->damage
.extent
.maxx
- rsrc
->damage
.extent
.minx
);
1369 unsigned damage_height
= (rsrc
->damage
.extent
.maxy
- rsrc
->damage
.extent
.miny
);
1371 if (damage_width
&& damage_height
) {
1372 panfrost_job_intersection_scissor(batch
, rsrc
->damage
.extent
.minx
,
1373 rsrc
->damage
.extent
.miny
,
1374 rsrc
->damage
.extent
.maxx
,
1375 rsrc
->damage
.extent
.maxy
);
1378 /* FIXME: Looks like aligning on a tile is not enough, but
1379 * aligning on twice the tile size seems to works. We don't
1380 * know exactly what happens here but this deserves extra
1381 * investigation to figure it out.
1383 batch
->minx
= batch
->minx
& ~((MALI_TILE_LENGTH
* 2) - 1);
1384 batch
->miny
= batch
->miny
& ~((MALI_TILE_LENGTH
* 2) - 1);
1385 batch
->maxx
= MIN2(ALIGN_POT(batch
->maxx
, MALI_TILE_LENGTH
* 2),
1387 batch
->maxy
= MIN2(ALIGN_POT(batch
->maxy
, MALI_TILE_LENGTH
* 2),
1388 rsrc
->base
.height0
);
1390 struct pipe_scissor_state damage
;
1391 struct pipe_box rects
[4];
1393 /* Clamp the damage box to the rendering area. */
1394 damage
.minx
= MAX2(batch
->minx
, rsrc
->damage
.biggest_rect
.x
);
1395 damage
.miny
= MAX2(batch
->miny
, rsrc
->damage
.biggest_rect
.y
);
1396 damage
.maxx
= MIN2(batch
->maxx
,
1397 rsrc
->damage
.biggest_rect
.x
+
1398 rsrc
->damage
.biggest_rect
.width
);
1399 damage
.maxy
= MIN2(batch
->maxy
,
1400 rsrc
->damage
.biggest_rect
.y
+
1401 rsrc
->damage
.biggest_rect
.height
);
1403 /* One damage rectangle means we can end up with at most 4 reload
1405 * 1: left region, only exists if damage.x > 0
1406 * 2: right region, only exists if damage.x + damage.width < fb->width
1407 * 3: top region, only exists if damage.y > 0. The intersection with
1408 * the left and right regions are dropped
1409 * 4: bottom region, only exists if damage.y + damage.height < fb->height.
1410 * The intersection with the left and right regions are dropped
1412 * ____________________________
1419 * |_______|___________|______|
1421 u_box_2d(batch
->minx
, batch
->miny
, damage
.minx
- batch
->minx
,
1422 batch
->maxy
- batch
->miny
, &rects
[0]);
1423 u_box_2d(damage
.maxx
, batch
->miny
, batch
->maxx
- damage
.maxx
,
1424 batch
->maxy
- batch
->miny
, &rects
[1]);
1425 u_box_2d(damage
.minx
, batch
->miny
, damage
.maxx
- damage
.minx
,
1426 damage
.miny
- batch
->miny
, &rects
[2]);
1427 u_box_2d(damage
.minx
, damage
.maxy
, damage
.maxx
- damage
.minx
,
1428 batch
->maxy
- damage
.maxy
, &rects
[3]);
1430 for (unsigned i
= 0; i
< 4; i
++) {
1431 /* Width and height are always >= 0 even if width is declared as a
1432 * signed integer: u_box_2d() helper takes unsigned args and
1433 * panfrost_set_damage_region() is taking care of clamping
1436 if (!rects
[i
].width
|| !rects
[i
].height
)
1439 /* Blit the wallpaper in */
1440 panfrost_blit_wallpaper(ctx
, &rects
[i
]);
1442 ctx
->wallpaper_batch
= NULL
;
1447 struct pipe_context
*pipe
,
1448 struct pipe_fence_handle
**fence
,
1451 struct panfrost_context
*ctx
= pan_context(pipe
);
1452 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1454 /* Nothing to do! */
1455 if (!job
->last_job
.gpu
&& !job
->clear
) return;
1457 if (!job
->clear
&& job
->last_tiler
.gpu
)
1458 panfrost_draw_wallpaper(&ctx
->base
);
1460 /* Whether to stall the pipeline for immediately correct results. Since
1461 * pipelined rendering is quite broken right now (to be fixed by the
1462 * panfrost_job refactor, just take the perf hit for correctness) */
1463 bool flush_immediate
= /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1465 /* Submit the frame itself */
1466 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1468 /* Prepare for the next frame */
1469 panfrost_invalidate_frame(ctx
);
1472 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1475 g2m_draw_mode(enum pipe_prim_type mode
)
1478 DEFINE_CASE(POINTS
);
1480 DEFINE_CASE(LINE_LOOP
);
1481 DEFINE_CASE(LINE_STRIP
);
1482 DEFINE_CASE(TRIANGLES
);
1483 DEFINE_CASE(TRIANGLE_STRIP
);
1484 DEFINE_CASE(TRIANGLE_FAN
);
1486 DEFINE_CASE(QUAD_STRIP
);
1487 DEFINE_CASE(POLYGON
);
1490 unreachable("Invalid draw mode");
1497 panfrost_translate_index_size(unsigned size
)
1501 return MALI_DRAW_INDEXED_UINT8
;
1504 return MALI_DRAW_INDEXED_UINT16
;
1507 return MALI_DRAW_INDEXED_UINT32
;
1510 unreachable("Invalid index size");
1514 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1515 * good for the duration of the draw (transient), could last longer */
1518 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1520 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1522 off_t offset
= info
->start
* info
->index_size
;
1523 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1525 if (!info
->has_user_indices
) {
1526 /* Only resources can be directly mapped */
1527 panfrost_job_add_bo(batch
, rsrc
->bo
);
1528 return rsrc
->bo
->gpu
+ offset
;
1530 /* Otherwise, we need to upload to transient memory */
1531 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1532 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1537 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1539 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1541 /* Check if we're scissoring at all */
1543 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1546 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1549 /* Count generated primitives (when there is no geom/tess shaders) for
1550 * transform feedback */
1553 panfrost_statistics_record(
1554 struct panfrost_context
*ctx
,
1555 const struct pipe_draw_info
*info
)
1557 if (!ctx
->active_queries
)
1560 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1561 ctx
->prims_generated
+= prims
;
1563 if (ctx
->streamout
.num_targets
<= 0)
1566 ctx
->tf_prims_generated
+= prims
;
1571 struct pipe_context
*pipe
,
1572 const struct pipe_draw_info
*info
)
1574 struct panfrost_context
*ctx
= pan_context(pipe
);
1576 /* First of all, check the scissor to see if anything is drawn at all.
1577 * If it's not, we drop the draw (mostly a conformance issue;
1578 * well-behaved apps shouldn't hit this) */
1580 if (panfrost_scissor_culls_everything(ctx
))
1583 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1584 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1586 int mode
= info
->mode
;
1588 /* Fallback unsupported restart index */
1589 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1591 if (info
->primitive_restart
&& info
->index_size
1592 && info
->restart_index
!= primitive_index
) {
1593 util_draw_vbo_without_prim_restart(pipe
, info
);
1597 /* Fallback for unsupported modes */
1599 assert(ctx
->rasterizer
!= NULL
);
1601 if (!(ctx
->draw_modes
& (1 << mode
))) {
1602 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1603 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1605 if (info
->count
< 4) {
1606 /* Degenerate case? */
1610 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1611 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1616 /* Now that we have a guaranteed terminating path, find the job.
1617 * Assignment commented out to prevent unused warning */
1619 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1621 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1623 /* Take into account a negative bias */
1624 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1625 ctx
->instance_count
= info
->instance_count
;
1626 ctx
->active_prim
= info
->mode
;
1628 /* For non-indexed draws, they're the same */
1629 unsigned vertex_count
= ctx
->vertex_count
;
1631 unsigned draw_flags
= 0;
1633 /* The draw flags interpret how primitive size is interpreted */
1635 if (panfrost_writes_point_size(ctx
))
1636 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1638 if (info
->primitive_restart
)
1639 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1641 /* For higher amounts of vertices (greater than what fits in a 16-bit
1642 * short), the other value is needed, otherwise there will be bizarre
1643 * rendering artefacts. It's not clear what these values mean yet. This
1644 * change is also needed for instancing and sometimes points (perhaps
1645 * related to dynamically setting gl_PointSize) */
1647 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1648 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1649 bool instanced
= ctx
->instance_count
> 1;
1651 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1653 /* This doesn't make much sense */
1654 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1655 draw_flags
|= 0x800;
1658 panfrost_statistics_record(ctx
, info
);
1660 if (info
->index_size
) {
1661 /* Calculate the min/max index used so we can figure out how
1662 * many times to invoke the vertex shader */
1664 /* Fetch / calculate index bounds */
1665 unsigned min_index
= 0, max_index
= 0;
1667 if (info
->max_index
== ~0u) {
1668 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1670 min_index
= info
->min_index
;
1671 max_index
= info
->max_index
;
1674 /* Use the corresponding values */
1675 vertex_count
= max_index
- min_index
+ 1;
1676 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1677 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1679 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1680 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1682 //assert(!info->restart_index); /* TODO: Research */
1684 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1685 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1687 /* Index count == vertex count, if no indexing is applied, as
1688 * if it is internally indexed in the expected order */
1690 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1691 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1693 /* Reverse index state */
1694 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1697 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1698 * vertex_count, 1) */
1700 panfrost_pack_work_groups_fused(
1701 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1702 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1703 1, vertex_count
, info
->instance_count
,
1706 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1708 /* Encode the padded vertex count */
1710 if (info
->instance_count
> 1) {
1711 /* Triangles have non-even vertex counts so they change how
1712 * padding works internally */
1715 mode
== PIPE_PRIM_TRIANGLES
||
1716 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1717 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1719 struct pan_shift_odd so
=
1720 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1722 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= so
.shift
;
1723 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= so
.shift
;
1725 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= so
.odd
;
1726 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= so
.odd
;
1728 ctx
->padded_count
= pan_expand_shift_odd(so
);
1730 ctx
->padded_count
= ctx
->vertex_count
;
1732 /* Reset instancing state */
1733 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1734 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1735 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1736 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1739 /* Fire off the draw itself */
1740 panfrost_queue_draw(ctx
);
1742 /* Increment transform feedback offsets */
1744 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1745 unsigned output_count
= u_stream_outputs_for_vertices(
1746 ctx
->active_prim
, ctx
->vertex_count
);
1748 ctx
->streamout
.offsets
[i
] += output_count
;
1755 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1761 panfrost_create_rasterizer_state(
1762 struct pipe_context
*pctx
,
1763 const struct pipe_rasterizer_state
*cso
)
1765 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1769 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1770 so
->tiler_gl_enables
= 0x7;
1773 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1775 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1776 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1778 if (cso
->cull_face
& PIPE_FACE_BACK
)
1779 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1785 panfrost_bind_rasterizer_state(
1786 struct pipe_context
*pctx
,
1789 struct panfrost_context
*ctx
= pan_context(pctx
);
1791 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1795 ctx
->rasterizer
= hwcso
;
1796 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1798 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1799 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1801 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1802 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1804 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1806 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1807 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1809 /* Point sprites are emulated */
1811 struct panfrost_shader_state
*variant
=
1812 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1814 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1815 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1819 panfrost_create_vertex_elements_state(
1820 struct pipe_context
*pctx
,
1821 unsigned num_elements
,
1822 const struct pipe_vertex_element
*elements
)
1824 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1826 so
->num_elements
= num_elements
;
1827 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1829 for (int i
= 0; i
< num_elements
; ++i
) {
1830 so
->hw
[i
].index
= i
;
1832 enum pipe_format fmt
= elements
[i
].src_format
;
1833 const struct util_format_description
*desc
= util_format_description(fmt
);
1834 so
->hw
[i
].unknown1
= 0x2;
1835 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1837 so
->hw
[i
].format
= panfrost_find_format(desc
);
1839 /* The field itself should probably be shifted over */
1840 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1847 panfrost_bind_vertex_elements_state(
1848 struct pipe_context
*pctx
,
1851 struct panfrost_context
*ctx
= pan_context(pctx
);
1853 ctx
->vertex
= hwcso
;
1854 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1858 panfrost_create_shader_state(
1859 struct pipe_context
*pctx
,
1860 const struct pipe_shader_state
*cso
)
1862 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1865 /* Token deep copy to prevent memory corruption */
1867 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1868 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1874 panfrost_delete_shader_state(
1875 struct pipe_context
*pctx
,
1878 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1880 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1881 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1884 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1885 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1886 panfrost_bo_unreference(pctx
->screen
, shader_state
->bo
);
1887 shader_state
->bo
= NULL
;
1894 panfrost_create_sampler_state(
1895 struct pipe_context
*pctx
,
1896 const struct pipe_sampler_state
*cso
)
1898 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1901 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1903 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1904 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1905 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1907 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1908 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1909 unsigned mip_filter
= mip_linear
?
1910 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1911 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1913 struct mali_sampler_descriptor sampler_descriptor
= {
1914 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1915 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1916 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1917 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1918 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1920 cso
->border_color
.f
[0],
1921 cso
->border_color
.f
[1],
1922 cso
->border_color
.f
[2],
1923 cso
->border_color
.f
[3]
1925 .min_lod
= FIXED_16(cso
->min_lod
),
1926 .max_lod
= FIXED_16(cso
->max_lod
),
1927 .seamless_cube_map
= cso
->seamless_cube_map
,
1930 /* If necessary, we disable mipmapping in the sampler descriptor by
1931 * clamping the LOD as tight as possible (from 0 to epsilon,
1932 * essentially -- remember these are fixed point numbers, so
1935 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1936 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1938 /* Enforce that there is something in the middle by adding epsilon*/
1940 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1941 sampler_descriptor
.max_lod
++;
1944 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1946 so
->hw
= sampler_descriptor
;
1952 panfrost_bind_sampler_states(
1953 struct pipe_context
*pctx
,
1954 enum pipe_shader_type shader
,
1955 unsigned start_slot
, unsigned num_sampler
,
1958 assert(start_slot
== 0);
1960 struct panfrost_context
*ctx
= pan_context(pctx
);
1962 /* XXX: Should upload, not just copy? */
1963 ctx
->sampler_count
[shader
] = num_sampler
;
1964 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1966 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1970 panfrost_variant_matches(
1971 struct panfrost_context
*ctx
,
1972 struct panfrost_shader_state
*variant
,
1973 enum pipe_shader_type type
)
1975 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1976 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1978 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1980 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1981 /* Make sure enable state is at least the same */
1982 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1986 /* Check that the contents of the test are the same */
1987 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1988 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1990 if (!(same_func
&& same_ref
)) {
1995 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1996 variant
->point_sprite_mask
)) {
1997 /* Ensure the same varyings are turned to point sprites */
1998 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
2001 /* Ensure the orientation is correct */
2003 rasterizer
->sprite_coord_mode
==
2004 PIPE_SPRITE_COORD_UPPER_LEFT
;
2006 if (variant
->point_sprite_upper_left
!= upper_left
)
2010 /* Otherwise, we're good to go */
2015 * Fix an uncompiled shader's stream output info, and produce a bitmask
2016 * of which VARYING_SLOT_* are captured for stream output.
2018 * Core Gallium stores output->register_index as a "slot" number, where
2019 * slots are assigned consecutively to all outputs in info->outputs_written.
2020 * This naive packing of outputs doesn't work for us - we too have slots,
2021 * but the layout is defined by the VUE map, which we won't have until we
2022 * compile a specific shader variant. So, we remap these and simply store
2023 * VARYING_SLOT_* in our copy's output->register_index fields.
2025 * We then produce a bitmask of outputs which are used for SO.
2027 * Implementation from iris.
2031 update_so_info(struct pipe_stream_output_info
*so_info
,
2032 uint64_t outputs_written
)
2034 uint64_t so_outputs
= 0;
2035 uint8_t reverse_map
[64] = {};
2038 while (outputs_written
)
2039 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
2041 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
2042 struct pipe_stream_output
*output
= &so_info
->output
[i
];
2044 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
2045 output
->register_index
= reverse_map
[output
->register_index
];
2047 so_outputs
|= 1ull << output
->register_index
;
2054 panfrost_bind_shader_state(
2055 struct pipe_context
*pctx
,
2057 enum pipe_shader_type type
)
2059 struct panfrost_context
*ctx
= pan_context(pctx
);
2061 ctx
->shader
[type
] = hwcso
;
2063 if (type
== PIPE_SHADER_FRAGMENT
)
2064 ctx
->dirty
|= PAN_DIRTY_FS
;
2066 ctx
->dirty
|= PAN_DIRTY_VS
;
2070 /* Match the appropriate variant */
2072 signed variant
= -1;
2073 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2075 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2076 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
2082 if (variant
== -1) {
2083 /* No variant matched, so create a new one */
2084 variant
= variants
->variant_count
++;
2085 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2087 struct panfrost_shader_state
*v
=
2088 &variants
->variants
[variant
];
2090 if (type
== PIPE_SHADER_FRAGMENT
) {
2091 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
2093 if (ctx
->rasterizer
) {
2094 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
2095 v
->point_sprite_upper_left
=
2096 ctx
->rasterizer
->base
.sprite_coord_mode
==
2097 PIPE_SPRITE_COORD_UPPER_LEFT
;
2101 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
2105 /* Select this variant */
2106 variants
->active_variant
= variant
;
2108 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2109 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2111 /* We finally have a variant, so compile it */
2113 if (!shader_state
->compiled
) {
2114 uint64_t outputs_written
= 0;
2116 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
2117 variants
->base
.type
,
2118 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
2119 variants
->base
.ir
.nir
:
2120 variants
->base
.tokens
,
2121 tgsi_processor_to_shader_stage(type
), shader_state
,
2124 shader_state
->compiled
= true;
2126 /* Fixup the stream out information, since what Gallium returns
2127 * normally is mildly insane */
2129 shader_state
->stream_output
= variants
->base
.stream_output
;
2130 shader_state
->so_mask
=
2131 update_so_info(&shader_state
->stream_output
, outputs_written
);
2136 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2138 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2142 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2144 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2148 panfrost_set_vertex_buffers(
2149 struct pipe_context
*pctx
,
2150 unsigned start_slot
,
2151 unsigned num_buffers
,
2152 const struct pipe_vertex_buffer
*buffers
)
2154 struct panfrost_context
*ctx
= pan_context(pctx
);
2156 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2160 panfrost_set_constant_buffer(
2161 struct pipe_context
*pctx
,
2162 enum pipe_shader_type shader
, uint index
,
2163 const struct pipe_constant_buffer
*buf
)
2165 struct panfrost_context
*ctx
= pan_context(pctx
);
2166 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2168 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2170 unsigned mask
= (1 << index
);
2172 if (unlikely(!buf
)) {
2173 pbuf
->enabled_mask
&= ~mask
;
2174 pbuf
->dirty_mask
&= ~mask
;
2178 pbuf
->enabled_mask
|= mask
;
2179 pbuf
->dirty_mask
|= mask
;
2183 panfrost_set_stencil_ref(
2184 struct pipe_context
*pctx
,
2185 const struct pipe_stencil_ref
*ref
)
2187 struct panfrost_context
*ctx
= pan_context(pctx
);
2188 ctx
->stencil_ref
= *ref
;
2190 /* Shader core dirty */
2191 ctx
->dirty
|= PAN_DIRTY_FS
;
2194 static enum mali_texture_type
2195 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2199 case PIPE_TEXTURE_1D
:
2200 case PIPE_TEXTURE_1D_ARRAY
:
2203 case PIPE_TEXTURE_2D
:
2204 case PIPE_TEXTURE_2D_ARRAY
:
2205 case PIPE_TEXTURE_RECT
:
2208 case PIPE_TEXTURE_3D
:
2211 case PIPE_TEXTURE_CUBE
:
2212 case PIPE_TEXTURE_CUBE_ARRAY
:
2213 return MALI_TEX_CUBE
;
2216 unreachable("Unknown target");
2220 static struct pipe_sampler_view
*
2221 panfrost_create_sampler_view(
2222 struct pipe_context
*pctx
,
2223 struct pipe_resource
*texture
,
2224 const struct pipe_sampler_view
*template)
2226 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2227 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2229 pipe_reference(NULL
, &texture
->reference
);
2231 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2234 so
->base
= *template;
2235 so
->base
.texture
= texture
;
2236 so
->base
.reference
.count
= 1;
2237 so
->base
.context
= pctx
;
2239 /* sampler_views correspond to texture descriptors, minus the texture
2240 * (data) itself. So, we serialise the descriptor here and cache it for
2243 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2245 unsigned char user_swizzle
[4] = {
2246 template->swizzle_r
,
2247 template->swizzle_g
,
2248 template->swizzle_b
,
2252 enum mali_format format
= panfrost_find_format(desc
);
2254 /* Check if we need to set a custom stride by computing the "expected"
2255 * stride and comparing it to what the BO actually wants. Only applies
2256 * to linear textures, since tiled/compressed textures have strict
2257 * alignment requirements for their strides as it is */
2259 unsigned first_level
= template->u
.tex
.first_level
;
2260 unsigned last_level
= template->u
.tex
.last_level
;
2262 if (prsrc
->layout
== PAN_LINEAR
) {
2263 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2264 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2265 unsigned width
= u_minify(texture
->width0
, l
);
2266 unsigned comp_stride
= width
* bytes_per_pixel
;
2268 if (comp_stride
!= actual_stride
) {
2269 so
->manual_stride
= true;
2275 /* In the hardware, array_size refers specifically to array textures,
2276 * whereas in Gallium, it also covers cubemaps */
2278 unsigned array_size
= texture
->array_size
;
2280 if (template->target
== PIPE_TEXTURE_CUBE
) {
2281 /* TODO: Cubemap arrays */
2282 assert(array_size
== 6);
2286 struct mali_texture_descriptor texture_descriptor
= {
2287 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2288 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2289 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2290 .array_size
= MALI_POSITIVE(array_size
),
2293 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2295 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2296 .type
= panfrost_translate_texture_type(template->target
),
2300 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2303 texture_descriptor
.levels
= last_level
- first_level
;
2305 so
->hw
= texture_descriptor
;
2307 return (struct pipe_sampler_view
*) so
;
2311 panfrost_set_sampler_views(
2312 struct pipe_context
*pctx
,
2313 enum pipe_shader_type shader
,
2314 unsigned start_slot
, unsigned num_views
,
2315 struct pipe_sampler_view
**views
)
2317 struct panfrost_context
*ctx
= pan_context(pctx
);
2319 assert(start_slot
== 0);
2321 unsigned new_nr
= 0;
2322 for (unsigned i
= 0; i
< num_views
; ++i
) {
2327 ctx
->sampler_view_count
[shader
] = new_nr
;
2328 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2330 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2334 panfrost_sampler_view_destroy(
2335 struct pipe_context
*pctx
,
2336 struct pipe_sampler_view
*view
)
2338 pipe_resource_reference(&view
->texture
, NULL
);
2343 panfrost_set_shader_buffers(
2344 struct pipe_context
*pctx
,
2345 enum pipe_shader_type shader
,
2346 unsigned start
, unsigned count
,
2347 const struct pipe_shader_buffer
*buffers
,
2348 unsigned writable_bitmask
)
2350 struct panfrost_context
*ctx
= pan_context(pctx
);
2352 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2353 buffers
, start
, count
);
2356 /* Hints that a framebuffer should use AFBC where possible */
2360 struct panfrost_screen
*screen
,
2361 const struct pipe_framebuffer_state
*fb
)
2363 /* AFBC implemenation incomplete; hide it */
2364 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2366 /* Hint AFBC to the resources bound to each color buffer */
2368 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2369 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2370 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2371 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2374 /* Also hint it to the depth buffer */
2377 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2378 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2383 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2384 const struct pipe_framebuffer_state
*fb
)
2386 struct panfrost_context
*ctx
= pan_context(pctx
);
2388 /* Flush when switching framebuffers, but not if the framebuffer
2389 * state is being restored by u_blitter
2392 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
2393 bool is_scanout
= panfrost_is_scanout(ctx
);
2394 bool has_draws
= job
->last_job
.gpu
;
2396 /* Bail out early when the current and new states are the same. */
2397 if (util_framebuffer_state_equal(&ctx
->pipe_framebuffer
, fb
))
2400 /* The wallpaper logic sets a new FB state before doing the blit and
2401 * restore the old one when it's done. Those FB states are reported to
2402 * be different because the surface they are pointing to are different,
2403 * but those surfaces actually point to the same cbufs/zbufs. In that
2404 * case we definitely don't want new FB descs to be emitted/attached
2405 * since the job is expected to be flushed just after the blit is done,
2406 * so let's just copy the new state and return here.
2408 if (ctx
->wallpaper_batch
) {
2409 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2413 if (!is_scanout
|| has_draws
)
2414 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2416 assert(!ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
&&
2417 !ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
2419 /* Invalidate the FBO job cache since we've just been assigned a new
2424 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2426 /* Given that we're rendering, we'd love to have compression */
2427 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
2429 panfrost_hint_afbc(screen
, &ctx
->pipe_framebuffer
);
2430 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
2431 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
2435 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2436 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2438 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2442 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2445 struct panfrost_context
*ctx
= pan_context(pipe
);
2446 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2447 ctx
->depth_stencil
= depth_stencil
;
2452 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2453 * emulated in the fragment shader */
2455 if (depth_stencil
->alpha
.enabled
) {
2456 /* We need to trigger a new shader (maybe) */
2457 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2461 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2463 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2464 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2466 /* If back-stencil is not enabled, use the front values */
2467 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2468 unsigned back_index
= back_enab
? 1 : 0;
2470 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2471 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2473 /* Depth state (TODO: Refactor) */
2474 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2476 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2478 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2479 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2481 /* Bounds test not implemented */
2482 assert(!depth_stencil
->depth
.bounds_test
);
2484 ctx
->dirty
|= PAN_DIRTY_FS
;
2488 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2494 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2495 unsigned sample_mask
)
2500 panfrost_set_clip_state(struct pipe_context
*pipe
,
2501 const struct pipe_clip_state
*clip
)
2503 //struct panfrost_context *panfrost = pan_context(pipe);
2507 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2508 unsigned start_slot
,
2509 unsigned num_viewports
,
2510 const struct pipe_viewport_state
*viewports
)
2512 struct panfrost_context
*ctx
= pan_context(pipe
);
2514 assert(start_slot
== 0);
2515 assert(num_viewports
== 1);
2517 ctx
->pipe_viewport
= *viewports
;
2521 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2522 unsigned start_slot
,
2523 unsigned num_scissors
,
2524 const struct pipe_scissor_state
*scissors
)
2526 struct panfrost_context
*ctx
= pan_context(pipe
);
2528 assert(start_slot
== 0);
2529 assert(num_scissors
== 1);
2531 ctx
->scissor
= *scissors
;
2535 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2536 const struct pipe_poly_stipple
*stipple
)
2538 //struct panfrost_context *panfrost = pan_context(pipe);
2542 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2545 struct panfrost_context
*ctx
= pan_context(pipe
);
2546 ctx
->active_queries
= enable
;
2550 panfrost_destroy(struct pipe_context
*pipe
)
2552 struct panfrost_context
*panfrost
= pan_context(pipe
);
2553 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2555 if (panfrost
->blitter
)
2556 util_blitter_destroy(panfrost
->blitter
);
2558 if (panfrost
->blitter_wallpaper
)
2559 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2561 panfrost_drm_free_slab(screen
, &panfrost
->scratchpad
);
2562 panfrost_drm_free_slab(screen
, &panfrost
->tiler_heap
);
2563 panfrost_drm_free_slab(screen
, &panfrost
->tiler_dummy
);
2568 static struct pipe_query
*
2569 panfrost_create_query(struct pipe_context
*pipe
,
2573 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2578 return (struct pipe_query
*) q
;
2582 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2588 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2590 struct panfrost_context
*ctx
= pan_context(pipe
);
2591 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2593 switch (query
->type
) {
2594 case PIPE_QUERY_OCCLUSION_COUNTER
:
2595 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2596 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2597 /* Allocate a word for the query results to be stored */
2598 query
->transfer
= panfrost_allocate_transient(ctx
, sizeof(unsigned));
2599 ctx
->occlusion_query
= query
;
2602 /* Geometry statistics are computed in the driver. XXX: geom/tess
2605 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2606 query
->start
= ctx
->prims_generated
;
2608 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2609 query
->start
= ctx
->tf_prims_generated
;
2613 fprintf(stderr
, "Skipping query %d\n", query
->type
);
2621 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2623 struct panfrost_context
*ctx
= pan_context(pipe
);
2624 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2626 switch (query
->type
) {
2627 case PIPE_QUERY_OCCLUSION_COUNTER
:
2628 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2629 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2630 ctx
->occlusion_query
= NULL
;
2632 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2633 query
->end
= ctx
->prims_generated
;
2635 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2636 query
->end
= ctx
->tf_prims_generated
;
2644 panfrost_get_query_result(struct pipe_context
*pipe
,
2645 struct pipe_query
*q
,
2647 union pipe_query_result
*vresult
)
2649 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2652 switch (query
->type
) {
2653 case PIPE_QUERY_OCCLUSION_COUNTER
:
2654 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2655 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2657 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2659 /* Read back the query results */
2660 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2661 unsigned passed
= *result
;
2663 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2664 vresult
->u64
= passed
;
2666 vresult
->b
= !!passed
;
2671 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2672 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2673 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2674 vresult
->u64
= query
->end
- query
->start
;
2678 DBG("Skipped query get %d\n", query
->type
);
2685 static struct pipe_stream_output_target
*
2686 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2687 struct pipe_resource
*prsc
,
2688 unsigned buffer_offset
,
2689 unsigned buffer_size
)
2691 struct pipe_stream_output_target
*target
;
2693 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2698 pipe_reference_init(&target
->reference
, 1);
2699 pipe_resource_reference(&target
->buffer
, prsc
);
2701 target
->context
= pctx
;
2702 target
->buffer_offset
= buffer_offset
;
2703 target
->buffer_size
= buffer_size
;
2709 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2710 struct pipe_stream_output_target
*target
)
2712 pipe_resource_reference(&target
->buffer
, NULL
);
2713 ralloc_free(target
);
2717 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2718 unsigned num_targets
,
2719 struct pipe_stream_output_target
**targets
,
2720 const unsigned *offsets
)
2722 struct panfrost_context
*ctx
= pan_context(pctx
);
2723 struct panfrost_streamout
*so
= &ctx
->streamout
;
2725 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2727 for (unsigned i
= 0; i
< num_targets
; i
++) {
2728 if (offsets
[i
] != -1)
2729 so
->offsets
[i
] = offsets
[i
];
2731 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2734 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2735 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2737 so
->num_targets
= num_targets
;
2741 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2743 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2744 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2746 panfrost_drm_allocate_slab(screen
, &ctx
->scratchpad
, 64*4, false, 0, 0, 0);
2747 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_heap
, 4096, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2748 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_dummy
, 1, false, PAN_ALLOCATE_INVISIBLE
, 0, 0);
2751 /* New context creation, which also does hardware initialisation since I don't
2752 * know the better way to structure this :smirk: */
2754 struct pipe_context
*
2755 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2757 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2758 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2759 memset(ctx
, 0, sizeof(*ctx
));
2760 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2762 ctx
->is_t6xx
= pscreen
->gpu_id
< 0x0700; /* Literally, "earlier than T700" */
2764 gallium
->screen
= screen
;
2766 gallium
->destroy
= panfrost_destroy
;
2768 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2770 gallium
->flush
= panfrost_flush
;
2771 gallium
->clear
= panfrost_clear
;
2772 gallium
->draw_vbo
= panfrost_draw_vbo
;
2774 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2775 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2776 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2778 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2780 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2781 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2782 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2784 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2785 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2786 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2788 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2789 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2790 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2792 gallium
->create_fs_state
= panfrost_create_shader_state
;
2793 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2794 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2796 gallium
->create_vs_state
= panfrost_create_shader_state
;
2797 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2798 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2800 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2801 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2802 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2804 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2805 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2806 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2808 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2810 gallium
->set_clip_state
= panfrost_set_clip_state
;
2811 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2812 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2813 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2814 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2816 gallium
->create_query
= panfrost_create_query
;
2817 gallium
->destroy_query
= panfrost_destroy_query
;
2818 gallium
->begin_query
= panfrost_begin_query
;
2819 gallium
->end_query
= panfrost_end_query
;
2820 gallium
->get_query_result
= panfrost_get_query_result
;
2822 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2823 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2824 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2826 panfrost_resource_context_init(gallium
);
2827 panfrost_blend_context_init(gallium
);
2828 panfrost_compute_context_init(gallium
);
2830 panfrost_drm_init_context(ctx
);
2832 panfrost_setup_hardware(ctx
);
2835 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2836 gallium
->const_uploader
= gallium
->stream_uploader
;
2837 assert(gallium
->stream_uploader
);
2839 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2840 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2842 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2844 ctx
->blitter
= util_blitter_create(gallium
);
2845 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2847 assert(ctx
->blitter
);
2848 assert(ctx
->blitter_wallpaper
);
2850 /* Prepare for render! */
2852 panfrost_job_init(ctx
);
2853 panfrost_emit_vertex_payload(ctx
);
2854 panfrost_emit_tiler_payload(ctx
);
2855 panfrost_invalidate_frame(ctx
);
2856 panfrost_default_shader_backend(ctx
);