2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_format.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
55 #include "pandecode/decode.h"
57 struct midgard_tiler_descriptor
58 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
60 struct panfrost_screen
*screen
= pan_screen(batch
->ctx
->base
.screen
);
61 bool hierarchy
= !(screen
->quirks
& MIDGARD_NO_HIER_TILING
);
62 struct midgard_tiler_descriptor t
= {0};
63 unsigned height
= batch
->key
.height
;
64 unsigned width
= batch
->key
.width
;
67 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
69 /* Compute the polygon header size and use that to offset the body */
71 unsigned header_size
= panfrost_tiler_header_size(
72 width
, height
, t
.hierarchy_mask
, hierarchy
);
74 t
.polygon_list_size
= panfrost_tiler_full_size(
75 width
, height
, t
.hierarchy_mask
, hierarchy
);
80 struct panfrost_bo
*tiler_heap
;
82 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
83 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
88 /* Allow the entire tiler heap */
89 t
.heap_start
= tiler_heap
->gpu
;
90 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
92 struct panfrost_bo
*tiler_dummy
;
94 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
95 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
97 /* The tiler is disabled, so don't allow the tiler heap */
98 t
.heap_start
= tiler_dummy
->gpu
;
99 t
.heap_end
= t
.heap_start
;
101 /* Use a dummy polygon list */
102 t
.polygon_list
= tiler_dummy
->gpu
;
104 /* Disable the tiler */
106 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
108 t
.hierarchy_mask
= MALI_TILER_USER
;
109 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
111 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
112 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
113 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
117 t
.polygon_list_body
=
118 t
.polygon_list
+ header_size
;
125 struct pipe_context
*pipe
,
127 const union pipe_color_union
*color
,
128 double depth
, unsigned stencil
)
130 struct panfrost_context
*ctx
= pan_context(pipe
);
132 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
133 * the existing batch targeting this FBO has draws. We could probably
134 * avoid that by replacing plain clears by quad-draws with a specific
135 * color/depth/stencil value, thus avoiding the generation of extra
138 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
140 panfrost_batch_add_fbo_bos(batch
);
141 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
145 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
147 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
148 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
150 /* If we haven't, reserve space for the framebuffer */
152 if (!batch
->framebuffer
.gpu
) {
153 unsigned size
= (screen
->quirks
& MIDGARD_SFBD
) ?
154 sizeof(struct mali_single_framebuffer
) :
155 sizeof(struct bifrost_framebuffer
);
157 batch
->framebuffer
= panfrost_allocate_transient(batch
, size
);
159 /* Tag the pointer */
160 if (!(screen
->quirks
& MIDGARD_SFBD
))
161 batch
->framebuffer
.gpu
|= MALI_MFBD
;
164 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
165 ctx
->payloads
[i
].postfix
.framebuffer
= batch
->framebuffer
.gpu
;
168 /* Reset per-frame context, called on context initialisation as well as after
169 * flushing a frame */
172 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
174 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
175 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
178 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
181 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
183 /* TODO: When does this need to be handled? */
184 ctx
->active_queries
= true;
187 /* In practice, every field of these payloads should be configurable
188 * arbitrarily, which means these functions are basically catch-all's for
189 * as-of-yet unwavering unknowns */
192 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
194 /* 0x2 bit clear on 32-bit T6XX */
196 struct midgard_payload_vertex_tiler payload
= {
197 .gl_enables
= 0x4 | 0x2,
200 /* Vertex and compute are closely coupled, so share a payload */
202 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
203 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
207 translate_tex_wrap(enum pipe_tex_wrap w
)
210 case PIPE_TEX_WRAP_REPEAT
:
211 return MALI_WRAP_REPEAT
;
213 case PIPE_TEX_WRAP_CLAMP
:
214 return MALI_WRAP_CLAMP
;
216 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
217 return MALI_WRAP_CLAMP_TO_EDGE
;
219 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
220 return MALI_WRAP_CLAMP_TO_BORDER
;
222 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
223 return MALI_WRAP_MIRRORED_REPEAT
;
225 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
226 return MALI_WRAP_MIRRORED_CLAMP
;
228 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
229 return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE
;
231 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
232 return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER
;
235 unreachable("Invalid wrap");
240 panfrost_translate_compare_func(enum pipe_compare_func in
)
243 case PIPE_FUNC_NEVER
:
244 return MALI_FUNC_NEVER
;
247 return MALI_FUNC_LESS
;
249 case PIPE_FUNC_EQUAL
:
250 return MALI_FUNC_EQUAL
;
252 case PIPE_FUNC_LEQUAL
:
253 return MALI_FUNC_LEQUAL
;
255 case PIPE_FUNC_GREATER
:
256 return MALI_FUNC_GREATER
;
258 case PIPE_FUNC_NOTEQUAL
:
259 return MALI_FUNC_NOTEQUAL
;
261 case PIPE_FUNC_GEQUAL
:
262 return MALI_FUNC_GEQUAL
;
264 case PIPE_FUNC_ALWAYS
:
265 return MALI_FUNC_ALWAYS
;
268 unreachable("Invalid func");
273 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
276 case PIPE_STENCIL_OP_KEEP
:
277 return MALI_STENCIL_KEEP
;
279 case PIPE_STENCIL_OP_ZERO
:
280 return MALI_STENCIL_ZERO
;
282 case PIPE_STENCIL_OP_REPLACE
:
283 return MALI_STENCIL_REPLACE
;
285 case PIPE_STENCIL_OP_INCR
:
286 return MALI_STENCIL_INCR
;
288 case PIPE_STENCIL_OP_DECR
:
289 return MALI_STENCIL_DECR
;
291 case PIPE_STENCIL_OP_INCR_WRAP
:
292 return MALI_STENCIL_INCR_WRAP
;
294 case PIPE_STENCIL_OP_DECR_WRAP
:
295 return MALI_STENCIL_DECR_WRAP
;
297 case PIPE_STENCIL_OP_INVERT
:
298 return MALI_STENCIL_INVERT
;
301 unreachable("Invalid stencil op");
306 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
308 out
->ref
= 0; /* Gallium gets it from elsewhere */
310 out
->mask
= in
->valuemask
;
311 out
->func
= panfrost_translate_compare_func(in
->func
);
312 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
313 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
314 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
318 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
320 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
321 struct mali_shader_meta shader
= {
322 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
324 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
325 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
328 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this is
329 * required (independent of 32-bit/64-bit descriptors), or why it's not
330 * used on later GPU revisions. Otherwise, all shader jobs fault on
331 * these earlier chips (perhaps this is a chicken bit of some kind).
332 * More investigation is needed. */
334 if (screen
->quirks
& MIDGARD_SFBD
)
335 shader
.unknown2_4
|= 0x10;
337 struct pipe_stencil_state default_stencil
= {
339 .func
= PIPE_FUNC_ALWAYS
,
340 .fail_op
= MALI_STENCIL_KEEP
,
341 .zfail_op
= MALI_STENCIL_KEEP
,
342 .zpass_op
= MALI_STENCIL_KEEP
,
347 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
348 shader
.stencil_mask_front
= default_stencil
.writemask
;
350 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
351 shader
.stencil_mask_back
= default_stencil
.writemask
;
353 if (default_stencil
.enabled
)
354 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
356 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
359 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
360 * graphics command stream. It should be called once per draw, accordding to
361 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
362 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
365 struct panfrost_transfer
366 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
368 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
369 struct mali_job_descriptor_header job
= {
370 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
371 .job_descriptor_size
= 1,
374 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
376 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sizeof(job
) + sizeof(*payload
));
377 memcpy(transfer
.cpu
, &job
, sizeof(job
));
378 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
383 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
385 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
386 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
388 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
392 panfrost_writes_point_size(struct panfrost_context
*ctx
)
394 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
395 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
397 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
400 /* Stage the attribute descriptors so we can adjust src_offset
401 * to let BOs align nicely */
404 panfrost_stage_attributes(struct panfrost_context
*ctx
)
406 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
407 struct panfrost_vertex_state
*so
= ctx
->vertex
;
409 size_t sz
= sizeof(struct mali_attr_meta
) * PAN_MAX_ATTRIBUTE
;
410 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
411 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
413 /* Copy as-is for the first pass */
414 memcpy(target
, so
->hw
, sz
);
416 /* Fixup offsets for the second pass. Recall that the hardware
417 * calculates attribute addresses as:
419 * addr = base + (stride * vtx) + src_offset;
421 * However, on Mali, base must be aligned to 64-bytes, so we
424 * base' = base & ~63 = base - (base & 63)
426 * To compensate when using base' (see emit_vertex_data), we have
427 * to adjust src_offset by the masked off piece:
429 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
430 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
431 * = base + (stride * vtx) + src_offset
437 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
439 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
440 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
441 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
442 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
444 /* Adjust by the masked off bits of the offset */
445 target
[i
].src_offset
+= (addr
& 63);
447 /* Also, somewhat obscurely per-instance data needs to be
448 * offset in response to a delayed start in an indexed draw */
450 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
451 target
[i
].src_offset
-= buf
->stride
* start
;
454 /* Let's also include vertex builtins */
456 target
[PAN_VERTEX_ID
].format
= MALI_R32UI
;
457 target
[PAN_VERTEX_ID
].swizzle
= panfrost_get_default_swizzle(1);
459 target
[PAN_INSTANCE_ID
].format
= MALI_R32UI
;
460 target
[PAN_INSTANCE_ID
].swizzle
= panfrost_get_default_swizzle(1);
462 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
466 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
468 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
469 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
471 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
474 if (ctx
->sampler_count
[t
]) {
475 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
477 struct panfrost_transfer transfer
=
478 panfrost_allocate_transient(batch
, transfer_size
);
480 struct mali_sampler_descriptor
*desc
=
481 (struct mali_sampler_descriptor
*) transfer
.cpu
;
483 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
484 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
486 upload
= transfer
.gpu
;
489 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
493 static enum mali_texture_layout
494 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
496 switch (rsrc
->layout
) {
498 return MALI_TEXTURE_AFBC
;
500 return MALI_TEXTURE_TILED
;
502 return MALI_TEXTURE_LINEAR
;
504 unreachable("Invalid texture layout");
510 struct panfrost_context
*ctx
,
511 enum pipe_shader_type st
,
512 struct panfrost_sampler_view
*view
)
517 struct pipe_sampler_view
*pview
= &view
->base
;
518 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
519 mali_ptr descriptor_gpu
;
522 /* Do we interleave an explicit stride with every element? */
524 bool has_manual_stride
= view
->manual_stride
;
526 /* For easy access */
528 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
529 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
530 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
531 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
532 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
533 unsigned first_face
= 0;
534 unsigned last_face
= 0;
535 unsigned face_mult
= 1;
537 /* Cubemaps have 6 faces as layers in between each actual layer.
538 * There's a bit of an impedence mismatch between Gallium and the
539 * hardware, let's fixup for it */
541 if (pview
->target
== PIPE_TEXTURE_CUBE
|| pview
->target
== PIPE_TEXTURE_CUBE_ARRAY
) {
542 /* TODO: logic wrong in the asserted out cases ... can they happen? */
544 first_face
= first_layer
% 6;
545 last_face
= last_layer
% 6;
549 assert((first_layer
== last_layer
) || (first_face
== 0 && last_face
== 5));
553 /* Lower-bit is set when sampling from colour AFBC */
554 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
555 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
556 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
558 /* Add the BO to the job so it's retained until the job is done. */
559 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
560 panfrost_batch_add_bo(batch
, rsrc
->bo
,
561 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
562 panfrost_bo_access_for_stage(st
));
564 /* Add the usage flags in, since they can change across the CSO
565 * lifetime due to layout switches */
567 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
568 view
->hw
.format
.manual_stride
= has_manual_stride
;
570 /* Inject the addresses in, interleaving array indices, mip levels,
571 * cube faces, and strides in that order */
574 unsigned levels
= 1 + last_level
- first_level
;
575 unsigned layers
= 1 + last_layer
- first_layer
;
576 unsigned faces
= 1 + last_face
- first_face
;
577 unsigned num_elements
= levels
* layers
* faces
;
578 if (has_manual_stride
)
581 descriptor
= malloc(sizeof(struct mali_texture_descriptor
) +
582 sizeof(mali_ptr
) * num_elements
);
583 memcpy(descriptor
, &view
->hw
, sizeof(struct mali_texture_descriptor
));
585 mali_ptr
*pointers_and_strides
= descriptor
+
586 sizeof(struct mali_texture_descriptor
);
588 for (unsigned w
= first_layer
; w
<= last_layer
; ++w
) {
589 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
590 for (unsigned f
= first_face
; f
<= last_face
; ++f
) {
591 pointers_and_strides
[idx
++] =
592 panfrost_get_texture_address(rsrc
, l
, w
* face_mult
+ f
)
593 + afbc_bit
+ view
->astc_stretch
;
594 if (has_manual_stride
) {
595 pointers_and_strides
[idx
++] =
596 rsrc
->slices
[l
].stride
;
602 descriptor_gpu
= panfrost_upload_transient(batch
, descriptor
,
603 sizeof(struct mali_texture_descriptor
) +
604 num_elements
* sizeof(*pointers_and_strides
));
607 return descriptor_gpu
;
611 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
613 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
615 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
616 mali_ptr trampoline
= 0;
618 if (ctx
->sampler_view_count
[t
]) {
619 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
621 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
623 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
625 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
628 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
632 struct sysval_uniform
{
641 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
642 struct sysval_uniform
*uniform
)
644 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
646 uniform
->f
[0] = vp
->scale
[0];
647 uniform
->f
[1] = vp
->scale
[1];
648 uniform
->f
[2] = vp
->scale
[2];
651 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
652 struct sysval_uniform
*uniform
)
654 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
656 uniform
->f
[0] = vp
->translate
[0];
657 uniform
->f
[1] = vp
->translate
[1];
658 uniform
->f
[2] = vp
->translate
[2];
661 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
662 enum pipe_shader_type st
,
663 unsigned int sysvalid
,
664 struct sysval_uniform
*uniform
)
666 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
667 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
668 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
669 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
672 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
675 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
676 tex
->u
.tex
.first_level
);
679 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
680 tex
->u
.tex
.first_level
);
683 uniform
->i
[dim
] = tex
->texture
->array_size
;
686 static void panfrost_upload_ssbo_sysval(
687 struct panfrost_context
*ctx
,
688 enum pipe_shader_type st
,
690 struct sysval_uniform
*uniform
)
692 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
693 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
695 /* Compute address */
696 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
697 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
699 panfrost_batch_add_bo(batch
, bo
,
700 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
701 panfrost_bo_access_for_stage(st
));
703 /* Upload address and size as sysval */
704 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
705 uniform
->u
[2] = sb
.buffer_size
;
709 panfrost_upload_sampler_sysval(
710 struct panfrost_context
*ctx
,
711 enum pipe_shader_type st
,
712 unsigned sampler_index
,
713 struct sysval_uniform
*uniform
)
715 struct pipe_sampler_state
*sampl
=
716 &ctx
->samplers
[st
][sampler_index
]->base
;
718 uniform
->f
[0] = sampl
->min_lod
;
719 uniform
->f
[1] = sampl
->max_lod
;
720 uniform
->f
[2] = sampl
->lod_bias
;
722 /* Even without any errata, Midgard represents "no mipmapping" as
723 * fixing the LOD with the clamps; keep behaviour consistent. c.f.
724 * panfrost_create_sampler_state which also explains our choice of
725 * epsilon value (again to keep behaviour consistent) */
727 if (sampl
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
728 uniform
->f
[1] = uniform
->f
[0] + (1.0/256.0);
731 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
732 struct sysval_uniform
*uniform
)
734 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
735 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
736 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
739 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
740 struct panfrost_shader_state
*ss
,
741 enum pipe_shader_type st
)
743 struct sysval_uniform
*uniforms
= (void *)buf
;
745 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
746 int sysval
= ss
->sysval
[i
];
748 switch (PAN_SYSVAL_TYPE(sysval
)) {
749 case PAN_SYSVAL_VIEWPORT_SCALE
:
750 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
752 case PAN_SYSVAL_VIEWPORT_OFFSET
:
753 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
755 case PAN_SYSVAL_TEXTURE_SIZE
:
756 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
759 case PAN_SYSVAL_SSBO
:
760 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
763 case PAN_SYSVAL_NUM_WORK_GROUPS
:
764 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
766 case PAN_SYSVAL_SAMPLER
:
767 panfrost_upload_sampler_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
777 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
779 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
780 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
783 return rsrc
->bo
->cpu
;
784 else if (cb
->user_buffer
)
785 return cb
->user_buffer
;
787 unreachable("No constant buffer");
791 panfrost_map_constant_buffer_gpu(
792 struct panfrost_context
*ctx
,
793 enum pipe_shader_type st
,
794 struct panfrost_constant_buffer
*buf
,
797 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
798 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
799 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
802 panfrost_batch_add_bo(batch
, rsrc
->bo
,
803 PAN_BO_ACCESS_SHARED
|
805 panfrost_bo_access_for_stage(st
));
807 /* Alignment gauranteed by PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */
808 return rsrc
->bo
->gpu
+ cb
->buffer_offset
;
809 } else if (cb
->user_buffer
) {
810 return panfrost_upload_transient(batch
, cb
->user_buffer
+ cb
->buffer_offset
, cb
->buffer_size
);
812 unreachable("No constant buffer");
816 /* Compute number of UBOs active (more specifically, compute the highest UBO
817 * number addressable -- if there are gaps, include them in the count anyway).
818 * We always include UBO #0 in the count, since we *need* uniforms enabled for
822 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
824 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
825 return 32 - __builtin_clz(mask
);
828 /* Fixes up a shader state with current state */
831 panfrost_patch_shader_state(struct panfrost_context
*ctx
,
832 enum pipe_shader_type stage
)
834 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
837 ctx
->payloads
[stage
].postfix
.shader
= 0;
841 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
843 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
844 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
846 ss
->tripipe
->midgard1
.flags_lo
= 0x220;
848 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
849 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
851 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
853 /* Add the shader BO to the batch. */
854 panfrost_batch_add_bo(batch
, ss
->bo
,
855 PAN_BO_ACCESS_PRIVATE
|
857 panfrost_bo_access_for_stage(stage
));
859 ctx
->payloads
[stage
].postfix
.shader
= panfrost_upload_transient(batch
,
861 sizeof(struct mali_shader_meta
));
864 /* Go through dirty flags and actualise them in the cmdstream. */
867 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
869 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
870 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
872 panfrost_batch_add_fbo_bos(batch
);
873 panfrost_attach_vt_framebuffer(ctx
);
875 if (with_vertex_data
) {
876 panfrost_emit_vertex_data(batch
);
878 /* Varyings emitted for -all- geometry */
879 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
880 panfrost_emit_varying_descriptor(ctx
, total_count
);
883 bool msaa
= ctx
->rasterizer
->base
.multisample
;
885 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
886 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
888 /* TODO: Sample size */
889 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
890 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
893 panfrost_batch_set_requirements(batch
);
895 if (ctx
->occlusion_query
) {
896 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
;
897 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
900 panfrost_patch_shader_state(ctx
, PIPE_SHADER_VERTEX
);
901 panfrost_patch_shader_state(ctx
, PIPE_SHADER_COMPUTE
);
903 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
904 /* Check if we need to link the gl_PointSize varying */
905 if (!panfrost_writes_point_size(ctx
)) {
906 /* If the size is constant, write it out. Otherwise,
907 * don't touch primitive_size (since we would clobber
908 * the pointer there) */
910 bool points
= ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
912 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= points
?
913 ctx
->rasterizer
->base
.point_size
:
914 ctx
->rasterizer
->base
.line_width
;
918 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
919 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
920 ctx
->dirty
|= PAN_DIRTY_FS
;
922 if (ctx
->dirty
& PAN_DIRTY_FS
) {
923 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
924 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
926 panfrost_patch_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
928 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
931 COPY(attribute_count
);
935 COPY(midgard1
.uniform_count
);
936 COPY(midgard1
.uniform_buffer_count
);
937 COPY(midgard1
.work_count
);
938 COPY(midgard1
.flags_lo
);
939 COPY(midgard1
.flags_hi
);
943 /* Get blending setup */
944 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
946 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
947 unsigned shader_offset
= 0;
948 struct panfrost_bo
*shader_bo
= NULL
;
950 for (unsigned c
= 0; c
< rt_count
; ++c
) {
951 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
, &shader_bo
, &shader_offset
);
954 /* If there is a blend shader, work registers are shared. XXX: opt */
956 for (unsigned c
= 0; c
< rt_count
; ++c
) {
957 if (blend
[c
].is_shader
)
958 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
961 /* Depending on whether it's legal to in the given shader, we
962 * try to enable early-z testing (or forward-pixel kill?) */
964 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_EARLY_Z
,
965 !variant
->can_discard
&& !variant
->writes_depth
);
967 /* Add the writes Z/S flags if needed. */
968 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
,
969 MALI_WRITES_Z
, variant
->writes_depth
);
970 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_hi
,
971 MALI_WRITES_S
, variant
->writes_stencil
);
973 /* Any time texturing is used, derivatives are implicitly
974 * calculated, so we need to enable helper invocations */
976 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_HELPER_INVOCATIONS
, variant
->helper_invocations
);
978 /* Assign the stencil refs late */
980 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
981 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
982 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
984 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
985 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
987 /* CAN_DISCARD should be set if the fragment shader possibly
988 * contains a 'discard' instruction. It is likely this is
989 * related to optimizations related to forward-pixel kill, as
990 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
991 * thing?" by Peter Harris
994 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, variant
->can_discard
);
995 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, 0x400, variant
->can_discard
);
997 /* Even on MFBD, the shader descriptor gets blend shaders. It's
998 * *also* copied to the blend_meta appended (by convention),
999 * but this is the field actually read by the hardware. (Or
1000 * maybe both are read...?). Specify the last RTi with a blend
1003 ctx
->fragment_shader_core
.blend
.shader
= 0;
1005 for (signed rt
= (rt_count
- 1); rt
>= 0; --rt
) {
1006 if (blend
[rt
].is_shader
) {
1007 ctx
->fragment_shader_core
.blend
.shader
=
1008 blend
[rt
].shader
.gpu
| blend
[rt
].shader
.first_tag
;
1013 if (screen
->quirks
& MIDGARD_SFBD
) {
1014 /* When only a single render target platform is used, the blend
1015 * information is inside the shader meta itself. We
1016 * additionally need to signal CAN_DISCARD for nontrivial blend
1017 * modes (so we're able to read back the destination buffer) */
1019 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_BLEND_SHADER
, blend
[0].is_shader
);
1021 if (!blend
[0].is_shader
) {
1022 ctx
->fragment_shader_core
.blend
.equation
=
1023 *blend
[0].equation
.equation
;
1024 ctx
->fragment_shader_core
.blend
.constant
=
1025 blend
[0].equation
.constant
;
1028 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, !blend
[0].no_blending
);
1031 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1032 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1033 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1035 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.shader
= transfer
.gpu
;
1037 if (!(screen
->quirks
& MIDGARD_SFBD
)) {
1038 /* Additional blend descriptor tacked on for jobs using MFBD */
1040 struct midgard_blend_rt rts
[4];
1042 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1043 rts
[i
].flags
= 0x200;
1046 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1047 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1048 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1050 SET_BIT(rts
[i
].flags
, MALI_BLEND_MRT_SHADER
, blend
[i
].is_shader
);
1051 SET_BIT(rts
[i
].flags
, MALI_BLEND_LOAD_TIB
, !blend
[i
].no_blending
);
1052 SET_BIT(rts
[i
].flags
, MALI_BLEND_SRGB
, is_srgb
);
1053 SET_BIT(rts
[i
].flags
, MALI_BLEND_NO_DITHER
, !ctx
->blend
->base
.dither
);
1055 if (blend
[i
].is_shader
) {
1056 rts
[i
].blend
.shader
= blend
[i
].shader
.gpu
| blend
[i
].shader
.first_tag
;
1058 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1059 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1063 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1067 /* We stage to transient, so always dirty.. */
1069 panfrost_stage_attributes(ctx
);
1071 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1072 panfrost_upload_sampler_descriptors(ctx
);
1074 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1075 panfrost_upload_texture_descriptors(ctx
);
1077 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1079 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1080 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1085 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1087 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1089 /* Uniforms are implicitly UBO #0 */
1090 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1092 /* Allocate room for the sysval and the uniforms */
1093 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1094 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1095 size_t size
= sys_size
+ uniform_size
;
1096 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1098 /* Upload sysvals requested by the shader */
1099 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1101 /* Upload uniforms */
1102 if (has_uniforms
&& uniform_size
) {
1103 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1104 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1108 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1110 struct mali_vertex_tiler_postfix
*postfix
=
1111 &ctx
->payloads
[i
].postfix
;
1113 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1116 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1117 assert(ubo_count
>= 1);
1119 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1120 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1122 /* Upload uniforms as a UBO */
1123 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1124 ubos
[0].ptr
= transfer
.gpu
>> 2;
1126 /* The rest are honest-to-goodness UBOs */
1128 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1129 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1131 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1132 bool empty
= usz
== 0;
1134 if (!enabled
|| empty
) {
1135 /* Stub out disabled UBOs to catch accesses */
1138 ubos
[ubo
].ptr
= 0xDEAD0000;
1142 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, i
, buf
, ubo
);
1144 unsigned bytes_per_field
= 16;
1145 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1146 unsigned fields
= aligned
/ bytes_per_field
;
1148 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1149 ubos
[ubo
].ptr
= gpu
>> 2;
1152 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1153 postfix
->uniforms
= transfer
.gpu
;
1154 postfix
->uniform_buffers
= ubufs
;
1156 buf
->dirty_mask
= 0;
1159 /* TODO: Upload the viewport somewhere more appropriate */
1161 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1162 * (somewhat) asymmetric ints. */
1163 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1165 struct mali_viewport view
= {
1166 /* By default, do no viewport clipping, i.e. clip to (-inf,
1167 * inf) in each direction. Clipping to the viewport in theory
1168 * should work, but in practice causes issues when we're not
1169 * explicitly trying to scissor */
1171 .clip_minx
= -INFINITY
,
1172 .clip_miny
= -INFINITY
,
1173 .clip_maxx
= INFINITY
,
1174 .clip_maxy
= INFINITY
,
1177 /* Always scissor to the viewport by default. */
1178 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1179 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1181 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1182 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1184 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1185 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1187 /* Apply the scissor test */
1189 unsigned minx
, miny
, maxx
, maxy
;
1191 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1192 minx
= MAX2(ss
->minx
, vp_minx
);
1193 miny
= MAX2(ss
->miny
, vp_miny
);
1194 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1195 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1203 /* Hardware needs the min/max to be strictly ordered, so flip if we
1204 * need to. The viewport transformation in the vertex shader will
1205 * handle the negatives if we don't */
1208 unsigned temp
= miny
;
1214 unsigned temp
= minx
;
1225 /* Clamp to the framebuffer size as a last check */
1227 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1228 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1230 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1231 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1233 /* Update the job, unless we're doing wallpapering (whose lack of
1234 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1235 * just... be faster :) */
1237 if (!ctx
->wallpaper_batch
)
1238 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1242 view
.viewport0
[0] = minx
;
1243 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1245 view
.viewport0
[1] = miny
;
1246 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1248 view
.clip_minz
= minz
;
1249 view
.clip_maxz
= maxz
;
1251 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1252 panfrost_upload_transient(batch
,
1254 sizeof(struct mali_viewport
));
1259 /* Corresponds to exactly one draw, but does not submit anything */
1262 panfrost_queue_draw(struct panfrost_context
*ctx
)
1264 /* Handle dirty flags now */
1265 panfrost_emit_for_draw(ctx
, true);
1267 /* If rasterizer discard is enable, only submit the vertex */
1269 bool rasterizer_discard
= ctx
->rasterizer
1270 && ctx
->rasterizer
->base
.rasterizer_discard
;
1272 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1273 struct panfrost_transfer tiler
;
1275 if (!rasterizer_discard
)
1276 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1278 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1280 if (rasterizer_discard
)
1281 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1282 else if (ctx
->wallpaper_batch
&& batch
->first_tiler
.gpu
)
1283 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1285 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1287 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1288 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1293 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1294 batch
->stack_size
= MAX2(batch
->stack_size
, ss
->stack_size
);
1298 /* The entire frame is in memory -- send it off to the kernel! */
1302 struct pipe_context
*pipe
,
1303 struct pipe_fence_handle
**fence
,
1306 struct panfrost_context
*ctx
= pan_context(pipe
);
1307 struct util_dynarray fences
;
1309 /* We must collect the fences before the flush is done, otherwise we'll
1310 * lose track of them.
1313 util_dynarray_init(&fences
, NULL
);
1314 hash_table_foreach(ctx
->batches
, hentry
) {
1315 struct panfrost_batch
*batch
= hentry
->data
;
1317 panfrost_batch_fence_reference(batch
->out_sync
);
1318 util_dynarray_append(&fences
,
1319 struct panfrost_batch_fence
*,
1324 /* Submit all pending jobs */
1325 panfrost_flush_all_batches(ctx
, false);
1328 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
1329 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1330 *fence
= (struct pipe_fence_handle
*)f
;
1332 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
1333 panfrost_batch_fence_unreference(*fence
);
1335 util_dynarray_fini(&fences
);
1338 if (pan_debug
& PAN_DBG_TRACE
)
1339 pandecode_next_frame();
1342 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1345 g2m_draw_mode(enum pipe_prim_type mode
)
1348 DEFINE_CASE(POINTS
);
1350 DEFINE_CASE(LINE_LOOP
);
1351 DEFINE_CASE(LINE_STRIP
);
1352 DEFINE_CASE(TRIANGLES
);
1353 DEFINE_CASE(TRIANGLE_STRIP
);
1354 DEFINE_CASE(TRIANGLE_FAN
);
1356 DEFINE_CASE(QUAD_STRIP
);
1357 DEFINE_CASE(POLYGON
);
1360 unreachable("Invalid draw mode");
1367 panfrost_translate_index_size(unsigned size
)
1371 return MALI_DRAW_INDEXED_UINT8
;
1374 return MALI_DRAW_INDEXED_UINT16
;
1377 return MALI_DRAW_INDEXED_UINT32
;
1380 unreachable("Invalid index size");
1384 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1385 * good for the duration of the draw (transient), could last longer */
1388 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1390 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1392 off_t offset
= info
->start
* info
->index_size
;
1393 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1395 if (!info
->has_user_indices
) {
1396 /* Only resources can be directly mapped */
1397 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1398 PAN_BO_ACCESS_SHARED
|
1399 PAN_BO_ACCESS_READ
|
1400 PAN_BO_ACCESS_VERTEX_TILER
);
1401 return rsrc
->bo
->gpu
+ offset
;
1403 /* Otherwise, we need to upload to transient memory */
1404 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1405 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1410 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1412 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1414 /* Check if we're scissoring at all */
1416 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1419 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1422 /* Count generated primitives (when there is no geom/tess shaders) for
1423 * transform feedback */
1426 panfrost_statistics_record(
1427 struct panfrost_context
*ctx
,
1428 const struct pipe_draw_info
*info
)
1430 if (!ctx
->active_queries
)
1433 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1434 ctx
->prims_generated
+= prims
;
1436 if (!ctx
->streamout
.num_targets
)
1439 ctx
->tf_prims_generated
+= prims
;
1444 struct pipe_context
*pipe
,
1445 const struct pipe_draw_info
*info
)
1447 struct panfrost_context
*ctx
= pan_context(pipe
);
1449 /* First of all, check the scissor to see if anything is drawn at all.
1450 * If it's not, we drop the draw (mostly a conformance issue;
1451 * well-behaved apps shouldn't hit this) */
1453 if (panfrost_scissor_culls_everything(ctx
))
1456 int mode
= info
->mode
;
1458 /* Fallback unsupported restart index */
1459 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1461 if (info
->primitive_restart
&& info
->index_size
1462 && info
->restart_index
!= primitive_index
) {
1463 util_draw_vbo_without_prim_restart(pipe
, info
);
1467 /* Fallback for unsupported modes */
1469 assert(ctx
->rasterizer
!= NULL
);
1471 if (!(ctx
->draw_modes
& (1 << mode
))) {
1472 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1473 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1475 if (info
->count
< 4) {
1476 /* Degenerate case? */
1480 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1481 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1486 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1487 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1489 /* Now that we have a guaranteed terminating path, find the job.
1490 * Assignment commented out to prevent unused warning */
1492 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1494 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1496 /* Take into account a negative bias */
1497 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1498 ctx
->instance_count
= info
->instance_count
;
1499 ctx
->active_prim
= info
->mode
;
1501 /* For non-indexed draws, they're the same */
1502 unsigned vertex_count
= ctx
->vertex_count
;
1504 unsigned draw_flags
= 0;
1506 /* The draw flags interpret how primitive size is interpreted */
1508 if (panfrost_writes_point_size(ctx
))
1509 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1511 if (info
->primitive_restart
)
1512 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1514 /* These doesn't make much sense */
1516 draw_flags
|= 0x3000;
1518 if (ctx
->rasterizer
&& ctx
->rasterizer
->base
.flatshade_first
)
1519 draw_flags
|= MALI_DRAW_FLATSHADE_FIRST
;
1521 panfrost_statistics_record(ctx
, info
);
1523 if (info
->index_size
) {
1524 /* Calculate the min/max index used so we can figure out how
1525 * many times to invoke the vertex shader */
1527 /* Fetch / calculate index bounds */
1528 unsigned min_index
= 0, max_index
= 0;
1530 if (info
->max_index
== ~0u) {
1531 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1533 min_index
= info
->min_index
;
1534 max_index
= info
->max_index
;
1537 /* Use the corresponding values */
1538 vertex_count
= max_index
- min_index
+ 1;
1539 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1540 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1542 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1543 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1545 //assert(!info->restart_index); /* TODO: Research */
1547 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1548 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1550 /* Index count == vertex count, if no indexing is applied, as
1551 * if it is internally indexed in the expected order */
1553 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1554 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1556 /* Reverse index state */
1557 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (mali_ptr
) 0;
1560 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1561 * vertex_count, 1) */
1563 panfrost_pack_work_groups_fused(
1564 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1565 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1566 1, vertex_count
, info
->instance_count
,
1569 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1571 /* Encode the padded vertex count */
1573 if (info
->instance_count
> 1) {
1574 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
1576 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
1577 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
1579 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= shift
;
1580 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= shift
;
1582 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= k
;
1583 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= k
;
1585 ctx
->padded_count
= vertex_count
;
1587 /* Reset instancing state */
1588 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1589 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1590 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1591 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1594 /* Fire off the draw itself */
1595 panfrost_queue_draw(ctx
);
1597 /* Increment transform feedback offsets */
1599 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1600 unsigned output_count
= u_stream_outputs_for_vertices(
1601 ctx
->active_prim
, ctx
->vertex_count
);
1603 ctx
->streamout
.offsets
[i
] += output_count
;
1610 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1616 panfrost_create_rasterizer_state(
1617 struct pipe_context
*pctx
,
1618 const struct pipe_rasterizer_state
*cso
)
1620 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1624 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1625 so
->tiler_gl_enables
= 0x7;
1628 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1630 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1631 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1633 if (cso
->cull_face
& PIPE_FACE_BACK
)
1634 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1640 panfrost_bind_rasterizer_state(
1641 struct pipe_context
*pctx
,
1644 struct panfrost_context
*ctx
= pan_context(pctx
);
1646 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1650 ctx
->rasterizer
= hwcso
;
1651 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1653 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
* 2.0f
;
1654 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1656 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1657 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1659 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1661 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1662 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1664 /* Point sprites are emulated */
1666 struct panfrost_shader_state
*variant
=
1667 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1669 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1670 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1674 panfrost_create_vertex_elements_state(
1675 struct pipe_context
*pctx
,
1676 unsigned num_elements
,
1677 const struct pipe_vertex_element
*elements
)
1679 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1681 so
->num_elements
= num_elements
;
1682 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1684 for (int i
= 0; i
< num_elements
; ++i
) {
1685 so
->hw
[i
].index
= i
;
1687 enum pipe_format fmt
= elements
[i
].src_format
;
1688 const struct util_format_description
*desc
= util_format_description(fmt
);
1689 so
->hw
[i
].unknown1
= 0x2;
1690 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1692 so
->hw
[i
].format
= panfrost_find_format(desc
);
1694 /* The field itself should probably be shifted over */
1695 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1702 panfrost_bind_vertex_elements_state(
1703 struct pipe_context
*pctx
,
1706 struct panfrost_context
*ctx
= pan_context(pctx
);
1708 ctx
->vertex
= hwcso
;
1709 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1713 panfrost_create_shader_state(
1714 struct pipe_context
*pctx
,
1715 const struct pipe_shader_state
*cso
,
1716 enum pipe_shader_type stage
)
1718 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1721 /* Token deep copy to prevent memory corruption */
1723 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1724 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1726 /* Precompile for shader-db if we need to */
1727 if (unlikely((pan_debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
1728 struct panfrost_context
*ctx
= pan_context(pctx
);
1730 struct mali_shader_meta meta
;
1731 struct panfrost_shader_state state
;
1732 uint64_t outputs_written
;
1734 panfrost_shader_compile(ctx
, &meta
,
1737 tgsi_processor_to_shader_stage(stage
), &state
,
1745 panfrost_delete_shader_state(
1746 struct pipe_context
*pctx
,
1749 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1751 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1752 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1755 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1756 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1757 panfrost_bo_unreference(shader_state
->bo
);
1758 shader_state
->bo
= NULL
;
1760 free(cso
->variants
);
1766 panfrost_create_sampler_state(
1767 struct pipe_context
*pctx
,
1768 const struct pipe_sampler_state
*cso
)
1770 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1773 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1775 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1776 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1777 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1779 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1780 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1781 unsigned mip_filter
= mip_linear
?
1782 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1783 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1785 struct mali_sampler_descriptor sampler_descriptor
= {
1786 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1787 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1788 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1789 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1790 .compare_func
= panfrost_flip_compare_func(
1791 panfrost_translate_compare_func(
1792 cso
->compare_func
)),
1794 cso
->border_color
.f
[0],
1795 cso
->border_color
.f
[1],
1796 cso
->border_color
.f
[2],
1797 cso
->border_color
.f
[3]
1799 .min_lod
= FIXED_16(cso
->min_lod
, false), /* clamp at 0 */
1800 .max_lod
= FIXED_16(cso
->max_lod
, false),
1801 .lod_bias
= FIXED_16(cso
->lod_bias
, true), /* can be negative */
1802 .seamless_cube_map
= cso
->seamless_cube_map
,
1805 /* If necessary, we disable mipmapping in the sampler descriptor by
1806 * clamping the LOD as tight as possible (from 0 to epsilon,
1807 * essentially -- remember these are fixed point numbers, so
1810 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
) {
1811 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1813 /* Enforce that there is something in the middle by adding epsilon*/
1815 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1816 sampler_descriptor
.max_lod
++;
1819 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1822 so
->hw
= sampler_descriptor
;
1828 panfrost_bind_sampler_states(
1829 struct pipe_context
*pctx
,
1830 enum pipe_shader_type shader
,
1831 unsigned start_slot
, unsigned num_sampler
,
1834 assert(start_slot
== 0);
1836 struct panfrost_context
*ctx
= pan_context(pctx
);
1838 /* XXX: Should upload, not just copy? */
1839 ctx
->sampler_count
[shader
] = num_sampler
;
1840 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1842 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1846 panfrost_variant_matches(
1847 struct panfrost_context
*ctx
,
1848 struct panfrost_shader_state
*variant
,
1849 enum pipe_shader_type type
)
1851 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1852 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1854 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1856 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1857 /* Make sure enable state is at least the same */
1858 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1862 /* Check that the contents of the test are the same */
1863 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1864 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1866 if (!(same_func
&& same_ref
)) {
1871 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1872 variant
->point_sprite_mask
)) {
1873 /* Ensure the same varyings are turned to point sprites */
1874 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1877 /* Ensure the orientation is correct */
1879 rasterizer
->sprite_coord_mode
==
1880 PIPE_SPRITE_COORD_UPPER_LEFT
;
1882 if (variant
->point_sprite_upper_left
!= upper_left
)
1886 /* Otherwise, we're good to go */
1891 * Fix an uncompiled shader's stream output info, and produce a bitmask
1892 * of which VARYING_SLOT_* are captured for stream output.
1894 * Core Gallium stores output->register_index as a "slot" number, where
1895 * slots are assigned consecutively to all outputs in info->outputs_written.
1896 * This naive packing of outputs doesn't work for us - we too have slots,
1897 * but the layout is defined by the VUE map, which we won't have until we
1898 * compile a specific shader variant. So, we remap these and simply store
1899 * VARYING_SLOT_* in our copy's output->register_index fields.
1901 * We then produce a bitmask of outputs which are used for SO.
1903 * Implementation from iris.
1907 update_so_info(struct pipe_stream_output_info
*so_info
,
1908 uint64_t outputs_written
)
1910 uint64_t so_outputs
= 0;
1911 uint8_t reverse_map
[64] = {0};
1914 while (outputs_written
)
1915 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1917 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1918 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1920 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1921 output
->register_index
= reverse_map
[output
->register_index
];
1923 so_outputs
|= 1ull << output
->register_index
;
1930 panfrost_bind_shader_state(
1931 struct pipe_context
*pctx
,
1933 enum pipe_shader_type type
)
1935 struct panfrost_context
*ctx
= pan_context(pctx
);
1937 ctx
->shader
[type
] = hwcso
;
1939 if (type
== PIPE_SHADER_FRAGMENT
)
1940 ctx
->dirty
|= PAN_DIRTY_FS
;
1942 ctx
->dirty
|= PAN_DIRTY_VS
;
1946 /* Match the appropriate variant */
1948 signed variant
= -1;
1949 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1951 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1952 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1958 if (variant
== -1) {
1959 /* No variant matched, so create a new one */
1960 variant
= variants
->variant_count
++;
1962 if (variants
->variant_count
> variants
->variant_space
) {
1963 unsigned old_space
= variants
->variant_space
;
1965 variants
->variant_space
*= 2;
1966 if (variants
->variant_space
== 0)
1967 variants
->variant_space
= 1;
1969 /* Arbitrary limit to stop runaway programs from
1970 * creating an unbounded number of shader variants. */
1971 assert(variants
->variant_space
< 1024);
1973 unsigned msize
= sizeof(struct panfrost_shader_state
);
1974 variants
->variants
= realloc(variants
->variants
,
1975 variants
->variant_space
* msize
);
1977 memset(&variants
->variants
[old_space
], 0,
1978 (variants
->variant_space
- old_space
) * msize
);
1981 struct panfrost_shader_state
*v
=
1982 &variants
->variants
[variant
];
1984 if (type
== PIPE_SHADER_FRAGMENT
) {
1985 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1987 if (ctx
->rasterizer
) {
1988 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1989 v
->point_sprite_upper_left
=
1990 ctx
->rasterizer
->base
.sprite_coord_mode
==
1991 PIPE_SPRITE_COORD_UPPER_LEFT
;
1995 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1999 /* Select this variant */
2000 variants
->active_variant
= variant
;
2002 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2003 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2005 /* We finally have a variant, so compile it */
2007 if (!shader_state
->compiled
) {
2008 uint64_t outputs_written
= 0;
2010 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
2011 variants
->base
.type
,
2012 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
2013 variants
->base
.ir
.nir
:
2014 variants
->base
.tokens
,
2015 tgsi_processor_to_shader_stage(type
), shader_state
,
2018 shader_state
->compiled
= true;
2020 /* Fixup the stream out information, since what Gallium returns
2021 * normally is mildly insane */
2023 shader_state
->stream_output
= variants
->base
.stream_output
;
2024 shader_state
->so_mask
=
2025 update_so_info(&shader_state
->stream_output
, outputs_written
);
2030 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
2032 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2036 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
2038 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2042 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2044 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2048 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2050 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2054 panfrost_set_vertex_buffers(
2055 struct pipe_context
*pctx
,
2056 unsigned start_slot
,
2057 unsigned num_buffers
,
2058 const struct pipe_vertex_buffer
*buffers
)
2060 struct panfrost_context
*ctx
= pan_context(pctx
);
2062 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2066 panfrost_set_constant_buffer(
2067 struct pipe_context
*pctx
,
2068 enum pipe_shader_type shader
, uint index
,
2069 const struct pipe_constant_buffer
*buf
)
2071 struct panfrost_context
*ctx
= pan_context(pctx
);
2072 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2074 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2076 unsigned mask
= (1 << index
);
2078 if (unlikely(!buf
)) {
2079 pbuf
->enabled_mask
&= ~mask
;
2080 pbuf
->dirty_mask
&= ~mask
;
2084 pbuf
->enabled_mask
|= mask
;
2085 pbuf
->dirty_mask
|= mask
;
2089 panfrost_set_stencil_ref(
2090 struct pipe_context
*pctx
,
2091 const struct pipe_stencil_ref
*ref
)
2093 struct panfrost_context
*ctx
= pan_context(pctx
);
2094 ctx
->stencil_ref
= *ref
;
2096 /* Shader core dirty */
2097 ctx
->dirty
|= PAN_DIRTY_FS
;
2100 static enum mali_texture_type
2101 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2105 case PIPE_TEXTURE_1D
:
2106 case PIPE_TEXTURE_1D_ARRAY
:
2109 case PIPE_TEXTURE_2D
:
2110 case PIPE_TEXTURE_2D_ARRAY
:
2111 case PIPE_TEXTURE_RECT
:
2114 case PIPE_TEXTURE_3D
:
2117 case PIPE_TEXTURE_CUBE
:
2118 case PIPE_TEXTURE_CUBE_ARRAY
:
2119 return MALI_TEX_CUBE
;
2122 unreachable("Unknown target");
2127 panfrost_compute_astc_stretch(
2128 const struct util_format_description
*desc
)
2130 unsigned width
= desc
->block
.width
;
2131 unsigned height
= desc
->block
.height
;
2132 assert(width
>= 4 && width
<= 12);
2133 assert(height
>= 4 && height
<= 12);
2138 return ((height
- 4) * 8) + (width
- 4);
2141 static struct pipe_sampler_view
*
2142 panfrost_create_sampler_view(
2143 struct pipe_context
*pctx
,
2144 struct pipe_resource
*texture
,
2145 const struct pipe_sampler_view
*template)
2147 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2148 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2150 pipe_reference(NULL
, &texture
->reference
);
2152 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2155 so
->base
= *template;
2156 so
->base
.texture
= texture
;
2157 so
->base
.reference
.count
= 1;
2158 so
->base
.context
= pctx
;
2160 /* sampler_views correspond to texture descriptors, minus the texture
2161 * (data) itself. So, we serialise the descriptor here and cache it for
2164 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2166 unsigned char user_swizzle
[4] = {
2167 template->swizzle_r
,
2168 template->swizzle_g
,
2169 template->swizzle_b
,
2173 enum mali_format format
= panfrost_find_format(desc
);
2175 if (format
== MALI_ASTC_HDR_SUPP
|| format
== MALI_ASTC_SRGB_SUPP
)
2176 so
->astc_stretch
= panfrost_compute_astc_stretch(desc
);
2178 /* Check if we need to set a custom stride by computing the "expected"
2179 * stride and comparing it to what the BO actually wants. Only applies
2180 * to linear textures, since tiled/compressed textures have strict
2181 * alignment requirements for their strides as it is */
2183 unsigned first_level
= template->u
.tex
.first_level
;
2184 unsigned last_level
= template->u
.tex
.last_level
;
2186 if (prsrc
->layout
== PAN_LINEAR
) {
2187 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2188 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2189 unsigned width
= u_minify(texture
->width0
, l
);
2190 unsigned comp_stride
= width
* bytes_per_pixel
;
2192 if (comp_stride
!= actual_stride
) {
2193 so
->manual_stride
= true;
2199 /* In the hardware, array_size refers specifically to array textures,
2200 * whereas in Gallium, it also covers cubemaps */
2202 unsigned array_size
= texture
->array_size
;
2204 if (template->target
== PIPE_TEXTURE_CUBE
) {
2205 /* TODO: Cubemap arrays */
2206 assert(array_size
== 6);
2210 struct mali_texture_descriptor texture_descriptor
= {
2211 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2212 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2213 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2214 .array_size
= MALI_POSITIVE(array_size
),
2217 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2219 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2220 .type
= panfrost_translate_texture_type(template->target
),
2224 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2227 texture_descriptor
.levels
= last_level
- first_level
;
2229 so
->hw
= texture_descriptor
;
2231 return (struct pipe_sampler_view
*) so
;
2235 panfrost_set_sampler_views(
2236 struct pipe_context
*pctx
,
2237 enum pipe_shader_type shader
,
2238 unsigned start_slot
, unsigned num_views
,
2239 struct pipe_sampler_view
**views
)
2241 struct panfrost_context
*ctx
= pan_context(pctx
);
2242 unsigned new_nr
= 0;
2245 assert(start_slot
== 0);
2247 for (i
= 0; i
< num_views
; ++i
) {
2250 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2254 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
2255 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2258 ctx
->sampler_view_count
[shader
] = new_nr
;
2260 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2264 panfrost_sampler_view_destroy(
2265 struct pipe_context
*pctx
,
2266 struct pipe_sampler_view
*view
)
2268 pipe_resource_reference(&view
->texture
, NULL
);
2273 panfrost_set_shader_buffers(
2274 struct pipe_context
*pctx
,
2275 enum pipe_shader_type shader
,
2276 unsigned start
, unsigned count
,
2277 const struct pipe_shader_buffer
*buffers
,
2278 unsigned writable_bitmask
)
2280 struct panfrost_context
*ctx
= pan_context(pctx
);
2282 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2283 buffers
, start
, count
);
2286 /* Hints that a framebuffer should use AFBC where possible */
2290 struct panfrost_screen
*screen
,
2291 const struct pipe_framebuffer_state
*fb
)
2293 /* AFBC implemenation incomplete; hide it */
2294 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2296 /* Hint AFBC to the resources bound to each color buffer */
2298 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2299 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2300 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2301 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2304 /* Also hint it to the depth buffer */
2307 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2308 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2313 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2314 const struct pipe_framebuffer_state
*fb
)
2316 struct panfrost_context
*ctx
= pan_context(pctx
);
2318 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
2319 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2321 panfrost_invalidate_frame(ctx
);
2325 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2326 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2328 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2332 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2335 struct panfrost_context
*ctx
= pan_context(pipe
);
2336 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2337 ctx
->depth_stencil
= depth_stencil
;
2342 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2343 * emulated in the fragment shader */
2345 if (depth_stencil
->alpha
.enabled
) {
2346 /* We need to trigger a new shader (maybe) */
2347 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2351 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2353 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2354 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2356 /* If back-stencil is not enabled, use the front values */
2357 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2358 unsigned back_index
= back_enab
? 1 : 0;
2360 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2361 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2363 /* Depth state (TODO: Refactor) */
2364 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_WRITEMASK
,
2365 depth_stencil
->depth
.writemask
);
2367 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2369 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2370 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2372 /* Bounds test not implemented */
2373 assert(!depth_stencil
->depth
.bounds_test
);
2375 ctx
->dirty
|= PAN_DIRTY_FS
;
2379 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2385 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2386 unsigned sample_mask
)
2391 panfrost_set_clip_state(struct pipe_context
*pipe
,
2392 const struct pipe_clip_state
*clip
)
2394 //struct panfrost_context *panfrost = pan_context(pipe);
2398 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2399 unsigned start_slot
,
2400 unsigned num_viewports
,
2401 const struct pipe_viewport_state
*viewports
)
2403 struct panfrost_context
*ctx
= pan_context(pipe
);
2405 assert(start_slot
== 0);
2406 assert(num_viewports
== 1);
2408 ctx
->pipe_viewport
= *viewports
;
2412 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2413 unsigned start_slot
,
2414 unsigned num_scissors
,
2415 const struct pipe_scissor_state
*scissors
)
2417 struct panfrost_context
*ctx
= pan_context(pipe
);
2419 assert(start_slot
== 0);
2420 assert(num_scissors
== 1);
2422 ctx
->scissor
= *scissors
;
2426 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2427 const struct pipe_poly_stipple
*stipple
)
2429 //struct panfrost_context *panfrost = pan_context(pipe);
2433 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2436 struct panfrost_context
*ctx
= pan_context(pipe
);
2437 ctx
->active_queries
= enable
;
2441 panfrost_destroy(struct pipe_context
*pipe
)
2443 struct panfrost_context
*panfrost
= pan_context(pipe
);
2445 if (panfrost
->blitter
)
2446 util_blitter_destroy(panfrost
->blitter
);
2448 if (panfrost
->blitter_wallpaper
)
2449 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2451 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
2452 u_upload_destroy(pipe
->stream_uploader
);
2457 static struct pipe_query
*
2458 panfrost_create_query(struct pipe_context
*pipe
,
2462 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2467 return (struct pipe_query
*) q
;
2471 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2473 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2476 panfrost_bo_unreference(query
->bo
);
2484 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2486 struct panfrost_context
*ctx
= pan_context(pipe
);
2487 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2489 switch (query
->type
) {
2490 case PIPE_QUERY_OCCLUSION_COUNTER
:
2491 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2492 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2493 /* Allocate a bo for the query results to be stored */
2495 query
->bo
= panfrost_bo_create(
2496 pan_screen(ctx
->base
.screen
),
2497 sizeof(unsigned), 0);
2500 unsigned *result
= (unsigned *)query
->bo
->cpu
;
2501 *result
= 0; /* Default to 0 if nothing at all drawn. */
2502 ctx
->occlusion_query
= query
;
2505 /* Geometry statistics are computed in the driver. XXX: geom/tess
2508 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2509 query
->start
= ctx
->prims_generated
;
2511 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2512 query
->start
= ctx
->tf_prims_generated
;
2516 DBG("Skipping query %u\n", query
->type
);
2524 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2526 struct panfrost_context
*ctx
= pan_context(pipe
);
2527 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2529 switch (query
->type
) {
2530 case PIPE_QUERY_OCCLUSION_COUNTER
:
2531 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2532 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2533 ctx
->occlusion_query
= NULL
;
2535 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2536 query
->end
= ctx
->prims_generated
;
2538 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2539 query
->end
= ctx
->tf_prims_generated
;
2547 panfrost_get_query_result(struct pipe_context
*pipe
,
2548 struct pipe_query
*q
,
2550 union pipe_query_result
*vresult
)
2552 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2553 struct panfrost_context
*ctx
= pan_context(pipe
);
2556 switch (query
->type
) {
2557 case PIPE_QUERY_OCCLUSION_COUNTER
:
2558 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2559 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2561 panfrost_flush_all_batches(ctx
, true);
2563 /* Read back the query results */
2564 unsigned *result
= (unsigned *) query
->bo
->cpu
;
2565 unsigned passed
= *result
;
2567 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2568 vresult
->u64
= passed
;
2570 vresult
->b
= !!passed
;
2575 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2576 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2577 panfrost_flush_all_batches(ctx
, true);
2578 vresult
->u64
= query
->end
- query
->start
;
2582 DBG("Skipped query get %u\n", query
->type
);
2589 static struct pipe_stream_output_target
*
2590 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2591 struct pipe_resource
*prsc
,
2592 unsigned buffer_offset
,
2593 unsigned buffer_size
)
2595 struct pipe_stream_output_target
*target
;
2597 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2602 pipe_reference_init(&target
->reference
, 1);
2603 pipe_resource_reference(&target
->buffer
, prsc
);
2605 target
->context
= pctx
;
2606 target
->buffer_offset
= buffer_offset
;
2607 target
->buffer_size
= buffer_size
;
2613 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2614 struct pipe_stream_output_target
*target
)
2616 pipe_resource_reference(&target
->buffer
, NULL
);
2617 ralloc_free(target
);
2621 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2622 unsigned num_targets
,
2623 struct pipe_stream_output_target
**targets
,
2624 const unsigned *offsets
)
2626 struct panfrost_context
*ctx
= pan_context(pctx
);
2627 struct panfrost_streamout
*so
= &ctx
->streamout
;
2629 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2631 for (unsigned i
= 0; i
< num_targets
; i
++) {
2632 if (offsets
[i
] != -1)
2633 so
->offsets
[i
] = offsets
[i
];
2635 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2638 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2639 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2641 so
->num_targets
= num_targets
;
2644 struct pipe_context
*
2645 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2647 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2648 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2650 gallium
->screen
= screen
;
2652 gallium
->destroy
= panfrost_destroy
;
2654 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2656 gallium
->flush
= panfrost_flush
;
2657 gallium
->clear
= panfrost_clear
;
2658 gallium
->draw_vbo
= panfrost_draw_vbo
;
2660 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2661 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2662 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2664 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2666 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2667 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2668 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2670 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2671 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2672 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2674 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2675 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2676 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2678 gallium
->create_fs_state
= panfrost_create_fs_state
;
2679 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2680 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2682 gallium
->create_vs_state
= panfrost_create_vs_state
;
2683 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2684 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2686 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2687 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2688 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2690 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2691 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2692 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2694 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2696 gallium
->set_clip_state
= panfrost_set_clip_state
;
2697 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2698 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2699 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2700 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2702 gallium
->create_query
= panfrost_create_query
;
2703 gallium
->destroy_query
= panfrost_destroy_query
;
2704 gallium
->begin_query
= panfrost_begin_query
;
2705 gallium
->end_query
= panfrost_end_query
;
2706 gallium
->get_query_result
= panfrost_get_query_result
;
2708 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2709 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2710 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2712 panfrost_resource_context_init(gallium
);
2713 panfrost_blend_context_init(gallium
);
2714 panfrost_compute_context_init(gallium
);
2717 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2718 gallium
->const_uploader
= gallium
->stream_uploader
;
2719 assert(gallium
->stream_uploader
);
2721 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2722 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2724 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2726 ctx
->blitter
= util_blitter_create(gallium
);
2727 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2729 assert(ctx
->blitter
);
2730 assert(ctx
->blitter_wallpaper
);
2732 /* Prepare for render! */
2734 panfrost_batch_init(ctx
);
2735 panfrost_emit_vertex_payload(ctx
);
2736 panfrost_invalidate_frame(ctx
);
2737 panfrost_default_shader_backend(ctx
);