panfrost: Drop QUADS primitive convert
[mesa.git] / src / gallium / drivers / panfrost / pan_context.c
1 /*
2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 */
26
27 #include <sys/poll.h>
28 #include <errno.h>
29
30 #include "pan_bo.h"
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
34
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
50
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
55 #include "pan_util.h"
56 #include "decode.h"
57 #include "util/pan_lower_framebuffer.h"
58
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch *batch, unsigned vertex_count)
61 {
62 struct panfrost_device *device = pan_device(batch->ctx->base.screen);
63 bool hierarchy = !(device->quirks & MIDGARD_NO_HIER_TILING);
64 struct midgard_tiler_descriptor t = {0};
65 unsigned height = batch->key.height;
66 unsigned width = batch->key.width;
67
68 t.hierarchy_mask =
69 panfrost_choose_hierarchy_mask(width, height, vertex_count, hierarchy);
70
71 /* Compute the polygon header size and use that to offset the body */
72
73 unsigned header_size = panfrost_tiler_header_size(
74 width, height, t.hierarchy_mask, hierarchy);
75
76 t.polygon_list_size = panfrost_tiler_full_size(
77 width, height, t.hierarchy_mask, hierarchy);
78
79 /* Sanity check */
80
81 if (vertex_count) {
82 struct panfrost_bo *tiler_heap;
83
84 tiler_heap = panfrost_batch_get_tiler_heap(batch);
85 t.polygon_list = panfrost_batch_get_polygon_list(batch,
86 header_size +
87 t.polygon_list_size);
88
89
90 /* Allow the entire tiler heap */
91 t.heap_start = tiler_heap->gpu;
92 t.heap_end = tiler_heap->gpu + tiler_heap->size;
93 } else {
94 struct panfrost_bo *tiler_dummy;
95
96 tiler_dummy = panfrost_batch_get_tiler_dummy(batch);
97 header_size = MALI_TILER_MINIMUM_HEADER_SIZE;
98
99 /* The tiler is disabled, so don't allow the tiler heap */
100 t.heap_start = tiler_dummy->gpu;
101 t.heap_end = t.heap_start;
102
103 /* Use a dummy polygon list */
104 t.polygon_list = tiler_dummy->gpu;
105
106 /* Disable the tiler */
107 if (hierarchy)
108 t.hierarchy_mask |= MALI_TILER_DISABLED;
109 else {
110 t.hierarchy_mask = MALI_TILER_USER;
111 t.polygon_list_size = MALI_TILER_MINIMUM_HEADER_SIZE + 4;
112
113 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
114 uint32_t *polygon_list_body = (uint32_t *) (tiler_dummy->cpu + header_size);
115 polygon_list_body[0] = 0xa0000000; /* TODO: Just that? */
116 }
117 }
118
119 t.polygon_list_body =
120 t.polygon_list + header_size;
121
122 return t;
123 }
124
125 static void
126 panfrost_clear(
127 struct pipe_context *pipe,
128 unsigned buffers,
129 const struct pipe_scissor_state *scissor_state,
130 const union pipe_color_union *color,
131 double depth, unsigned stencil)
132 {
133 struct panfrost_context *ctx = pan_context(pipe);
134
135 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
136 * the existing batch targeting this FBO has draws. We could probably
137 * avoid that by replacing plain clears by quad-draws with a specific
138 * color/depth/stencil value, thus avoiding the generation of extra
139 * fragment jobs.
140 */
141 struct panfrost_batch *batch = panfrost_get_fresh_batch_for_fbo(ctx);
142
143 panfrost_batch_add_fbo_bos(batch);
144 panfrost_batch_clear(batch, buffers, color, depth, stencil);
145 }
146
147 bool
148 panfrost_writes_point_size(struct panfrost_context *ctx)
149 {
150 assert(ctx->shader[PIPE_SHADER_VERTEX]);
151 struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
152
153 return vs->writes_point_size && ctx->active_prim == PIPE_PRIM_POINTS;
154 }
155
156 /* Compute number of UBOs active (more specifically, compute the highest UBO
157 * number addressable -- if there are gaps, include them in the count anyway).
158 * We always include UBO #0 in the count, since we *need* uniforms enabled for
159 * sysvals. */
160
161 unsigned
162 panfrost_ubo_count(struct panfrost_context *ctx, enum pipe_shader_type stage)
163 {
164 unsigned mask = ctx->constant_buffer[stage].enabled_mask | 1;
165 return 32 - __builtin_clz(mask);
166 }
167
168 /* The entire frame is in memory -- send it off to the kernel! */
169
170 void
171 panfrost_flush(
172 struct pipe_context *pipe,
173 struct pipe_fence_handle **fence,
174 unsigned flags)
175 {
176 struct panfrost_context *ctx = pan_context(pipe);
177 struct panfrost_device *dev = pan_device(pipe->screen);
178 uint32_t syncobj = 0;
179
180 if (fence)
181 drmSyncobjCreate(dev->fd, 0, &syncobj);
182
183 /* Submit all pending jobs */
184 panfrost_flush_all_batches(ctx, syncobj);
185
186 if (fence) {
187 struct panfrost_fence *f = panfrost_fence_create(ctx, syncobj);
188 pipe->screen->fence_reference(pipe->screen, fence, NULL);
189 *fence = (struct pipe_fence_handle *)f;
190 }
191
192 if (dev->debug & PAN_DBG_TRACE)
193 pandecode_next_frame();
194 }
195
196 static void
197 panfrost_texture_barrier(struct pipe_context *pipe, unsigned flags)
198 {
199 struct panfrost_context *ctx = pan_context(pipe);
200 panfrost_flush_all_batches(ctx, 0);
201 }
202
203 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
204
205 static int
206 g2m_draw_mode(enum pipe_prim_type mode)
207 {
208 switch (mode) {
209 DEFINE_CASE(POINTS);
210 DEFINE_CASE(LINES);
211 DEFINE_CASE(LINE_LOOP);
212 DEFINE_CASE(LINE_STRIP);
213 DEFINE_CASE(TRIANGLES);
214 DEFINE_CASE(TRIANGLE_STRIP);
215 DEFINE_CASE(TRIANGLE_FAN);
216 DEFINE_CASE(QUADS);
217 DEFINE_CASE(QUAD_STRIP);
218 DEFINE_CASE(POLYGON);
219
220 default:
221 unreachable("Invalid draw mode");
222 }
223 }
224
225 #undef DEFINE_CASE
226
227 static bool
228 panfrost_scissor_culls_everything(struct panfrost_context *ctx)
229 {
230 const struct pipe_scissor_state *ss = &ctx->scissor;
231
232 /* Check if we're scissoring at all */
233
234 if (!ctx->rasterizer->base.scissor)
235 return false;
236
237 return (ss->minx == ss->maxx) || (ss->miny == ss->maxy);
238 }
239
240 /* Count generated primitives (when there is no geom/tess shaders) for
241 * transform feedback */
242
243 static void
244 panfrost_statistics_record(
245 struct panfrost_context *ctx,
246 const struct pipe_draw_info *info)
247 {
248 if (!ctx->active_queries)
249 return;
250
251 uint32_t prims = u_prims_for_vertices(info->mode, info->count);
252 ctx->prims_generated += prims;
253
254 if (!ctx->streamout.num_targets)
255 return;
256
257 ctx->tf_prims_generated += prims;
258 }
259
260 static void
261 panfrost_update_streamout_offsets(struct panfrost_context *ctx)
262 {
263 for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) {
264 unsigned count;
265
266 count = u_stream_outputs_for_vertices(ctx->active_prim,
267 ctx->vertex_count);
268 ctx->streamout.offsets[i] += count;
269 }
270 }
271
272 static void
273 panfrost_draw_vbo(
274 struct pipe_context *pipe,
275 const struct pipe_draw_info *info)
276 {
277 struct panfrost_context *ctx = pan_context(pipe);
278
279 /* First of all, check the scissor to see if anything is drawn at all.
280 * If it's not, we drop the draw (mostly a conformance issue;
281 * well-behaved apps shouldn't hit this) */
282
283 if (panfrost_scissor_culls_everything(ctx))
284 return;
285
286 int mode = info->mode;
287
288 /* Fallback unsupported restart index */
289 unsigned primitive_index = (1 << (info->index_size * 8)) - 1;
290
291 if (info->primitive_restart && info->index_size
292 && info->restart_index != primitive_index) {
293 util_draw_vbo_without_prim_restart(pipe, info);
294 return;
295 }
296
297 /* Fallback for unsupported modes */
298
299 assert(ctx->rasterizer != NULL);
300
301 if (!(ctx->draw_modes & (1 << mode))) {
302 if (info->count < 4) {
303 /* Degenerate case? */
304 return;
305 }
306
307 util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base);
308 util_primconvert_draw_vbo(ctx->primconvert, info);
309 return;
310 }
311
312 /* Now that we have a guaranteed terminating path, find the job.
313 * Assignment commented out to prevent unused warning */
314
315 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
316
317 panfrost_batch_add_fbo_bos(batch);
318 panfrost_batch_set_requirements(batch);
319
320 /* Take into account a negative bias */
321 ctx->vertex_count = info->count + abs(info->index_bias);
322 ctx->instance_count = info->instance_count;
323 ctx->active_prim = info->mode;
324
325 struct mali_vertex_tiler_prefix vertex_prefix, tiler_prefix;
326 struct mali_vertex_tiler_postfix vertex_postfix, tiler_postfix;
327 union midgard_primitive_size primitive_size;
328 unsigned vertex_count;
329
330 panfrost_vt_init(ctx, PIPE_SHADER_VERTEX, &vertex_prefix, &vertex_postfix);
331 panfrost_vt_init(ctx, PIPE_SHADER_FRAGMENT, &tiler_prefix, &tiler_postfix);
332
333 panfrost_vt_set_draw_info(ctx, info, g2m_draw_mode(mode),
334 &vertex_postfix, &tiler_prefix,
335 &tiler_postfix, &vertex_count,
336 &ctx->padded_count);
337
338 panfrost_statistics_record(ctx, info);
339
340 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
341 * vertex_count, 1) */
342
343 panfrost_pack_work_groups_fused(&vertex_prefix, &tiler_prefix,
344 1, vertex_count, info->instance_count,
345 1, 1, 1);
346
347 /* Emit all sort of descriptors. */
348 panfrost_emit_vertex_data(batch, &vertex_postfix);
349 panfrost_emit_varying_descriptor(batch,
350 ctx->padded_count *
351 ctx->instance_count,
352 &vertex_postfix, &tiler_postfix,
353 &primitive_size);
354 panfrost_emit_shader_meta(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
355 panfrost_emit_shader_meta(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
356 panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
357 panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
358 panfrost_emit_texture_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
359 panfrost_emit_texture_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
360 panfrost_emit_const_buf(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
361 panfrost_emit_const_buf(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
362 panfrost_emit_viewport(batch, &tiler_postfix);
363
364 panfrost_vt_update_primitive_size(ctx, &tiler_prefix, &primitive_size);
365
366 /* Fire off the draw itself */
367 panfrost_emit_vertex_tiler_jobs(batch, &vertex_prefix, &vertex_postfix,
368 &tiler_prefix, &tiler_postfix,
369 &primitive_size);
370
371 /* Adjust the batch stack size based on the new shader stack sizes. */
372 panfrost_batch_adjust_stack_size(batch);
373
374 /* Increment transform feedback offsets */
375 panfrost_update_streamout_offsets(ctx);
376 }
377
378 /* CSO state */
379
380 static void
381 panfrost_generic_cso_delete(struct pipe_context *pctx, void *hwcso)
382 {
383 free(hwcso);
384 }
385
386 static void *
387 panfrost_create_rasterizer_state(
388 struct pipe_context *pctx,
389 const struct pipe_rasterizer_state *cso)
390 {
391 struct panfrost_rasterizer *so = CALLOC_STRUCT(panfrost_rasterizer);
392
393 so->base = *cso;
394
395 return so;
396 }
397
398 static void
399 panfrost_bind_rasterizer_state(
400 struct pipe_context *pctx,
401 void *hwcso)
402 {
403 struct panfrost_context *ctx = pan_context(pctx);
404
405 ctx->rasterizer = hwcso;
406
407 if (!hwcso)
408 return;
409
410 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
411 assert(ctx->rasterizer->base.offset_clamp == 0.0);
412
413 /* Point sprites are emulated */
414
415 struct panfrost_shader_state *variant = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
416
417 if (ctx->rasterizer->base.sprite_coord_enable || (variant && variant->point_sprite_mask))
418 ctx->base.bind_fs_state(&ctx->base, ctx->shader[PIPE_SHADER_FRAGMENT]);
419 }
420
421 static void *
422 panfrost_create_vertex_elements_state(
423 struct pipe_context *pctx,
424 unsigned num_elements,
425 const struct pipe_vertex_element *elements)
426 {
427 struct panfrost_vertex_state *so = CALLOC_STRUCT(panfrost_vertex_state);
428 struct panfrost_device *dev = pan_device(pctx->screen);
429
430 so->num_elements = num_elements;
431 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
432
433 for (int i = 0; i < num_elements; ++i) {
434 enum pipe_format fmt = elements[i].src_format;
435 const struct util_format_description *desc = util_format_description(fmt);
436 unsigned swizzle = 0;
437 if (dev->quirks & HAS_SWIZZLES)
438 swizzle = panfrost_translate_swizzle_4(desc->swizzle);
439 else
440 swizzle = panfrost_bifrost_swizzle(desc->nr_channels);
441
442 enum mali_format hw_format = panfrost_pipe_format_table[desc->format].hw;
443 so->formats[i] = (hw_format << 12) | swizzle;
444 assert(hw_format);
445 }
446
447 /* Let's also prepare vertex builtins */
448 if (dev->quirks & HAS_SWIZZLES)
449 so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
450 else
451 so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
452
453 if (dev->quirks & HAS_SWIZZLES)
454 so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
455 else
456 so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
457
458 return so;
459 }
460
461 static void
462 panfrost_bind_vertex_elements_state(
463 struct pipe_context *pctx,
464 void *hwcso)
465 {
466 struct panfrost_context *ctx = pan_context(pctx);
467 ctx->vertex = hwcso;
468 }
469
470 static void *
471 panfrost_create_shader_state(
472 struct pipe_context *pctx,
473 const struct pipe_shader_state *cso,
474 enum pipe_shader_type stage)
475 {
476 struct panfrost_shader_variants *so = CALLOC_STRUCT(panfrost_shader_variants);
477 struct panfrost_device *dev = pan_device(pctx->screen);
478 so->base = *cso;
479
480 /* Token deep copy to prevent memory corruption */
481
482 if (cso->type == PIPE_SHADER_IR_TGSI)
483 so->base.tokens = tgsi_dup_tokens(so->base.tokens);
484
485 /* Precompile for shader-db if we need to */
486 if (unlikely((dev->debug & PAN_DBG_PRECOMPILE) && cso->type == PIPE_SHADER_IR_NIR)) {
487 struct panfrost_context *ctx = pan_context(pctx);
488
489 struct panfrost_shader_state state;
490 uint64_t outputs_written;
491
492 panfrost_shader_compile(ctx, PIPE_SHADER_IR_NIR,
493 so->base.ir.nir,
494 tgsi_processor_to_shader_stage(stage),
495 &state, &outputs_written);
496 }
497
498 return so;
499 }
500
501 static void
502 panfrost_delete_shader_state(
503 struct pipe_context *pctx,
504 void *so)
505 {
506 struct panfrost_shader_variants *cso = (struct panfrost_shader_variants *) so;
507
508 if (cso->base.type == PIPE_SHADER_IR_TGSI) {
509 /* TODO: leaks TGSI tokens! */
510 }
511
512 for (unsigned i = 0; i < cso->variant_count; ++i) {
513 struct panfrost_shader_state *shader_state = &cso->variants[i];
514 panfrost_bo_unreference(shader_state->bo);
515 shader_state->bo = NULL;
516 }
517 free(cso->variants);
518
519 free(so);
520 }
521
522 static void *
523 panfrost_create_sampler_state(
524 struct pipe_context *pctx,
525 const struct pipe_sampler_state *cso)
526 {
527 struct panfrost_sampler_state *so = CALLOC_STRUCT(panfrost_sampler_state);
528 struct panfrost_device *device = pan_device(pctx->screen);
529
530 so->base = *cso;
531
532 if (device->quirks & IS_BIFROST)
533 panfrost_sampler_desc_init_bifrost(cso, (struct mali_bifrost_sampler_packed *) &so->hw);
534 else
535 panfrost_sampler_desc_init(cso, &so->hw);
536
537 return so;
538 }
539
540 static void
541 panfrost_bind_sampler_states(
542 struct pipe_context *pctx,
543 enum pipe_shader_type shader,
544 unsigned start_slot, unsigned num_sampler,
545 void **sampler)
546 {
547 assert(start_slot == 0);
548
549 struct panfrost_context *ctx = pan_context(pctx);
550
551 /* XXX: Should upload, not just copy? */
552 ctx->sampler_count[shader] = num_sampler;
553 memcpy(ctx->samplers[shader], sampler, num_sampler * sizeof (void *));
554 }
555
556 static bool
557 panfrost_variant_matches(
558 struct panfrost_context *ctx,
559 struct panfrost_shader_state *variant,
560 enum pipe_shader_type type)
561 {
562 struct panfrost_device *dev = pan_device(ctx->base.screen);
563 struct pipe_rasterizer_state *rasterizer = &ctx->rasterizer->base;
564
565 bool is_fragment = (type == PIPE_SHADER_FRAGMENT);
566
567 if (variant->outputs_read) {
568 struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
569
570 unsigned i;
571 BITSET_FOREACH_SET(i, &variant->outputs_read, 8) {
572 enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
573
574 if ((fb->nr_cbufs > i) && fb->cbufs[i])
575 fmt = fb->cbufs[i]->format;
576
577 const struct util_format_description *desc =
578 util_format_description(fmt);
579
580 if (pan_format_class_load(desc, dev->quirks) == PAN_FORMAT_NATIVE)
581 fmt = PIPE_FORMAT_NONE;
582
583 if (variant->rt_formats[i] != fmt)
584 return false;
585 }
586 }
587
588 /* Point sprites TODO on bifrost, always pass */
589 if (is_fragment && rasterizer && (rasterizer->sprite_coord_enable |
590 variant->point_sprite_mask)
591 && !(dev->quirks & IS_BIFROST)) {
592 /* Ensure the same varyings are turned to point sprites */
593 if (rasterizer->sprite_coord_enable != variant->point_sprite_mask)
594 return false;
595
596 /* Ensure the orientation is correct */
597 bool upper_left =
598 rasterizer->sprite_coord_mode ==
599 PIPE_SPRITE_COORD_UPPER_LEFT;
600
601 if (variant->point_sprite_upper_left != upper_left)
602 return false;
603 }
604
605 /* Otherwise, we're good to go */
606 return true;
607 }
608
609 /**
610 * Fix an uncompiled shader's stream output info, and produce a bitmask
611 * of which VARYING_SLOT_* are captured for stream output.
612 *
613 * Core Gallium stores output->register_index as a "slot" number, where
614 * slots are assigned consecutively to all outputs in info->outputs_written.
615 * This naive packing of outputs doesn't work for us - we too have slots,
616 * but the layout is defined by the VUE map, which we won't have until we
617 * compile a specific shader variant. So, we remap these and simply store
618 * VARYING_SLOT_* in our copy's output->register_index fields.
619 *
620 * We then produce a bitmask of outputs which are used for SO.
621 *
622 * Implementation from iris.
623 */
624
625 static uint64_t
626 update_so_info(struct pipe_stream_output_info *so_info,
627 uint64_t outputs_written)
628 {
629 uint64_t so_outputs = 0;
630 uint8_t reverse_map[64] = {0};
631 unsigned slot = 0;
632
633 while (outputs_written)
634 reverse_map[slot++] = u_bit_scan64(&outputs_written);
635
636 for (unsigned i = 0; i < so_info->num_outputs; i++) {
637 struct pipe_stream_output *output = &so_info->output[i];
638
639 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
640 output->register_index = reverse_map[output->register_index];
641
642 so_outputs |= 1ull << output->register_index;
643 }
644
645 return so_outputs;
646 }
647
648 static void
649 panfrost_bind_shader_state(
650 struct pipe_context *pctx,
651 void *hwcso,
652 enum pipe_shader_type type)
653 {
654 struct panfrost_context *ctx = pan_context(pctx);
655 struct panfrost_device *dev = pan_device(ctx->base.screen);
656 ctx->shader[type] = hwcso;
657
658 if (!hwcso) return;
659
660 /* Match the appropriate variant */
661
662 signed variant = -1;
663 struct panfrost_shader_variants *variants = (struct panfrost_shader_variants *) hwcso;
664
665 for (unsigned i = 0; i < variants->variant_count; ++i) {
666 if (panfrost_variant_matches(ctx, &variants->variants[i], type)) {
667 variant = i;
668 break;
669 }
670 }
671
672 if (variant == -1) {
673 /* No variant matched, so create a new one */
674 variant = variants->variant_count++;
675
676 if (variants->variant_count > variants->variant_space) {
677 unsigned old_space = variants->variant_space;
678
679 variants->variant_space *= 2;
680 if (variants->variant_space == 0)
681 variants->variant_space = 1;
682
683 /* Arbitrary limit to stop runaway programs from
684 * creating an unbounded number of shader variants. */
685 assert(variants->variant_space < 1024);
686
687 unsigned msize = sizeof(struct panfrost_shader_state);
688 variants->variants = realloc(variants->variants,
689 variants->variant_space * msize);
690
691 memset(&variants->variants[old_space], 0,
692 (variants->variant_space - old_space) * msize);
693 }
694
695 struct panfrost_shader_state *v =
696 &variants->variants[variant];
697
698 if (type == PIPE_SHADER_FRAGMENT) {
699 struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
700 for (unsigned i = 0; i < fb->nr_cbufs; ++i) {
701 enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
702
703 if ((fb->nr_cbufs > i) && fb->cbufs[i])
704 fmt = fb->cbufs[i]->format;
705
706 const struct util_format_description *desc =
707 util_format_description(fmt);
708
709 if (pan_format_class_load(desc, dev->quirks) == PAN_FORMAT_NATIVE)
710 fmt = PIPE_FORMAT_NONE;
711
712 v->rt_formats[i] = fmt;
713 }
714
715 /* Point sprites are TODO on Bifrost */
716 if (ctx->rasterizer && !(dev->quirks & IS_BIFROST)) {
717 v->point_sprite_mask = ctx->rasterizer->base.sprite_coord_enable;
718 v->point_sprite_upper_left =
719 ctx->rasterizer->base.sprite_coord_mode ==
720 PIPE_SPRITE_COORD_UPPER_LEFT;
721 }
722 }
723 }
724
725 /* Select this variant */
726 variants->active_variant = variant;
727
728 struct panfrost_shader_state *shader_state = &variants->variants[variant];
729 assert(panfrost_variant_matches(ctx, shader_state, type));
730
731 /* We finally have a variant, so compile it */
732
733 if (!shader_state->compiled) {
734 uint64_t outputs_written = 0;
735
736 panfrost_shader_compile(ctx, variants->base.type,
737 variants->base.type == PIPE_SHADER_IR_NIR ?
738 variants->base.ir.nir :
739 variants->base.tokens,
740 tgsi_processor_to_shader_stage(type),
741 shader_state,
742 &outputs_written);
743
744 shader_state->compiled = true;
745
746 /* Fixup the stream out information, since what Gallium returns
747 * normally is mildly insane */
748
749 shader_state->stream_output = variants->base.stream_output;
750 shader_state->so_mask =
751 update_so_info(&shader_state->stream_output, outputs_written);
752 }
753 }
754
755 static void *
756 panfrost_create_vs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
757 {
758 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
759 }
760
761 static void *
762 panfrost_create_fs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
763 {
764 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
765 }
766
767 static void
768 panfrost_bind_vs_state(struct pipe_context *pctx, void *hwcso)
769 {
770 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
771 }
772
773 static void
774 panfrost_bind_fs_state(struct pipe_context *pctx, void *hwcso)
775 {
776 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
777 }
778
779 static void
780 panfrost_set_vertex_buffers(
781 struct pipe_context *pctx,
782 unsigned start_slot,
783 unsigned num_buffers,
784 const struct pipe_vertex_buffer *buffers)
785 {
786 struct panfrost_context *ctx = pan_context(pctx);
787
788 util_set_vertex_buffers_mask(ctx->vertex_buffers, &ctx->vb_mask, buffers, start_slot, num_buffers);
789 }
790
791 static void
792 panfrost_set_constant_buffer(
793 struct pipe_context *pctx,
794 enum pipe_shader_type shader, uint index,
795 const struct pipe_constant_buffer *buf)
796 {
797 struct panfrost_context *ctx = pan_context(pctx);
798 struct panfrost_constant_buffer *pbuf = &ctx->constant_buffer[shader];
799
800 util_copy_constant_buffer(&pbuf->cb[index], buf);
801
802 unsigned mask = (1 << index);
803
804 if (unlikely(!buf)) {
805 pbuf->enabled_mask &= ~mask;
806 pbuf->dirty_mask &= ~mask;
807 return;
808 }
809
810 pbuf->enabled_mask |= mask;
811 pbuf->dirty_mask |= mask;
812 }
813
814 static void
815 panfrost_set_stencil_ref(
816 struct pipe_context *pctx,
817 const struct pipe_stencil_ref *ref)
818 {
819 struct panfrost_context *ctx = pan_context(pctx);
820 ctx->stencil_ref = *ref;
821 }
822
823 void
824 panfrost_create_sampler_view_bo(struct panfrost_sampler_view *so,
825 struct pipe_context *pctx,
826 struct pipe_resource *texture)
827 {
828 struct panfrost_device *device = pan_device(pctx->screen);
829 struct panfrost_resource *prsrc = (struct panfrost_resource *)texture;
830 enum pipe_format format = so->base.format;
831 assert(prsrc->bo);
832
833 /* Format to access the stencil portion of a Z32_S8 texture */
834 if (format == PIPE_FORMAT_X32_S8X24_UINT) {
835 assert(prsrc->separate_stencil);
836 texture = &prsrc->separate_stencil->base;
837 prsrc = (struct panfrost_resource *)texture;
838 format = texture->format;
839 }
840
841 const struct util_format_description *desc = util_format_description(format);
842
843 bool fake_rgtc = !panfrost_supports_compressed_format(device, MALI_BC4_UNORM);
844
845 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC && fake_rgtc) {
846 if (desc->is_snorm)
847 format = PIPE_FORMAT_R8G8B8A8_SNORM;
848 else
849 format = PIPE_FORMAT_R8G8B8A8_UNORM;
850 desc = util_format_description(format);
851 }
852
853 so->texture_bo = prsrc->bo->gpu;
854 so->modifier = prsrc->modifier;
855
856 unsigned char user_swizzle[4] = {
857 so->base.swizzle_r,
858 so->base.swizzle_g,
859 so->base.swizzle_b,
860 so->base.swizzle_a
861 };
862
863 /* In the hardware, array_size refers specifically to array textures,
864 * whereas in Gallium, it also covers cubemaps */
865
866 unsigned array_size = texture->array_size;
867 unsigned depth = texture->depth0;
868
869 if (so->base.target == PIPE_TEXTURE_CUBE) {
870 /* TODO: Cubemap arrays */
871 assert(array_size == 6);
872 array_size /= 6;
873 }
874
875 /* MSAA only supported for 2D textures (and 2D texture arrays via an
876 * extension currently unimplemented */
877
878 if (so->base.target == PIPE_TEXTURE_2D) {
879 assert(depth == 1);
880 depth = texture->nr_samples;
881 } else {
882 /* MSAA only supported for 2D textures */
883 assert(texture->nr_samples <= 1);
884 }
885
886 enum mali_texture_dimension type =
887 panfrost_translate_texture_dimension(so->base.target);
888
889 if (device->quirks & IS_BIFROST) {
890 unsigned char composed_swizzle[4];
891 util_format_compose_swizzles(desc->swizzle, user_swizzle, composed_swizzle);
892
893 unsigned size = panfrost_estimate_texture_payload_size(
894 so->base.u.tex.first_level,
895 so->base.u.tex.last_level,
896 so->base.u.tex.first_layer,
897 so->base.u.tex.last_layer,
898 texture->nr_samples,
899 type, prsrc->modifier);
900
901 so->bo = panfrost_bo_create(device, size, 0);
902
903 panfrost_new_texture_bifrost(
904 &so->bifrost_descriptor,
905 texture->width0, texture->height0,
906 depth, array_size,
907 format,
908 type, prsrc->modifier,
909 so->base.u.tex.first_level,
910 so->base.u.tex.last_level,
911 so->base.u.tex.first_layer,
912 so->base.u.tex.last_layer,
913 texture->nr_samples,
914 prsrc->cubemap_stride,
915 panfrost_translate_swizzle_4(composed_swizzle),
916 prsrc->bo->gpu,
917 prsrc->slices,
918 so->bo);
919 } else {
920 unsigned size = panfrost_estimate_texture_payload_size(
921 so->base.u.tex.first_level,
922 so->base.u.tex.last_level,
923 so->base.u.tex.first_layer,
924 so->base.u.tex.last_layer,
925 texture->nr_samples,
926 type, prsrc->modifier);
927 size += MALI_MIDGARD_TEXTURE_LENGTH;
928
929 so->bo = panfrost_bo_create(device, size, 0);
930
931 panfrost_new_texture(
932 so->bo->cpu,
933 texture->width0, texture->height0,
934 depth, array_size,
935 format,
936 type, prsrc->modifier,
937 so->base.u.tex.first_level,
938 so->base.u.tex.last_level,
939 so->base.u.tex.first_layer,
940 so->base.u.tex.last_layer,
941 texture->nr_samples,
942 prsrc->cubemap_stride,
943 panfrost_translate_swizzle_4(user_swizzle),
944 prsrc->bo->gpu,
945 prsrc->slices);
946 }
947 }
948
949 static struct pipe_sampler_view *
950 panfrost_create_sampler_view(
951 struct pipe_context *pctx,
952 struct pipe_resource *texture,
953 const struct pipe_sampler_view *template)
954 {
955 struct panfrost_sampler_view *so = rzalloc(pctx, struct panfrost_sampler_view);
956
957 pipe_reference(NULL, &texture->reference);
958
959 so->base = *template;
960 so->base.texture = texture;
961 so->base.reference.count = 1;
962 so->base.context = pctx;
963
964 panfrost_create_sampler_view_bo(so, pctx, texture);
965
966 return (struct pipe_sampler_view *) so;
967 }
968
969 static void
970 panfrost_set_sampler_views(
971 struct pipe_context *pctx,
972 enum pipe_shader_type shader,
973 unsigned start_slot, unsigned num_views,
974 struct pipe_sampler_view **views)
975 {
976 struct panfrost_context *ctx = pan_context(pctx);
977 unsigned new_nr = 0;
978 unsigned i;
979
980 assert(start_slot == 0);
981
982 for (i = 0; i < num_views; ++i) {
983 if (views[i])
984 new_nr = i + 1;
985 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
986 views[i]);
987 }
988
989 for (; i < ctx->sampler_view_count[shader]; i++) {
990 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
991 NULL);
992 }
993 ctx->sampler_view_count[shader] = new_nr;
994 }
995
996 static void
997 panfrost_sampler_view_destroy(
998 struct pipe_context *pctx,
999 struct pipe_sampler_view *pview)
1000 {
1001 struct panfrost_sampler_view *view = (struct panfrost_sampler_view *) pview;
1002
1003 pipe_resource_reference(&pview->texture, NULL);
1004 panfrost_bo_unreference(view->bo);
1005 ralloc_free(view);
1006 }
1007
1008 static void
1009 panfrost_set_shader_buffers(
1010 struct pipe_context *pctx,
1011 enum pipe_shader_type shader,
1012 unsigned start, unsigned count,
1013 const struct pipe_shader_buffer *buffers,
1014 unsigned writable_bitmask)
1015 {
1016 struct panfrost_context *ctx = pan_context(pctx);
1017
1018 util_set_shader_buffers_mask(ctx->ssbo[shader], &ctx->ssbo_mask[shader],
1019 buffers, start, count);
1020 }
1021
1022 static void
1023 panfrost_set_framebuffer_state(struct pipe_context *pctx,
1024 const struct pipe_framebuffer_state *fb)
1025 {
1026 struct panfrost_context *ctx = pan_context(pctx);
1027
1028 util_copy_framebuffer_state(&ctx->pipe_framebuffer, fb);
1029 ctx->batch = NULL;
1030
1031 /* We may need to generate a new variant if the fragment shader is
1032 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1033 struct panfrost_shader_variants *fs = ctx->shader[PIPE_SHADER_FRAGMENT];
1034
1035 if (fs && fs->variant_count && fs->variants[fs->active_variant].outputs_read)
1036 ctx->base.bind_fs_state(&ctx->base, fs);
1037 }
1038
1039 static inline unsigned
1040 pan_pipe_to_stencil_op(enum pipe_stencil_op in)
1041 {
1042 switch (in) {
1043 case PIPE_STENCIL_OP_KEEP: return MALI_STENCIL_OP_KEEP;
1044 case PIPE_STENCIL_OP_ZERO: return MALI_STENCIL_OP_ZERO;
1045 case PIPE_STENCIL_OP_REPLACE: return MALI_STENCIL_OP_REPLACE;
1046 case PIPE_STENCIL_OP_INCR: return MALI_STENCIL_OP_INCR_SAT;
1047 case PIPE_STENCIL_OP_DECR: return MALI_STENCIL_OP_DECR_SAT;
1048 case PIPE_STENCIL_OP_INCR_WRAP: return MALI_STENCIL_OP_INCR_WRAP;
1049 case PIPE_STENCIL_OP_DECR_WRAP: return MALI_STENCIL_OP_DECR_WRAP;
1050 case PIPE_STENCIL_OP_INVERT: return MALI_STENCIL_OP_INVERT;
1051 default: unreachable("Invalid stencil op");
1052 }
1053 }
1054
1055 static inline void
1056 pan_pipe_to_stencil(const struct pipe_stencil_state *in, void *out)
1057 {
1058 pan_pack(out, STENCIL, cfg) {
1059 cfg.mask = in->valuemask;
1060 cfg.compare_function = panfrost_translate_compare_func(in->func);
1061 cfg.stencil_fail = pan_pipe_to_stencil_op(in->fail_op);
1062 cfg.depth_fail = pan_pipe_to_stencil_op(in->zfail_op);
1063 cfg.depth_pass = pan_pipe_to_stencil_op(in->zpass_op);
1064 }
1065 }
1066
1067 static void *
1068 panfrost_create_depth_stencil_state(struct pipe_context *pipe,
1069 const struct pipe_depth_stencil_alpha_state *zsa)
1070 {
1071 struct panfrost_zsa_state *so = CALLOC_STRUCT(panfrost_zsa_state);
1072 so->base = *zsa;
1073
1074 pan_pipe_to_stencil(&zsa->stencil[0], &so->stencil_front);
1075 pan_pipe_to_stencil(&zsa->stencil[1], &so->stencil_back);
1076
1077 so->stencil_mask_front = zsa->stencil[0].writemask;
1078
1079 if (zsa->stencil[1].enabled)
1080 so->stencil_mask_back = zsa->stencil[1].writemask;
1081 else
1082 so->stencil_mask_back = so->stencil_mask_front;
1083
1084 /* Alpha lowered by frontend */
1085 assert(!zsa->alpha.enabled);
1086
1087 /* TODO: Bounds test should be easy */
1088 assert(!zsa->depth.bounds_test);
1089
1090 return so;
1091 }
1092
1093 static void
1094 panfrost_bind_depth_stencil_state(struct pipe_context *pipe,
1095 void *cso)
1096 {
1097 struct panfrost_context *ctx = pan_context(pipe);
1098 struct panfrost_zsa_state *zsa = cso;
1099 ctx->depth_stencil = zsa;
1100 }
1101
1102 static void
1103 panfrost_delete_depth_stencil_state(struct pipe_context *pipe, void *depth)
1104 {
1105 free( depth );
1106 }
1107
1108 static void
1109 panfrost_set_sample_mask(struct pipe_context *pipe,
1110 unsigned sample_mask)
1111 {
1112 struct panfrost_context *ctx = pan_context(pipe);
1113 ctx->sample_mask = sample_mask;
1114 }
1115
1116 static void
1117 panfrost_set_min_samples(struct pipe_context *pipe,
1118 unsigned min_samples)
1119 {
1120 struct panfrost_context *ctx = pan_context(pipe);
1121 ctx->min_samples = min_samples;
1122 }
1123
1124
1125 static void
1126 panfrost_set_clip_state(struct pipe_context *pipe,
1127 const struct pipe_clip_state *clip)
1128 {
1129 //struct panfrost_context *panfrost = pan_context(pipe);
1130 }
1131
1132 static void
1133 panfrost_set_viewport_states(struct pipe_context *pipe,
1134 unsigned start_slot,
1135 unsigned num_viewports,
1136 const struct pipe_viewport_state *viewports)
1137 {
1138 struct panfrost_context *ctx = pan_context(pipe);
1139
1140 assert(start_slot == 0);
1141 assert(num_viewports == 1);
1142
1143 ctx->pipe_viewport = *viewports;
1144 }
1145
1146 static void
1147 panfrost_set_scissor_states(struct pipe_context *pipe,
1148 unsigned start_slot,
1149 unsigned num_scissors,
1150 const struct pipe_scissor_state *scissors)
1151 {
1152 struct panfrost_context *ctx = pan_context(pipe);
1153
1154 assert(start_slot == 0);
1155 assert(num_scissors == 1);
1156
1157 ctx->scissor = *scissors;
1158 }
1159
1160 static void
1161 panfrost_set_polygon_stipple(struct pipe_context *pipe,
1162 const struct pipe_poly_stipple *stipple)
1163 {
1164 //struct panfrost_context *panfrost = pan_context(pipe);
1165 }
1166
1167 static void
1168 panfrost_set_active_query_state(struct pipe_context *pipe,
1169 bool enable)
1170 {
1171 struct panfrost_context *ctx = pan_context(pipe);
1172 ctx->active_queries = enable;
1173 }
1174
1175 static void
1176 panfrost_destroy(struct pipe_context *pipe)
1177 {
1178 struct panfrost_context *panfrost = pan_context(pipe);
1179
1180 if (panfrost->blitter)
1181 util_blitter_destroy(panfrost->blitter);
1182
1183 if (panfrost->blitter_wallpaper)
1184 util_blitter_destroy(panfrost->blitter_wallpaper);
1185
1186 util_unreference_framebuffer_state(&panfrost->pipe_framebuffer);
1187 u_upload_destroy(pipe->stream_uploader);
1188
1189 ralloc_free(pipe);
1190 }
1191
1192 static struct pipe_query *
1193 panfrost_create_query(struct pipe_context *pipe,
1194 unsigned type,
1195 unsigned index)
1196 {
1197 struct panfrost_query *q = rzalloc(pipe, struct panfrost_query);
1198
1199 q->type = type;
1200 q->index = index;
1201
1202 return (struct pipe_query *) q;
1203 }
1204
1205 static void
1206 panfrost_destroy_query(struct pipe_context *pipe, struct pipe_query *q)
1207 {
1208 struct panfrost_query *query = (struct panfrost_query *) q;
1209
1210 if (query->bo) {
1211 panfrost_bo_unreference(query->bo);
1212 query->bo = NULL;
1213 }
1214
1215 ralloc_free(q);
1216 }
1217
1218 static bool
1219 panfrost_begin_query(struct pipe_context *pipe, struct pipe_query *q)
1220 {
1221 struct panfrost_context *ctx = pan_context(pipe);
1222 struct panfrost_query *query = (struct panfrost_query *) q;
1223
1224 switch (query->type) {
1225 case PIPE_QUERY_OCCLUSION_COUNTER:
1226 case PIPE_QUERY_OCCLUSION_PREDICATE:
1227 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1228 /* Allocate a bo for the query results to be stored */
1229 if (!query->bo) {
1230 query->bo = panfrost_bo_create(
1231 pan_device(ctx->base.screen),
1232 sizeof(unsigned), 0);
1233 }
1234
1235 unsigned *result = (unsigned *)query->bo->cpu;
1236 *result = 0; /* Default to 0 if nothing at all drawn. */
1237 ctx->occlusion_query = query;
1238 break;
1239
1240 /* Geometry statistics are computed in the driver. XXX: geom/tess
1241 * shaders.. */
1242
1243 case PIPE_QUERY_PRIMITIVES_GENERATED:
1244 query->start = ctx->prims_generated;
1245 break;
1246 case PIPE_QUERY_PRIMITIVES_EMITTED:
1247 query->start = ctx->tf_prims_generated;
1248 break;
1249
1250 default:
1251 /* TODO: timestamp queries, etc? */
1252 break;
1253 }
1254
1255 return true;
1256 }
1257
1258 static bool
1259 panfrost_end_query(struct pipe_context *pipe, struct pipe_query *q)
1260 {
1261 struct panfrost_context *ctx = pan_context(pipe);
1262 struct panfrost_query *query = (struct panfrost_query *) q;
1263
1264 switch (query->type) {
1265 case PIPE_QUERY_OCCLUSION_COUNTER:
1266 case PIPE_QUERY_OCCLUSION_PREDICATE:
1267 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1268 ctx->occlusion_query = NULL;
1269 break;
1270 case PIPE_QUERY_PRIMITIVES_GENERATED:
1271 query->end = ctx->prims_generated;
1272 break;
1273 case PIPE_QUERY_PRIMITIVES_EMITTED:
1274 query->end = ctx->tf_prims_generated;
1275 break;
1276 }
1277
1278 return true;
1279 }
1280
1281 static bool
1282 panfrost_get_query_result(struct pipe_context *pipe,
1283 struct pipe_query *q,
1284 bool wait,
1285 union pipe_query_result *vresult)
1286 {
1287 struct panfrost_query *query = (struct panfrost_query *) q;
1288 struct panfrost_context *ctx = pan_context(pipe);
1289
1290
1291 switch (query->type) {
1292 case PIPE_QUERY_OCCLUSION_COUNTER:
1293 case PIPE_QUERY_OCCLUSION_PREDICATE:
1294 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1295 panfrost_flush_batches_accessing_bo(ctx, query->bo, false);
1296 panfrost_bo_wait(query->bo, INT64_MAX, false);
1297
1298 /* Read back the query results */
1299 unsigned *result = (unsigned *) query->bo->cpu;
1300 unsigned passed = *result;
1301
1302 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
1303 vresult->u64 = passed;
1304 } else {
1305 vresult->b = !!passed;
1306 }
1307
1308 break;
1309
1310 case PIPE_QUERY_PRIMITIVES_GENERATED:
1311 case PIPE_QUERY_PRIMITIVES_EMITTED:
1312 panfrost_flush_all_batches(ctx, 0);
1313 vresult->u64 = query->end - query->start;
1314 break;
1315
1316 default:
1317 /* TODO: more queries */
1318 break;
1319 }
1320
1321 return true;
1322 }
1323
1324 static struct pipe_stream_output_target *
1325 panfrost_create_stream_output_target(struct pipe_context *pctx,
1326 struct pipe_resource *prsc,
1327 unsigned buffer_offset,
1328 unsigned buffer_size)
1329 {
1330 struct pipe_stream_output_target *target;
1331
1332 target = rzalloc(pctx, struct pipe_stream_output_target);
1333
1334 if (!target)
1335 return NULL;
1336
1337 pipe_reference_init(&target->reference, 1);
1338 pipe_resource_reference(&target->buffer, prsc);
1339
1340 target->context = pctx;
1341 target->buffer_offset = buffer_offset;
1342 target->buffer_size = buffer_size;
1343
1344 return target;
1345 }
1346
1347 static void
1348 panfrost_stream_output_target_destroy(struct pipe_context *pctx,
1349 struct pipe_stream_output_target *target)
1350 {
1351 pipe_resource_reference(&target->buffer, NULL);
1352 ralloc_free(target);
1353 }
1354
1355 static void
1356 panfrost_set_stream_output_targets(struct pipe_context *pctx,
1357 unsigned num_targets,
1358 struct pipe_stream_output_target **targets,
1359 const unsigned *offsets)
1360 {
1361 struct panfrost_context *ctx = pan_context(pctx);
1362 struct panfrost_streamout *so = &ctx->streamout;
1363
1364 assert(num_targets <= ARRAY_SIZE(so->targets));
1365
1366 for (unsigned i = 0; i < num_targets; i++) {
1367 if (offsets[i] != -1)
1368 so->offsets[i] = offsets[i];
1369
1370 pipe_so_target_reference(&so->targets[i], targets[i]);
1371 }
1372
1373 for (unsigned i = 0; i < so->num_targets; i++)
1374 pipe_so_target_reference(&so->targets[i], NULL);
1375
1376 so->num_targets = num_targets;
1377 }
1378
1379 struct pipe_context *
1380 panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags)
1381 {
1382 struct panfrost_context *ctx = rzalloc(screen, struct panfrost_context);
1383 struct pipe_context *gallium = (struct pipe_context *) ctx;
1384 struct panfrost_device *dev = pan_device(screen);
1385
1386 gallium->screen = screen;
1387
1388 gallium->destroy = panfrost_destroy;
1389
1390 gallium->set_framebuffer_state = panfrost_set_framebuffer_state;
1391
1392 gallium->flush = panfrost_flush;
1393 gallium->clear = panfrost_clear;
1394 gallium->draw_vbo = panfrost_draw_vbo;
1395 gallium->texture_barrier = panfrost_texture_barrier;
1396
1397 gallium->set_vertex_buffers = panfrost_set_vertex_buffers;
1398 gallium->set_constant_buffer = panfrost_set_constant_buffer;
1399 gallium->set_shader_buffers = panfrost_set_shader_buffers;
1400
1401 gallium->set_stencil_ref = panfrost_set_stencil_ref;
1402
1403 gallium->create_sampler_view = panfrost_create_sampler_view;
1404 gallium->set_sampler_views = panfrost_set_sampler_views;
1405 gallium->sampler_view_destroy = panfrost_sampler_view_destroy;
1406
1407 gallium->create_rasterizer_state = panfrost_create_rasterizer_state;
1408 gallium->bind_rasterizer_state = panfrost_bind_rasterizer_state;
1409 gallium->delete_rasterizer_state = panfrost_generic_cso_delete;
1410
1411 gallium->create_vertex_elements_state = panfrost_create_vertex_elements_state;
1412 gallium->bind_vertex_elements_state = panfrost_bind_vertex_elements_state;
1413 gallium->delete_vertex_elements_state = panfrost_generic_cso_delete;
1414
1415 gallium->create_fs_state = panfrost_create_fs_state;
1416 gallium->delete_fs_state = panfrost_delete_shader_state;
1417 gallium->bind_fs_state = panfrost_bind_fs_state;
1418
1419 gallium->create_vs_state = panfrost_create_vs_state;
1420 gallium->delete_vs_state = panfrost_delete_shader_state;
1421 gallium->bind_vs_state = panfrost_bind_vs_state;
1422
1423 gallium->create_sampler_state = panfrost_create_sampler_state;
1424 gallium->delete_sampler_state = panfrost_generic_cso_delete;
1425 gallium->bind_sampler_states = panfrost_bind_sampler_states;
1426
1427 gallium->create_depth_stencil_alpha_state = panfrost_create_depth_stencil_state;
1428 gallium->bind_depth_stencil_alpha_state = panfrost_bind_depth_stencil_state;
1429 gallium->delete_depth_stencil_alpha_state = panfrost_delete_depth_stencil_state;
1430
1431 gallium->set_sample_mask = panfrost_set_sample_mask;
1432 gallium->set_min_samples = panfrost_set_min_samples;
1433
1434 gallium->set_clip_state = panfrost_set_clip_state;
1435 gallium->set_viewport_states = panfrost_set_viewport_states;
1436 gallium->set_scissor_states = panfrost_set_scissor_states;
1437 gallium->set_polygon_stipple = panfrost_set_polygon_stipple;
1438 gallium->set_active_query_state = panfrost_set_active_query_state;
1439
1440 gallium->create_query = panfrost_create_query;
1441 gallium->destroy_query = panfrost_destroy_query;
1442 gallium->begin_query = panfrost_begin_query;
1443 gallium->end_query = panfrost_end_query;
1444 gallium->get_query_result = panfrost_get_query_result;
1445
1446 gallium->create_stream_output_target = panfrost_create_stream_output_target;
1447 gallium->stream_output_target_destroy = panfrost_stream_output_target_destroy;
1448 gallium->set_stream_output_targets = panfrost_set_stream_output_targets;
1449
1450 panfrost_resource_context_init(gallium);
1451 panfrost_blend_context_init(gallium);
1452 panfrost_compute_context_init(gallium);
1453
1454 gallium->stream_uploader = u_upload_create_default(gallium);
1455 gallium->const_uploader = gallium->stream_uploader;
1456 assert(gallium->stream_uploader);
1457
1458 /* All of our GPUs support ES mode. Midgard supports additionally
1459 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1460
1461 ctx->draw_modes = (1 << (PIPE_PRIM_QUADS + 1)) - 1;
1462
1463 if (!(dev->quirks & IS_BIFROST)) {
1464 ctx->draw_modes |= (1 << PIPE_PRIM_QUAD_STRIP);
1465 ctx->draw_modes |= (1 << PIPE_PRIM_POLYGON);
1466 }
1467
1468 ctx->primconvert = util_primconvert_create(gallium, ctx->draw_modes);
1469
1470 ctx->blitter = util_blitter_create(gallium);
1471 ctx->blitter_wallpaper = util_blitter_create(gallium);
1472
1473 assert(ctx->blitter);
1474 assert(ctx->blitter_wallpaper);
1475
1476 /* Prepare for render! */
1477
1478 panfrost_batch_init(ctx);
1479
1480 if (!(dev->quirks & IS_BIFROST)) {
1481 for (unsigned c = 0; c < PIPE_MAX_COLOR_BUFS; ++c)
1482 ctx->blit_blend.rt[c].shaders = _mesa_hash_table_u64_create(ctx);
1483 }
1484
1485 /* By default mask everything on */
1486 ctx->sample_mask = ~0;
1487 ctx->active_queries = true;
1488
1489 return gallium;
1490 }