2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_format.h"
34 #include "util/macros.h"
35 #include "util/u_format.h"
36 #include "util/u_inlines.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_memory.h"
39 #include "util/u_vbuf.h"
40 #include "util/half_float.h"
41 #include "util/u_helpers.h"
42 #include "util/u_format.h"
43 #include "util/u_prim.h"
44 #include "util/u_prim_restart.h"
45 #include "indices/u_primconvert.h"
46 #include "tgsi/tgsi_parse.h"
47 #include "tgsi/tgsi_from_mesa.h"
48 #include "util/u_math.h"
50 #include "pan_screen.h"
51 #include "pan_blending.h"
52 #include "pan_blend_shaders.h"
55 /* Framebuffer descriptor */
57 static struct midgard_tiler_descriptor
58 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
60 struct midgard_tiler_descriptor t
= {};
61 unsigned height
= batch
->key
.height
;
62 unsigned width
= batch
->key
.width
;
65 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
67 /* Compute the polygon header size and use that to offset the body */
69 unsigned header_size
= panfrost_tiler_header_size(
70 width
, height
, t
.hierarchy_mask
);
72 t
.polygon_list_size
= panfrost_tiler_full_size(
73 width
, height
, t
.hierarchy_mask
);
77 if (t
.hierarchy_mask
) {
78 struct panfrost_bo
*tiler_heap
;
80 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
81 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
86 /* Allow the entire tiler heap */
87 t
.heap_start
= tiler_heap
->gpu
;
88 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
90 struct panfrost_bo
*tiler_dummy
;
92 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
94 /* The tiler is disabled, so don't allow the tiler heap */
95 t
.heap_start
= tiler_dummy
->gpu
;
96 t
.heap_end
= t
.heap_start
;
98 /* Use a dummy polygon list */
99 t
.polygon_list
= tiler_dummy
->gpu
;
101 /* Disable the tiler */
102 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
105 t
.polygon_list_body
=
106 t
.polygon_list
+ header_size
;
111 struct mali_single_framebuffer
112 panfrost_emit_sfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
114 unsigned width
= batch
->key
.width
;
115 unsigned height
= batch
->key
.height
;
117 struct mali_single_framebuffer framebuffer
= {
118 .width
= MALI_POSITIVE(width
),
119 .height
= MALI_POSITIVE(height
),
121 .format
= 0x30000000,
122 .clear_flags
= 0x1000,
123 .unknown_address_0
= panfrost_batch_get_scratchpad(batch
)->gpu
,
124 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
),
130 struct bifrost_framebuffer
131 panfrost_emit_mfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
133 unsigned width
= batch
->key
.width
;
134 unsigned height
= batch
->key
.height
;
136 struct bifrost_framebuffer framebuffer
= {
137 .unk0
= 0x1e5, /* 1e4 if no spill */
138 .width1
= MALI_POSITIVE(width
),
139 .height1
= MALI_POSITIVE(height
),
140 .width2
= MALI_POSITIVE(width
),
141 .height2
= MALI_POSITIVE(height
),
145 .rt_count_1
= MALI_POSITIVE(batch
->key
.nr_cbufs
),
150 .scratchpad
= panfrost_batch_get_scratchpad(batch
)->gpu
,
151 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
)
159 struct pipe_context
*pipe
,
161 const union pipe_color_union
*color
,
162 double depth
, unsigned stencil
)
164 struct panfrost_context
*ctx
= pan_context(pipe
);
166 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
167 * the existing batch targeting this FBO has draws. We could probably
168 * avoid that by replacing plain clears by quad-draws with a specific
169 * color/depth/stencil value, thus avoiding the generation of extra
170 * fragment/set_value jobs.
172 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
174 panfrost_batch_add_fbo_bos(batch
);
175 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
179 panfrost_attach_vt_mfbd(struct panfrost_batch
*batch
)
181 struct bifrost_framebuffer mfbd
= panfrost_emit_mfbd(batch
, ~0);
183 return panfrost_upload_transient(batch
, &mfbd
, sizeof(mfbd
)) | MALI_MFBD
;
187 panfrost_attach_vt_sfbd(struct panfrost_batch
*batch
)
189 struct mali_single_framebuffer sfbd
= panfrost_emit_sfbd(batch
, ~0);
191 return panfrost_upload_transient(batch
, &sfbd
, sizeof(sfbd
)) | MALI_SFBD
;
195 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
197 /* Skip the attach if we can */
199 if (ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
) {
200 assert(ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
204 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
205 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
207 if (!batch
->framebuffer
)
208 batch
->framebuffer
= screen
->require_sfbd
?
209 panfrost_attach_vt_sfbd(batch
) :
210 panfrost_attach_vt_mfbd(batch
);
212 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
213 ctx
->payloads
[i
].postfix
.framebuffer
= batch
->framebuffer
;
216 /* Reset per-frame context, called on context initialisation as well as after
217 * flushing a frame */
220 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
222 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
223 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
226 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
229 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
231 /* TODO: When does this need to be handled? */
232 ctx
->active_queries
= true;
235 /* In practice, every field of these payloads should be configurable
236 * arbitrarily, which means these functions are basically catch-all's for
237 * as-of-yet unwavering unknowns */
240 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
242 /* 0x2 bit clear on 32-bit T6XX */
244 struct midgard_payload_vertex_tiler payload
= {
245 .gl_enables
= 0x4 | 0x2,
248 /* Vertex and compute are closely coupled, so share a payload */
250 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
251 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
255 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
257 struct midgard_payload_vertex_tiler payload
= {
259 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
263 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
267 translate_tex_wrap(enum pipe_tex_wrap w
)
270 case PIPE_TEX_WRAP_REPEAT
:
271 return MALI_WRAP_REPEAT
;
273 /* TODO: lower GL_CLAMP? */
274 case PIPE_TEX_WRAP_CLAMP
:
275 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
276 return MALI_WRAP_CLAMP_TO_EDGE
;
278 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
279 return MALI_WRAP_CLAMP_TO_BORDER
;
281 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
282 return MALI_WRAP_MIRRORED_REPEAT
;
285 unreachable("Invalid wrap");
290 panfrost_translate_compare_func(enum pipe_compare_func in
)
293 case PIPE_FUNC_NEVER
:
294 return MALI_FUNC_NEVER
;
297 return MALI_FUNC_LESS
;
299 case PIPE_FUNC_EQUAL
:
300 return MALI_FUNC_EQUAL
;
302 case PIPE_FUNC_LEQUAL
:
303 return MALI_FUNC_LEQUAL
;
305 case PIPE_FUNC_GREATER
:
306 return MALI_FUNC_GREATER
;
308 case PIPE_FUNC_NOTEQUAL
:
309 return MALI_FUNC_NOTEQUAL
;
311 case PIPE_FUNC_GEQUAL
:
312 return MALI_FUNC_GEQUAL
;
314 case PIPE_FUNC_ALWAYS
:
315 return MALI_FUNC_ALWAYS
;
318 unreachable("Invalid func");
323 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
326 case PIPE_FUNC_NEVER
:
327 return MALI_ALT_FUNC_NEVER
;
330 return MALI_ALT_FUNC_LESS
;
332 case PIPE_FUNC_EQUAL
:
333 return MALI_ALT_FUNC_EQUAL
;
335 case PIPE_FUNC_LEQUAL
:
336 return MALI_ALT_FUNC_LEQUAL
;
338 case PIPE_FUNC_GREATER
:
339 return MALI_ALT_FUNC_GREATER
;
341 case PIPE_FUNC_NOTEQUAL
:
342 return MALI_ALT_FUNC_NOTEQUAL
;
344 case PIPE_FUNC_GEQUAL
:
345 return MALI_ALT_FUNC_GEQUAL
;
347 case PIPE_FUNC_ALWAYS
:
348 return MALI_ALT_FUNC_ALWAYS
;
351 unreachable("Invalid alt func");
356 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
359 case PIPE_STENCIL_OP_KEEP
:
360 return MALI_STENCIL_KEEP
;
362 case PIPE_STENCIL_OP_ZERO
:
363 return MALI_STENCIL_ZERO
;
365 case PIPE_STENCIL_OP_REPLACE
:
366 return MALI_STENCIL_REPLACE
;
368 case PIPE_STENCIL_OP_INCR
:
369 return MALI_STENCIL_INCR
;
371 case PIPE_STENCIL_OP_DECR
:
372 return MALI_STENCIL_DECR
;
374 case PIPE_STENCIL_OP_INCR_WRAP
:
375 return MALI_STENCIL_INCR_WRAP
;
377 case PIPE_STENCIL_OP_DECR_WRAP
:
378 return MALI_STENCIL_DECR_WRAP
;
380 case PIPE_STENCIL_OP_INVERT
:
381 return MALI_STENCIL_INVERT
;
384 unreachable("Invalid stencil op");
389 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
391 out
->ref
= 0; /* Gallium gets it from elsewhere */
393 out
->mask
= in
->valuemask
;
394 out
->func
= panfrost_translate_compare_func(in
->func
);
395 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
396 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
397 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
401 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
403 struct mali_shader_meta shader
= {
404 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
406 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
407 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
410 /* unknown2_4 has 0x10 bit set on T6XX. We don't know why this is
411 * required (independent of 32-bit/64-bit descriptors), or why it's not
412 * used on later GPU revisions. Otherwise, all shader jobs fault on
413 * these earlier chips (perhaps this is a chicken bit of some kind).
414 * More investigation is needed. */
417 shader
.unknown2_4
|= 0x10;
420 struct pipe_stencil_state default_stencil
= {
422 .func
= PIPE_FUNC_ALWAYS
,
423 .fail_op
= MALI_STENCIL_KEEP
,
424 .zfail_op
= MALI_STENCIL_KEEP
,
425 .zpass_op
= MALI_STENCIL_KEEP
,
430 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
431 shader
.stencil_mask_front
= default_stencil
.writemask
;
433 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
434 shader
.stencil_mask_back
= default_stencil
.writemask
;
436 if (default_stencil
.enabled
)
437 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
439 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
442 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
443 * graphics command stream. It should be called once per draw, accordding to
444 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
445 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
448 struct panfrost_transfer
449 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
451 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
452 struct mali_job_descriptor_header job
= {
453 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
454 .job_descriptor_size
= 1,
457 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
459 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sizeof(job
) + sizeof(*payload
));
460 memcpy(transfer
.cpu
, &job
, sizeof(job
));
461 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
466 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
468 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
469 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
471 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
475 panfrost_writes_point_size(struct panfrost_context
*ctx
)
477 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
478 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
480 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
483 /* Stage the attribute descriptors so we can adjust src_offset
484 * to let BOs align nicely */
487 panfrost_stage_attributes(struct panfrost_context
*ctx
)
489 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
490 struct panfrost_vertex_state
*so
= ctx
->vertex
;
492 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
493 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
494 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
496 /* Copy as-is for the first pass */
497 memcpy(target
, so
->hw
, sz
);
499 /* Fixup offsets for the second pass. Recall that the hardware
500 * calculates attribute addresses as:
502 * addr = base + (stride * vtx) + src_offset;
504 * However, on Mali, base must be aligned to 64-bytes, so we
507 * base' = base & ~63 = base - (base & 63)
509 * To compensate when using base' (see emit_vertex_data), we have
510 * to adjust src_offset by the masked off piece:
512 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
513 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
514 * = base + (stride * vtx) + src_offset
520 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
522 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
523 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
524 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
525 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
527 /* Adjust by the masked off bits of the offset */
528 target
[i
].src_offset
+= (addr
& 63);
530 /* Also, somewhat obscurely per-instance data needs to be
531 * offset in response to a delayed start in an indexed draw */
533 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
534 target
[i
].src_offset
-= buf
->stride
* start
;
540 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
544 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
546 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
547 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
549 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
552 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
553 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
555 struct panfrost_transfer transfer
=
556 panfrost_allocate_transient(batch
, transfer_size
);
558 struct mali_sampler_descriptor
*desc
=
559 (struct mali_sampler_descriptor
*) transfer
.cpu
;
561 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
562 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
564 upload
= transfer
.gpu
;
567 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
571 static enum mali_texture_layout
572 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
574 /* TODO: other linear depth textures */
575 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
577 switch (rsrc
->layout
) {
579 return MALI_TEXTURE_AFBC
;
582 return MALI_TEXTURE_TILED
;
584 return is_depth
? MALI_TEXTURE_TILED
: MALI_TEXTURE_LINEAR
;
586 unreachable("Invalid texture layout");
592 struct panfrost_context
*ctx
,
593 enum pipe_shader_type st
,
594 struct panfrost_sampler_view
*view
)
599 struct pipe_sampler_view
*pview
= &view
->base
;
600 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
602 /* Do we interleave an explicit stride with every element? */
604 bool has_manual_stride
= view
->manual_stride
;
606 /* For easy access */
608 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
609 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
610 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
611 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
612 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
614 /* Lower-bit is set when sampling from colour AFBC */
615 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
616 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
617 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
619 /* Add the BO to the job so it's retained until the job is done. */
620 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
621 panfrost_batch_add_bo(batch
, rsrc
->bo
,
622 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
623 panfrost_bo_access_for_stage(st
));
625 /* Add the usage flags in, since they can change across the CSO
626 * lifetime due to layout switches */
628 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
629 view
->hw
.format
.manual_stride
= has_manual_stride
;
631 /* Inject the addresses in, interleaving mip levels, cube faces, and
632 * strides in that order */
636 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
637 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
639 view
->hw
.payload
[idx
++] =
640 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
642 if (has_manual_stride
) {
643 view
->hw
.payload
[idx
++] =
644 rsrc
->slices
[l
].stride
;
649 return panfrost_upload_transient(batch
, &view
->hw
,
650 sizeof(struct mali_texture_descriptor
));
654 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
656 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
658 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
659 mali_ptr trampoline
= 0;
661 if (ctx
->sampler_view_count
[t
]) {
662 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
664 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
666 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
668 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
671 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
675 struct sysval_uniform
{
684 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
685 struct sysval_uniform
*uniform
)
687 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
689 uniform
->f
[0] = vp
->scale
[0];
690 uniform
->f
[1] = vp
->scale
[1];
691 uniform
->f
[2] = vp
->scale
[2];
694 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
695 struct sysval_uniform
*uniform
)
697 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
699 uniform
->f
[0] = vp
->translate
[0];
700 uniform
->f
[1] = vp
->translate
[1];
701 uniform
->f
[2] = vp
->translate
[2];
704 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
705 enum pipe_shader_type st
,
706 unsigned int sysvalid
,
707 struct sysval_uniform
*uniform
)
709 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
710 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
711 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
712 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
715 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
718 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
719 tex
->u
.tex
.first_level
);
722 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
723 tex
->u
.tex
.first_level
);
726 uniform
->i
[dim
] = tex
->texture
->array_size
;
729 static void panfrost_upload_ssbo_sysval(
730 struct panfrost_context
*ctx
,
731 enum pipe_shader_type st
,
733 struct sysval_uniform
*uniform
)
735 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
736 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
738 /* Compute address */
739 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
740 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
742 panfrost_batch_add_bo(batch
, bo
,
743 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
744 panfrost_bo_access_for_stage(st
));
746 /* Upload address and size as sysval */
747 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
748 uniform
->u
[2] = sb
.buffer_size
;
751 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
752 struct sysval_uniform
*uniform
)
754 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
755 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
756 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
759 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
760 struct panfrost_shader_state
*ss
,
761 enum pipe_shader_type st
)
763 struct sysval_uniform
*uniforms
= (void *)buf
;
765 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
766 int sysval
= ss
->sysval
[i
];
768 switch (PAN_SYSVAL_TYPE(sysval
)) {
769 case PAN_SYSVAL_VIEWPORT_SCALE
:
770 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
772 case PAN_SYSVAL_VIEWPORT_OFFSET
:
773 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
775 case PAN_SYSVAL_TEXTURE_SIZE
:
776 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
779 case PAN_SYSVAL_SSBO
:
780 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
783 case PAN_SYSVAL_NUM_WORK_GROUPS
:
784 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
794 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
796 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
797 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
800 return rsrc
->bo
->cpu
;
801 else if (cb
->user_buffer
)
802 return cb
->user_buffer
;
804 unreachable("No constant buffer");
808 panfrost_map_constant_buffer_gpu(
809 struct panfrost_context
*ctx
,
810 enum pipe_shader_type st
,
811 struct panfrost_constant_buffer
*buf
,
814 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
815 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
816 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
819 panfrost_batch_add_bo(batch
, rsrc
->bo
,
820 PAN_BO_ACCESS_SHARED
|
822 panfrost_bo_access_for_stage(st
));
823 return rsrc
->bo
->gpu
;
824 } else if (cb
->user_buffer
) {
825 return panfrost_upload_transient(batch
, cb
->user_buffer
, cb
->buffer_size
);
827 unreachable("No constant buffer");
831 /* Compute number of UBOs active (more specifically, compute the highest UBO
832 * number addressable -- if there are gaps, include them in the count anyway).
833 * We always include UBO #0 in the count, since we *need* uniforms enabled for
837 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
839 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
840 return 32 - __builtin_clz(mask
);
843 /* Fixes up a shader state with current state, returning a GPU address to the
847 panfrost_patch_shader_state(
848 struct panfrost_context
*ctx
,
849 struct panfrost_shader_state
*ss
,
850 enum pipe_shader_type stage
,
853 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
854 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
856 ss
->tripipe
->midgard1
.flags
= 0x220;
858 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
859 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
861 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
863 /* Add the shader BO to the batch. */
864 panfrost_batch_add_bo(batch
, ss
->bo
,
865 PAN_BO_ACCESS_PRIVATE
|
867 panfrost_bo_access_for_stage(stage
));
869 /* We can't reuse over frames; that's not safe. The descriptor must be
870 * transient uploaded */
873 return panfrost_upload_transient(batch
, ss
->tripipe
,
874 sizeof(struct mali_shader_meta
));
877 /* If we don't need an upload, don't bother */
883 panfrost_patch_shader_state_compute(
884 struct panfrost_context
*ctx
,
885 enum pipe_shader_type stage
,
888 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
891 ctx
->payloads
[stage
].postfix
._shader_upper
= 0;
895 struct panfrost_shader_state
*s
= &all
->variants
[all
->active_variant
];
897 ctx
->payloads
[stage
].postfix
._shader_upper
=
898 panfrost_patch_shader_state(ctx
, s
, stage
, should_upload
) >> 4;
901 /* Go through dirty flags and actualise them in the cmdstream. */
904 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
906 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
907 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
909 panfrost_batch_add_fbo_bos(batch
);
910 panfrost_attach_vt_framebuffer(ctx
);
912 if (with_vertex_data
) {
913 panfrost_emit_vertex_data(batch
);
915 /* Varyings emitted for -all- geometry */
916 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
917 panfrost_emit_varying_descriptor(ctx
, total_count
);
920 bool msaa
= ctx
->rasterizer
->base
.multisample
;
922 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
923 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
925 /* TODO: Sample size */
926 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
927 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
930 panfrost_batch_set_requirements(batch
);
932 if (ctx
->occlusion_query
) {
933 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
934 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
937 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_VERTEX
, true);
938 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_COMPUTE
, true);
940 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
941 /* Check if we need to link the gl_PointSize varying */
942 if (!panfrost_writes_point_size(ctx
)) {
943 /* If the size is constant, write it out. Otherwise,
944 * don't touch primitive_size (since we would clobber
945 * the pointer there) */
947 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
951 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
952 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
953 ctx
->dirty
|= PAN_DIRTY_FS
;
955 if (ctx
->dirty
& PAN_DIRTY_FS
) {
956 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
957 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
959 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
961 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
964 COPY(attribute_count
);
968 COPY(midgard1
.uniform_count
);
969 COPY(midgard1
.uniform_buffer_count
);
970 COPY(midgard1
.work_count
);
971 COPY(midgard1
.flags
);
972 COPY(midgard1
.unknown2
);
976 /* Get blending setup */
977 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
979 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
981 for (unsigned c
= 0; c
< rt_count
; ++c
)
982 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
984 /* If there is a blend shader, work registers are shared. XXX: opt */
986 for (unsigned c
= 0; c
< rt_count
; ++c
) {
987 if (blend
[c
].is_shader
)
988 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
991 /* Set late due to depending on render state */
992 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
994 /* Depending on whether it's legal to in the given shader, we
995 * try to enable early-z testing (or forward-pixel kill?) */
997 if (!variant
->can_discard
)
998 flags
|= MALI_EARLY_Z
;
1000 /* Any time texturing is used, derivatives are implicitly
1001 * calculated, so we need to enable helper invocations */
1003 if (variant
->helper_invocations
)
1004 flags
|= MALI_HELPER_INVOCATIONS
;
1006 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
1008 /* Assign the stencil refs late */
1010 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
1011 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
1012 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
1014 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
1015 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
1017 /* CAN_DISCARD should be set if the fragment shader possibly
1018 * contains a 'discard' instruction. It is likely this is
1019 * related to optimizations related to forward-pixel kill, as
1020 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1021 * thing?" by Peter Harris
1024 if (variant
->can_discard
) {
1025 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1026 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1029 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1030 * *also* copied to the blend_meta appended (by convention),
1031 * but this is the field actually read by the hardware. (Or
1032 * maybe both are read...?) */
1034 if (blend
[0].is_shader
) {
1035 ctx
->fragment_shader_core
.blend
.shader
=
1036 blend
[0].shader
.bo
->gpu
| blend
[0].shader
.first_tag
;
1038 ctx
->fragment_shader_core
.blend
.shader
= 0;
1041 if (screen
->require_sfbd
) {
1042 /* When only a single render target platform is used, the blend
1043 * information is inside the shader meta itself. We
1044 * additionally need to signal CAN_DISCARD for nontrivial blend
1045 * modes (so we're able to read back the destination buffer) */
1047 if (!blend
[0].is_shader
) {
1048 ctx
->fragment_shader_core
.blend
.equation
=
1049 *blend
[0].equation
.equation
;
1050 ctx
->fragment_shader_core
.blend
.constant
=
1051 blend
[0].equation
.constant
;
1054 if (!blend
[0].no_blending
) {
1055 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1059 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1060 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1061 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1063 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1065 if (!screen
->require_sfbd
) {
1066 /* Additional blend descriptor tacked on for jobs using MFBD */
1068 struct midgard_blend_rt rts
[4];
1070 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1071 unsigned blend_count
= 0x200;
1073 if (blend
[i
].is_shader
) {
1074 /* For a blend shader, the bottom nibble corresponds to
1075 * the number of work registers used, which signals the
1076 * -existence- of a blend shader */
1078 assert(blend
[i
].shader
.work_count
>= 2);
1079 blend_count
|= MIN2(blend
[i
].shader
.work_count
, 3);
1081 /* Otherwise, the bottom bit simply specifies if
1082 * blending (anything other than REPLACE) is enabled */
1084 if (!blend
[i
].no_blending
)
1090 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1091 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1092 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1094 rts
[i
].flags
= blend_count
;
1097 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1099 if (!ctx
->blend
->base
.dither
)
1100 rts
[i
].flags
|= MALI_BLEND_NO_DITHER
;
1102 /* TODO: sRGB in blend shaders is currently
1103 * unimplemented. Contact me (Alyssa) if you're
1104 * interested in working on this. We have
1105 * native Midgard ops for helping here, but
1106 * they're not well-understood yet. */
1108 assert(!(is_srgb
&& blend
[i
].is_shader
));
1110 if (blend
[i
].is_shader
) {
1111 rts
[i
].blend
.shader
= blend
[i
].shader
.bo
->gpu
| blend
[i
].shader
.first_tag
;
1113 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1114 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1118 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1122 /* We stage to transient, so always dirty.. */
1124 panfrost_stage_attributes(ctx
);
1126 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1127 panfrost_upload_sampler_descriptors(ctx
);
1129 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1130 panfrost_upload_texture_descriptors(ctx
);
1132 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1134 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1135 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1140 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1142 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1144 /* Uniforms are implicitly UBO #0 */
1145 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1147 /* Allocate room for the sysval and the uniforms */
1148 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1149 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1150 size_t size
= sys_size
+ uniform_size
;
1151 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1153 /* Upload sysvals requested by the shader */
1154 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1156 /* Upload uniforms */
1158 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1159 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1163 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1165 struct mali_vertex_tiler_postfix
*postfix
=
1166 &ctx
->payloads
[i
].postfix
;
1168 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1171 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1172 assert(ubo_count
>= 1);
1174 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1175 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1177 /* Upload uniforms as a UBO */
1178 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1179 ubos
[0].ptr
= transfer
.gpu
>> 2;
1181 /* The rest are honest-to-goodness UBOs */
1183 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1184 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1186 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1187 bool empty
= usz
== 0;
1189 if (!enabled
|| empty
) {
1190 /* Stub out disabled UBOs to catch accesses */
1193 ubos
[ubo
].ptr
= 0xDEAD0000;
1197 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, i
, buf
, ubo
);
1199 unsigned bytes_per_field
= 16;
1200 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1201 unsigned fields
= aligned
/ bytes_per_field
;
1203 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1204 ubos
[ubo
].ptr
= gpu
>> 2;
1207 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1208 postfix
->uniforms
= transfer
.gpu
;
1209 postfix
->uniform_buffers
= ubufs
;
1211 buf
->dirty_mask
= 0;
1214 /* TODO: Upload the viewport somewhere more appropriate */
1216 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1217 * (somewhat) asymmetric ints. */
1218 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1220 struct mali_viewport view
= {
1221 /* By default, do no viewport clipping, i.e. clip to (-inf,
1222 * inf) in each direction. Clipping to the viewport in theory
1223 * should work, but in practice causes issues when we're not
1224 * explicitly trying to scissor */
1226 .clip_minx
= -INFINITY
,
1227 .clip_miny
= -INFINITY
,
1228 .clip_maxx
= INFINITY
,
1229 .clip_maxy
= INFINITY
,
1232 /* Always scissor to the viewport by default. */
1233 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1234 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1236 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1237 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1239 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1240 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1242 /* Apply the scissor test */
1244 unsigned minx
, miny
, maxx
, maxy
;
1246 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1247 minx
= MAX2(ss
->minx
, vp_minx
);
1248 miny
= MAX2(ss
->miny
, vp_miny
);
1249 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1250 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1258 /* Hardware needs the min/max to be strictly ordered, so flip if we
1259 * need to. The viewport transformation in the vertex shader will
1260 * handle the negatives if we don't */
1263 unsigned temp
= miny
;
1269 unsigned temp
= minx
;
1280 /* Clamp to the framebuffer size as a last check */
1282 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1283 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1285 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1286 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1288 /* Update the job, unless we're doing wallpapering (whose lack of
1289 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1290 * just... be faster :) */
1292 if (!ctx
->wallpaper_batch
)
1293 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1297 view
.viewport0
[0] = minx
;
1298 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1300 view
.viewport0
[1] = miny
;
1301 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1303 view
.clip_minz
= minz
;
1304 view
.clip_maxz
= maxz
;
1306 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1307 panfrost_upload_transient(batch
,
1309 sizeof(struct mali_viewport
));
1314 /* Corresponds to exactly one draw, but does not submit anything */
1317 panfrost_queue_draw(struct panfrost_context
*ctx
)
1319 /* Handle dirty flags now */
1320 panfrost_emit_for_draw(ctx
, true);
1322 /* If rasterizer discard is enable, only submit the vertex */
1324 bool rasterizer_discard
= ctx
->rasterizer
1325 && ctx
->rasterizer
->base
.rasterizer_discard
;
1327 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1328 struct panfrost_transfer tiler
;
1330 if (!rasterizer_discard
)
1331 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1333 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1335 if (rasterizer_discard
)
1336 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1337 else if (ctx
->wallpaper_batch
&& batch
->first_tiler
.gpu
)
1338 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1340 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1343 /* The entire frame is in memory -- send it off to the kernel! */
1347 struct pipe_context
*pipe
,
1348 struct pipe_fence_handle
**fence
,
1351 struct panfrost_context
*ctx
= pan_context(pipe
);
1352 struct util_dynarray fences
;
1354 /* We must collect the fences before the flush is done, otherwise we'll
1355 * lose track of them.
1358 util_dynarray_init(&fences
, NULL
);
1359 hash_table_foreach(ctx
->batches
, hentry
) {
1360 struct panfrost_batch
*batch
= hentry
->data
;
1362 panfrost_batch_fence_reference(batch
->out_sync
);
1363 util_dynarray_append(&fences
,
1364 struct panfrost_batch_fence
*,
1369 /* Submit all pending jobs */
1370 panfrost_flush_all_batches(ctx
, false);
1373 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
1374 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1375 *fence
= (struct pipe_fence_handle
*)f
;
1377 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
1378 panfrost_batch_fence_unreference(*fence
);
1380 util_dynarray_fini(&fences
);
1384 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1387 g2m_draw_mode(enum pipe_prim_type mode
)
1390 DEFINE_CASE(POINTS
);
1392 DEFINE_CASE(LINE_LOOP
);
1393 DEFINE_CASE(LINE_STRIP
);
1394 DEFINE_CASE(TRIANGLES
);
1395 DEFINE_CASE(TRIANGLE_STRIP
);
1396 DEFINE_CASE(TRIANGLE_FAN
);
1398 DEFINE_CASE(QUAD_STRIP
);
1399 DEFINE_CASE(POLYGON
);
1402 unreachable("Invalid draw mode");
1409 panfrost_translate_index_size(unsigned size
)
1413 return MALI_DRAW_INDEXED_UINT8
;
1416 return MALI_DRAW_INDEXED_UINT16
;
1419 return MALI_DRAW_INDEXED_UINT32
;
1422 unreachable("Invalid index size");
1426 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1427 * good for the duration of the draw (transient), could last longer */
1430 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1432 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1434 off_t offset
= info
->start
* info
->index_size
;
1435 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1437 if (!info
->has_user_indices
) {
1438 /* Only resources can be directly mapped */
1439 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1440 PAN_BO_ACCESS_SHARED
|
1441 PAN_BO_ACCESS_READ
|
1442 PAN_BO_ACCESS_VERTEX_TILER
);
1443 return rsrc
->bo
->gpu
+ offset
;
1445 /* Otherwise, we need to upload to transient memory */
1446 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1447 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1452 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1454 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1456 /* Check if we're scissoring at all */
1458 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1461 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1464 /* Count generated primitives (when there is no geom/tess shaders) for
1465 * transform feedback */
1468 panfrost_statistics_record(
1469 struct panfrost_context
*ctx
,
1470 const struct pipe_draw_info
*info
)
1472 if (!ctx
->active_queries
)
1475 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1476 ctx
->prims_generated
+= prims
;
1478 if (!ctx
->streamout
.num_targets
)
1481 ctx
->tf_prims_generated
+= prims
;
1486 struct pipe_context
*pipe
,
1487 const struct pipe_draw_info
*info
)
1489 struct panfrost_context
*ctx
= pan_context(pipe
);
1491 /* First of all, check the scissor to see if anything is drawn at all.
1492 * If it's not, we drop the draw (mostly a conformance issue;
1493 * well-behaved apps shouldn't hit this) */
1495 if (panfrost_scissor_culls_everything(ctx
))
1498 int mode
= info
->mode
;
1500 /* Fallback unsupported restart index */
1501 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1503 if (info
->primitive_restart
&& info
->index_size
1504 && info
->restart_index
!= primitive_index
) {
1505 util_draw_vbo_without_prim_restart(pipe
, info
);
1509 /* Fallback for unsupported modes */
1511 assert(ctx
->rasterizer
!= NULL
);
1513 if (!(ctx
->draw_modes
& (1 << mode
))) {
1514 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1515 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1517 if (info
->count
< 4) {
1518 /* Degenerate case? */
1522 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1523 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1528 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1529 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1531 /* Now that we have a guaranteed terminating path, find the job.
1532 * Assignment commented out to prevent unused warning */
1534 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1536 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1538 /* Take into account a negative bias */
1539 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1540 ctx
->instance_count
= info
->instance_count
;
1541 ctx
->active_prim
= info
->mode
;
1543 /* For non-indexed draws, they're the same */
1544 unsigned vertex_count
= ctx
->vertex_count
;
1546 unsigned draw_flags
= 0;
1548 /* The draw flags interpret how primitive size is interpreted */
1550 if (panfrost_writes_point_size(ctx
))
1551 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1553 if (info
->primitive_restart
)
1554 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1556 /* For higher amounts of vertices (greater than what fits in a 16-bit
1557 * short), the other value is needed, otherwise there will be bizarre
1558 * rendering artefacts. It's not clear what these values mean yet. This
1559 * change is also needed for instancing and sometimes points (perhaps
1560 * related to dynamically setting gl_PointSize) */
1562 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1563 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1564 bool instanced
= ctx
->instance_count
> 1;
1566 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1568 /* This doesn't make much sense */
1569 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1570 draw_flags
|= 0x800;
1573 panfrost_statistics_record(ctx
, info
);
1575 if (info
->index_size
) {
1576 /* Calculate the min/max index used so we can figure out how
1577 * many times to invoke the vertex shader */
1579 /* Fetch / calculate index bounds */
1580 unsigned min_index
= 0, max_index
= 0;
1582 if (info
->max_index
== ~0u) {
1583 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1585 min_index
= info
->min_index
;
1586 max_index
= info
->max_index
;
1589 /* Use the corresponding values */
1590 vertex_count
= max_index
- min_index
+ 1;
1591 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1592 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1594 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1595 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1597 //assert(!info->restart_index); /* TODO: Research */
1599 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1600 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1602 /* Index count == vertex count, if no indexing is applied, as
1603 * if it is internally indexed in the expected order */
1605 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1606 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1608 /* Reverse index state */
1609 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1612 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1613 * vertex_count, 1) */
1615 panfrost_pack_work_groups_fused(
1616 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1617 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1618 1, vertex_count
, info
->instance_count
,
1621 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1623 /* Encode the padded vertex count */
1625 if (info
->instance_count
> 1) {
1626 /* Triangles have non-even vertex counts so they change how
1627 * padding works internally */
1630 mode
== PIPE_PRIM_TRIANGLES
||
1631 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1632 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1634 struct pan_shift_odd so
=
1635 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1637 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= so
.shift
;
1638 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= so
.shift
;
1640 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= so
.odd
;
1641 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= so
.odd
;
1643 ctx
->padded_count
= pan_expand_shift_odd(so
);
1645 ctx
->padded_count
= vertex_count
;
1647 /* Reset instancing state */
1648 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1649 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1650 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1651 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1654 /* Fire off the draw itself */
1655 panfrost_queue_draw(ctx
);
1657 /* Increment transform feedback offsets */
1659 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1660 unsigned output_count
= u_stream_outputs_for_vertices(
1661 ctx
->active_prim
, ctx
->vertex_count
);
1663 ctx
->streamout
.offsets
[i
] += output_count
;
1670 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1676 panfrost_create_rasterizer_state(
1677 struct pipe_context
*pctx
,
1678 const struct pipe_rasterizer_state
*cso
)
1680 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1684 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1685 so
->tiler_gl_enables
= 0x7;
1688 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1690 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1691 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1693 if (cso
->cull_face
& PIPE_FACE_BACK
)
1694 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1700 panfrost_bind_rasterizer_state(
1701 struct pipe_context
*pctx
,
1704 struct panfrost_context
*ctx
= pan_context(pctx
);
1706 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1710 ctx
->rasterizer
= hwcso
;
1711 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1713 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1714 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1716 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1717 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1719 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1721 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1722 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1724 /* Point sprites are emulated */
1726 struct panfrost_shader_state
*variant
=
1727 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1729 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1730 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1734 panfrost_create_vertex_elements_state(
1735 struct pipe_context
*pctx
,
1736 unsigned num_elements
,
1737 const struct pipe_vertex_element
*elements
)
1739 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1741 so
->num_elements
= num_elements
;
1742 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1744 for (int i
= 0; i
< num_elements
; ++i
) {
1745 so
->hw
[i
].index
= i
;
1747 enum pipe_format fmt
= elements
[i
].src_format
;
1748 const struct util_format_description
*desc
= util_format_description(fmt
);
1749 so
->hw
[i
].unknown1
= 0x2;
1750 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1752 so
->hw
[i
].format
= panfrost_find_format(desc
);
1754 /* The field itself should probably be shifted over */
1755 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1762 panfrost_bind_vertex_elements_state(
1763 struct pipe_context
*pctx
,
1766 struct panfrost_context
*ctx
= pan_context(pctx
);
1768 ctx
->vertex
= hwcso
;
1769 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1773 panfrost_create_shader_state(
1774 struct pipe_context
*pctx
,
1775 const struct pipe_shader_state
*cso
)
1777 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1780 /* Token deep copy to prevent memory corruption */
1782 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1783 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1789 panfrost_delete_shader_state(
1790 struct pipe_context
*pctx
,
1793 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1795 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1796 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1799 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1800 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1801 panfrost_bo_unreference(shader_state
->bo
);
1802 shader_state
->bo
= NULL
;
1809 panfrost_create_sampler_state(
1810 struct pipe_context
*pctx
,
1811 const struct pipe_sampler_state
*cso
)
1813 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1816 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1818 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1819 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1820 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1822 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1823 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1824 unsigned mip_filter
= mip_linear
?
1825 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1826 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1828 struct mali_sampler_descriptor sampler_descriptor
= {
1829 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1830 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1831 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1832 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1833 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1835 cso
->border_color
.f
[0],
1836 cso
->border_color
.f
[1],
1837 cso
->border_color
.f
[2],
1838 cso
->border_color
.f
[3]
1840 .min_lod
= FIXED_16(cso
->min_lod
),
1841 .max_lod
= FIXED_16(cso
->max_lod
),
1842 .seamless_cube_map
= cso
->seamless_cube_map
,
1845 /* If necessary, we disable mipmapping in the sampler descriptor by
1846 * clamping the LOD as tight as possible (from 0 to epsilon,
1847 * essentially -- remember these are fixed point numbers, so
1850 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1851 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1853 /* Enforce that there is something in the middle by adding epsilon*/
1855 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1856 sampler_descriptor
.max_lod
++;
1859 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1861 so
->hw
= sampler_descriptor
;
1867 panfrost_bind_sampler_states(
1868 struct pipe_context
*pctx
,
1869 enum pipe_shader_type shader
,
1870 unsigned start_slot
, unsigned num_sampler
,
1873 assert(start_slot
== 0);
1875 struct panfrost_context
*ctx
= pan_context(pctx
);
1877 /* XXX: Should upload, not just copy? */
1878 ctx
->sampler_count
[shader
] = num_sampler
;
1879 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1881 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1885 panfrost_variant_matches(
1886 struct panfrost_context
*ctx
,
1887 struct panfrost_shader_state
*variant
,
1888 enum pipe_shader_type type
)
1890 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1891 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1893 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1895 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1896 /* Make sure enable state is at least the same */
1897 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1901 /* Check that the contents of the test are the same */
1902 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1903 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1905 if (!(same_func
&& same_ref
)) {
1910 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1911 variant
->point_sprite_mask
)) {
1912 /* Ensure the same varyings are turned to point sprites */
1913 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1916 /* Ensure the orientation is correct */
1918 rasterizer
->sprite_coord_mode
==
1919 PIPE_SPRITE_COORD_UPPER_LEFT
;
1921 if (variant
->point_sprite_upper_left
!= upper_left
)
1925 /* Otherwise, we're good to go */
1930 * Fix an uncompiled shader's stream output info, and produce a bitmask
1931 * of which VARYING_SLOT_* are captured for stream output.
1933 * Core Gallium stores output->register_index as a "slot" number, where
1934 * slots are assigned consecutively to all outputs in info->outputs_written.
1935 * This naive packing of outputs doesn't work for us - we too have slots,
1936 * but the layout is defined by the VUE map, which we won't have until we
1937 * compile a specific shader variant. So, we remap these and simply store
1938 * VARYING_SLOT_* in our copy's output->register_index fields.
1940 * We then produce a bitmask of outputs which are used for SO.
1942 * Implementation from iris.
1946 update_so_info(struct pipe_stream_output_info
*so_info
,
1947 uint64_t outputs_written
)
1949 uint64_t so_outputs
= 0;
1950 uint8_t reverse_map
[64] = {};
1953 while (outputs_written
)
1954 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1956 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1957 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1959 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1960 output
->register_index
= reverse_map
[output
->register_index
];
1962 so_outputs
|= 1ull << output
->register_index
;
1969 panfrost_bind_shader_state(
1970 struct pipe_context
*pctx
,
1972 enum pipe_shader_type type
)
1974 struct panfrost_context
*ctx
= pan_context(pctx
);
1976 ctx
->shader
[type
] = hwcso
;
1978 if (type
== PIPE_SHADER_FRAGMENT
)
1979 ctx
->dirty
|= PAN_DIRTY_FS
;
1981 ctx
->dirty
|= PAN_DIRTY_VS
;
1985 /* Match the appropriate variant */
1987 signed variant
= -1;
1988 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1990 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1991 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1997 if (variant
== -1) {
1998 /* No variant matched, so create a new one */
1999 variant
= variants
->variant_count
++;
2000 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2002 struct panfrost_shader_state
*v
=
2003 &variants
->variants
[variant
];
2005 if (type
== PIPE_SHADER_FRAGMENT
) {
2006 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
2008 if (ctx
->rasterizer
) {
2009 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
2010 v
->point_sprite_upper_left
=
2011 ctx
->rasterizer
->base
.sprite_coord_mode
==
2012 PIPE_SPRITE_COORD_UPPER_LEFT
;
2016 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
2020 /* Select this variant */
2021 variants
->active_variant
= variant
;
2023 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2024 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2026 /* We finally have a variant, so compile it */
2028 if (!shader_state
->compiled
) {
2029 uint64_t outputs_written
= 0;
2031 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
2032 variants
->base
.type
,
2033 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
2034 variants
->base
.ir
.nir
:
2035 variants
->base
.tokens
,
2036 tgsi_processor_to_shader_stage(type
), shader_state
,
2039 shader_state
->compiled
= true;
2041 /* Fixup the stream out information, since what Gallium returns
2042 * normally is mildly insane */
2044 shader_state
->stream_output
= variants
->base
.stream_output
;
2045 shader_state
->so_mask
=
2046 update_so_info(&shader_state
->stream_output
, outputs_written
);
2051 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2053 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2057 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2059 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2063 panfrost_set_vertex_buffers(
2064 struct pipe_context
*pctx
,
2065 unsigned start_slot
,
2066 unsigned num_buffers
,
2067 const struct pipe_vertex_buffer
*buffers
)
2069 struct panfrost_context
*ctx
= pan_context(pctx
);
2071 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2075 panfrost_set_constant_buffer(
2076 struct pipe_context
*pctx
,
2077 enum pipe_shader_type shader
, uint index
,
2078 const struct pipe_constant_buffer
*buf
)
2080 struct panfrost_context
*ctx
= pan_context(pctx
);
2081 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2083 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2085 unsigned mask
= (1 << index
);
2087 if (unlikely(!buf
)) {
2088 pbuf
->enabled_mask
&= ~mask
;
2089 pbuf
->dirty_mask
&= ~mask
;
2093 pbuf
->enabled_mask
|= mask
;
2094 pbuf
->dirty_mask
|= mask
;
2098 panfrost_set_stencil_ref(
2099 struct pipe_context
*pctx
,
2100 const struct pipe_stencil_ref
*ref
)
2102 struct panfrost_context
*ctx
= pan_context(pctx
);
2103 ctx
->stencil_ref
= *ref
;
2105 /* Shader core dirty */
2106 ctx
->dirty
|= PAN_DIRTY_FS
;
2109 static enum mali_texture_type
2110 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2114 case PIPE_TEXTURE_1D
:
2115 case PIPE_TEXTURE_1D_ARRAY
:
2118 case PIPE_TEXTURE_2D
:
2119 case PIPE_TEXTURE_2D_ARRAY
:
2120 case PIPE_TEXTURE_RECT
:
2123 case PIPE_TEXTURE_3D
:
2126 case PIPE_TEXTURE_CUBE
:
2127 case PIPE_TEXTURE_CUBE_ARRAY
:
2128 return MALI_TEX_CUBE
;
2131 unreachable("Unknown target");
2135 static struct pipe_sampler_view
*
2136 panfrost_create_sampler_view(
2137 struct pipe_context
*pctx
,
2138 struct pipe_resource
*texture
,
2139 const struct pipe_sampler_view
*template)
2141 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2142 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2144 pipe_reference(NULL
, &texture
->reference
);
2146 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2149 so
->base
= *template;
2150 so
->base
.texture
= texture
;
2151 so
->base
.reference
.count
= 1;
2152 so
->base
.context
= pctx
;
2154 /* sampler_views correspond to texture descriptors, minus the texture
2155 * (data) itself. So, we serialise the descriptor here and cache it for
2158 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2160 unsigned char user_swizzle
[4] = {
2161 template->swizzle_r
,
2162 template->swizzle_g
,
2163 template->swizzle_b
,
2167 enum mali_format format
= panfrost_find_format(desc
);
2169 /* Check if we need to set a custom stride by computing the "expected"
2170 * stride and comparing it to what the BO actually wants. Only applies
2171 * to linear textures, since tiled/compressed textures have strict
2172 * alignment requirements for their strides as it is */
2174 unsigned first_level
= template->u
.tex
.first_level
;
2175 unsigned last_level
= template->u
.tex
.last_level
;
2177 if (prsrc
->layout
== PAN_LINEAR
) {
2178 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2179 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2180 unsigned width
= u_minify(texture
->width0
, l
);
2181 unsigned comp_stride
= width
* bytes_per_pixel
;
2183 if (comp_stride
!= actual_stride
) {
2184 so
->manual_stride
= true;
2190 /* In the hardware, array_size refers specifically to array textures,
2191 * whereas in Gallium, it also covers cubemaps */
2193 unsigned array_size
= texture
->array_size
;
2195 if (template->target
== PIPE_TEXTURE_CUBE
) {
2196 /* TODO: Cubemap arrays */
2197 assert(array_size
== 6);
2201 struct mali_texture_descriptor texture_descriptor
= {
2202 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2203 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2204 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2205 .array_size
= MALI_POSITIVE(array_size
),
2208 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2210 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2211 .type
= panfrost_translate_texture_type(template->target
),
2215 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2218 texture_descriptor
.levels
= last_level
- first_level
;
2220 so
->hw
= texture_descriptor
;
2222 return (struct pipe_sampler_view
*) so
;
2226 panfrost_set_sampler_views(
2227 struct pipe_context
*pctx
,
2228 enum pipe_shader_type shader
,
2229 unsigned start_slot
, unsigned num_views
,
2230 struct pipe_sampler_view
**views
)
2232 struct panfrost_context
*ctx
= pan_context(pctx
);
2234 assert(start_slot
== 0);
2236 unsigned new_nr
= 0;
2237 for (unsigned i
= 0; i
< num_views
; ++i
) {
2242 ctx
->sampler_view_count
[shader
] = new_nr
;
2243 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2245 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2249 panfrost_sampler_view_destroy(
2250 struct pipe_context
*pctx
,
2251 struct pipe_sampler_view
*view
)
2253 pipe_resource_reference(&view
->texture
, NULL
);
2258 panfrost_set_shader_buffers(
2259 struct pipe_context
*pctx
,
2260 enum pipe_shader_type shader
,
2261 unsigned start
, unsigned count
,
2262 const struct pipe_shader_buffer
*buffers
,
2263 unsigned writable_bitmask
)
2265 struct panfrost_context
*ctx
= pan_context(pctx
);
2267 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2268 buffers
, start
, count
);
2271 /* Hints that a framebuffer should use AFBC where possible */
2275 struct panfrost_screen
*screen
,
2276 const struct pipe_framebuffer_state
*fb
)
2278 /* AFBC implemenation incomplete; hide it */
2279 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2281 /* Hint AFBC to the resources bound to each color buffer */
2283 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2284 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2285 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2286 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2289 /* Also hint it to the depth buffer */
2292 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2293 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2298 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2299 const struct pipe_framebuffer_state
*fb
)
2301 struct panfrost_context
*ctx
= pan_context(pctx
);
2303 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
2304 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2306 panfrost_invalidate_frame(ctx
);
2310 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2311 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2313 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2317 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2320 struct panfrost_context
*ctx
= pan_context(pipe
);
2321 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2322 ctx
->depth_stencil
= depth_stencil
;
2327 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2328 * emulated in the fragment shader */
2330 if (depth_stencil
->alpha
.enabled
) {
2331 /* We need to trigger a new shader (maybe) */
2332 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2336 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2338 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2339 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2341 /* If back-stencil is not enabled, use the front values */
2342 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2343 unsigned back_index
= back_enab
? 1 : 0;
2345 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2346 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2348 /* Depth state (TODO: Refactor) */
2349 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2351 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2353 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2354 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2356 /* Bounds test not implemented */
2357 assert(!depth_stencil
->depth
.bounds_test
);
2359 ctx
->dirty
|= PAN_DIRTY_FS
;
2363 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2369 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2370 unsigned sample_mask
)
2375 panfrost_set_clip_state(struct pipe_context
*pipe
,
2376 const struct pipe_clip_state
*clip
)
2378 //struct panfrost_context *panfrost = pan_context(pipe);
2382 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2383 unsigned start_slot
,
2384 unsigned num_viewports
,
2385 const struct pipe_viewport_state
*viewports
)
2387 struct panfrost_context
*ctx
= pan_context(pipe
);
2389 assert(start_slot
== 0);
2390 assert(num_viewports
== 1);
2392 ctx
->pipe_viewport
= *viewports
;
2396 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2397 unsigned start_slot
,
2398 unsigned num_scissors
,
2399 const struct pipe_scissor_state
*scissors
)
2401 struct panfrost_context
*ctx
= pan_context(pipe
);
2403 assert(start_slot
== 0);
2404 assert(num_scissors
== 1);
2406 ctx
->scissor
= *scissors
;
2410 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2411 const struct pipe_poly_stipple
*stipple
)
2413 //struct panfrost_context *panfrost = pan_context(pipe);
2417 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2420 struct panfrost_context
*ctx
= pan_context(pipe
);
2421 ctx
->active_queries
= enable
;
2425 panfrost_destroy(struct pipe_context
*pipe
)
2427 struct panfrost_context
*panfrost
= pan_context(pipe
);
2429 if (panfrost
->blitter
)
2430 util_blitter_destroy(panfrost
->blitter
);
2432 if (panfrost
->blitter_wallpaper
)
2433 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2438 static struct pipe_query
*
2439 panfrost_create_query(struct pipe_context
*pipe
,
2443 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2448 return (struct pipe_query
*) q
;
2452 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2458 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2460 struct panfrost_context
*ctx
= pan_context(pipe
);
2461 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2462 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
2464 switch (query
->type
) {
2465 case PIPE_QUERY_OCCLUSION_COUNTER
:
2466 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2467 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2468 /* Allocate a word for the query results to be stored */
2469 query
->transfer
= panfrost_allocate_transient(batch
, sizeof(unsigned));
2470 ctx
->occlusion_query
= query
;
2473 /* Geometry statistics are computed in the driver. XXX: geom/tess
2476 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2477 query
->start
= ctx
->prims_generated
;
2479 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2480 query
->start
= ctx
->tf_prims_generated
;
2484 fprintf(stderr
, "Skipping query %u\n", query
->type
);
2492 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2494 struct panfrost_context
*ctx
= pan_context(pipe
);
2495 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2497 switch (query
->type
) {
2498 case PIPE_QUERY_OCCLUSION_COUNTER
:
2499 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2500 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2501 ctx
->occlusion_query
= NULL
;
2503 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2504 query
->end
= ctx
->prims_generated
;
2506 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2507 query
->end
= ctx
->tf_prims_generated
;
2515 panfrost_get_query_result(struct pipe_context
*pipe
,
2516 struct pipe_query
*q
,
2518 union pipe_query_result
*vresult
)
2520 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2521 struct panfrost_context
*ctx
= pan_context(pipe
);
2524 switch (query
->type
) {
2525 case PIPE_QUERY_OCCLUSION_COUNTER
:
2526 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2527 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2529 panfrost_flush_all_batches(ctx
, true);
2531 /* Read back the query results */
2532 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2533 unsigned passed
= *result
;
2535 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2536 vresult
->u64
= passed
;
2538 vresult
->b
= !!passed
;
2543 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2544 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2545 panfrost_flush_all_batches(ctx
, true);
2546 vresult
->u64
= query
->end
- query
->start
;
2550 DBG("Skipped query get %u\n", query
->type
);
2557 static struct pipe_stream_output_target
*
2558 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2559 struct pipe_resource
*prsc
,
2560 unsigned buffer_offset
,
2561 unsigned buffer_size
)
2563 struct pipe_stream_output_target
*target
;
2565 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2570 pipe_reference_init(&target
->reference
, 1);
2571 pipe_resource_reference(&target
->buffer
, prsc
);
2573 target
->context
= pctx
;
2574 target
->buffer_offset
= buffer_offset
;
2575 target
->buffer_size
= buffer_size
;
2581 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2582 struct pipe_stream_output_target
*target
)
2584 pipe_resource_reference(&target
->buffer
, NULL
);
2585 ralloc_free(target
);
2589 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2590 unsigned num_targets
,
2591 struct pipe_stream_output_target
**targets
,
2592 const unsigned *offsets
)
2594 struct panfrost_context
*ctx
= pan_context(pctx
);
2595 struct panfrost_streamout
*so
= &ctx
->streamout
;
2597 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2599 for (unsigned i
= 0; i
< num_targets
; i
++) {
2600 if (offsets
[i
] != -1)
2601 so
->offsets
[i
] = offsets
[i
];
2603 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2606 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2607 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2609 so
->num_targets
= num_targets
;
2612 struct pipe_context
*
2613 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2615 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2616 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2617 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2619 ctx
->is_t6xx
= pscreen
->gpu_id
< 0x0700; /* Literally, "earlier than T700" */
2621 gallium
->screen
= screen
;
2623 gallium
->destroy
= panfrost_destroy
;
2625 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2627 gallium
->flush
= panfrost_flush
;
2628 gallium
->clear
= panfrost_clear
;
2629 gallium
->draw_vbo
= panfrost_draw_vbo
;
2631 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2632 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2633 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2635 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2637 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2638 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2639 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2641 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2642 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2643 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2645 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2646 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2647 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2649 gallium
->create_fs_state
= panfrost_create_shader_state
;
2650 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2651 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2653 gallium
->create_vs_state
= panfrost_create_shader_state
;
2654 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2655 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2657 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2658 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2659 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2661 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2662 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2663 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2665 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2667 gallium
->set_clip_state
= panfrost_set_clip_state
;
2668 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2669 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2670 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2671 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2673 gallium
->create_query
= panfrost_create_query
;
2674 gallium
->destroy_query
= panfrost_destroy_query
;
2675 gallium
->begin_query
= panfrost_begin_query
;
2676 gallium
->end_query
= panfrost_end_query
;
2677 gallium
->get_query_result
= panfrost_get_query_result
;
2679 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2680 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2681 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2683 panfrost_resource_context_init(gallium
);
2684 panfrost_blend_context_init(gallium
);
2685 panfrost_compute_context_init(gallium
);
2688 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2689 gallium
->const_uploader
= gallium
->stream_uploader
;
2690 assert(gallium
->stream_uploader
);
2692 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2693 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2695 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2697 ctx
->blitter
= util_blitter_create(gallium
);
2698 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2700 assert(ctx
->blitter
);
2701 assert(ctx
->blitter_wallpaper
);
2703 /* Prepare for render! */
2705 panfrost_batch_init(ctx
);
2706 panfrost_emit_vertex_payload(ctx
);
2707 panfrost_emit_tiler_payload(ctx
);
2708 panfrost_invalidate_frame(ctx
);
2709 panfrost_default_shader_backend(ctx
);