2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_format.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
55 #include "pandecode/decode.h"
57 struct midgard_tiler_descriptor
58 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
60 struct panfrost_screen
*screen
= pan_screen(batch
->ctx
->base
.screen
);
61 bool hierarchy
= !(screen
->quirks
& MIDGARD_NO_HIER_TILING
);
62 struct midgard_tiler_descriptor t
= {0};
63 unsigned height
= batch
->key
.height
;
64 unsigned width
= batch
->key
.width
;
67 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
69 /* Compute the polygon header size and use that to offset the body */
71 unsigned header_size
= panfrost_tiler_header_size(
72 width
, height
, t
.hierarchy_mask
, hierarchy
);
74 t
.polygon_list_size
= panfrost_tiler_full_size(
75 width
, height
, t
.hierarchy_mask
, hierarchy
);
80 struct panfrost_bo
*tiler_heap
;
82 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
83 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
88 /* Allow the entire tiler heap */
89 t
.heap_start
= tiler_heap
->gpu
;
90 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
92 struct panfrost_bo
*tiler_dummy
;
94 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
95 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
97 /* The tiler is disabled, so don't allow the tiler heap */
98 t
.heap_start
= tiler_dummy
->gpu
;
99 t
.heap_end
= t
.heap_start
;
101 /* Use a dummy polygon list */
102 t
.polygon_list
= tiler_dummy
->gpu
;
104 /* Disable the tiler */
106 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
108 t
.hierarchy_mask
= MALI_TILER_USER
;
109 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
111 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
112 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
113 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
117 t
.polygon_list_body
=
118 t
.polygon_list
+ header_size
;
125 struct pipe_context
*pipe
,
127 const union pipe_color_union
*color
,
128 double depth
, unsigned stencil
)
130 struct panfrost_context
*ctx
= pan_context(pipe
);
132 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
133 * the existing batch targeting this FBO has draws. We could probably
134 * avoid that by replacing plain clears by quad-draws with a specific
135 * color/depth/stencil value, thus avoiding the generation of extra
138 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
140 panfrost_batch_add_fbo_bos(batch
);
141 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
144 /* TODO: Bifrost requires just a mali_shared_memory, without the rest of the
148 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
150 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
151 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
153 /* If we haven't, reserve space for the framebuffer */
155 if (!batch
->framebuffer
.gpu
) {
156 unsigned size
= (screen
->quirks
& MIDGARD_SFBD
) ?
157 sizeof(struct mali_single_framebuffer
) :
158 sizeof(struct mali_framebuffer
);
160 batch
->framebuffer
= panfrost_allocate_transient(batch
, size
);
162 /* Tag the pointer */
163 if (!(screen
->quirks
& MIDGARD_SFBD
))
164 batch
->framebuffer
.gpu
|= MALI_MFBD
;
167 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
168 ctx
->payloads
[i
].postfix
.shared_memory
= batch
->framebuffer
.gpu
;
171 /* Reset per-frame context, called on context initialisation as well as after
172 * flushing a frame */
175 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
177 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
178 ctx
->payloads
[i
].postfix
.shared_memory
= 0;
180 /* TODO: When does this need to be handled? */
181 ctx
->active_queries
= true;
184 /* In practice, every field of these payloads should be configurable
185 * arbitrarily, which means these functions are basically catch-all's for
186 * as-of-yet unwavering unknowns */
189 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
191 /* 0x2 bit clear on 32-bit T6XX */
193 struct midgard_payload_vertex_tiler payload
= {
194 .gl_enables
= 0x4 | 0x2,
197 /* Vertex and compute are closely coupled, so share a payload */
199 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
200 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
204 translate_tex_wrap(enum pipe_tex_wrap w
)
207 case PIPE_TEX_WRAP_REPEAT
:
208 return MALI_WRAP_REPEAT
;
210 case PIPE_TEX_WRAP_CLAMP
:
211 return MALI_WRAP_CLAMP
;
213 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
214 return MALI_WRAP_CLAMP_TO_EDGE
;
216 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
217 return MALI_WRAP_CLAMP_TO_BORDER
;
219 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
220 return MALI_WRAP_MIRRORED_REPEAT
;
222 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
223 return MALI_WRAP_MIRRORED_CLAMP
;
225 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
226 return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE
;
228 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
229 return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER
;
232 unreachable("Invalid wrap");
237 panfrost_translate_compare_func(enum pipe_compare_func in
)
240 case PIPE_FUNC_NEVER
:
241 return MALI_FUNC_NEVER
;
244 return MALI_FUNC_LESS
;
246 case PIPE_FUNC_EQUAL
:
247 return MALI_FUNC_EQUAL
;
249 case PIPE_FUNC_LEQUAL
:
250 return MALI_FUNC_LEQUAL
;
252 case PIPE_FUNC_GREATER
:
253 return MALI_FUNC_GREATER
;
255 case PIPE_FUNC_NOTEQUAL
:
256 return MALI_FUNC_NOTEQUAL
;
258 case PIPE_FUNC_GEQUAL
:
259 return MALI_FUNC_GEQUAL
;
261 case PIPE_FUNC_ALWAYS
:
262 return MALI_FUNC_ALWAYS
;
265 unreachable("Invalid func");
270 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
273 case PIPE_STENCIL_OP_KEEP
:
274 return MALI_STENCIL_KEEP
;
276 case PIPE_STENCIL_OP_ZERO
:
277 return MALI_STENCIL_ZERO
;
279 case PIPE_STENCIL_OP_REPLACE
:
280 return MALI_STENCIL_REPLACE
;
282 case PIPE_STENCIL_OP_INCR
:
283 return MALI_STENCIL_INCR
;
285 case PIPE_STENCIL_OP_DECR
:
286 return MALI_STENCIL_DECR
;
288 case PIPE_STENCIL_OP_INCR_WRAP
:
289 return MALI_STENCIL_INCR_WRAP
;
291 case PIPE_STENCIL_OP_DECR_WRAP
:
292 return MALI_STENCIL_DECR_WRAP
;
294 case PIPE_STENCIL_OP_INVERT
:
295 return MALI_STENCIL_INVERT
;
298 unreachable("Invalid stencil op");
303 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
305 out
->ref
= 0; /* Gallium gets it from elsewhere */
307 out
->mask
= in
->valuemask
;
308 out
->func
= panfrost_translate_compare_func(in
->func
);
309 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
310 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
311 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
315 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
317 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
318 struct mali_shader_meta shader
= {
319 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
321 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
322 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
325 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this is
326 * required (independent of 32-bit/64-bit descriptors), or why it's not
327 * used on later GPU revisions. Otherwise, all shader jobs fault on
328 * these earlier chips (perhaps this is a chicken bit of some kind).
329 * More investigation is needed. */
331 if (screen
->quirks
& MIDGARD_SFBD
)
332 shader
.unknown2_4
|= 0x10;
334 struct pipe_stencil_state default_stencil
= {
336 .func
= PIPE_FUNC_ALWAYS
,
337 .fail_op
= MALI_STENCIL_KEEP
,
338 .zfail_op
= MALI_STENCIL_KEEP
,
339 .zpass_op
= MALI_STENCIL_KEEP
,
344 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
345 shader
.stencil_mask_front
= default_stencil
.writemask
;
347 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
348 shader
.stencil_mask_back
= default_stencil
.writemask
;
350 if (default_stencil
.enabled
)
351 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
353 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
357 panfrost_writes_point_size(struct panfrost_context
*ctx
)
359 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
360 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
362 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
365 /* Stage the attribute descriptors so we can adjust src_offset
366 * to let BOs align nicely */
369 panfrost_stage_attributes(struct panfrost_context
*ctx
)
371 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
372 struct panfrost_vertex_state
*so
= ctx
->vertex
;
374 size_t sz
= sizeof(struct mali_attr_meta
) * PAN_MAX_ATTRIBUTE
;
375 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
376 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
378 /* Copy as-is for the first pass */
379 memcpy(target
, so
->hw
, sz
);
381 /* Fixup offsets for the second pass. Recall that the hardware
382 * calculates attribute addresses as:
384 * addr = base + (stride * vtx) + src_offset;
386 * However, on Mali, base must be aligned to 64-bytes, so we
389 * base' = base & ~63 = base - (base & 63)
391 * To compensate when using base' (see emit_vertex_data), we have
392 * to adjust src_offset by the masked off piece:
394 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
395 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
396 * = base + (stride * vtx) + src_offset
402 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
404 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
405 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
406 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
407 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
408 mali_ptr addr
= rsrc
->bo
->gpu
+ buf
->buffer_offset
;
410 /* Adjust by the masked off bits of the offset. Make sure we
411 * read src_offset from so->hw (which is not GPU visible)
412 * rather than target (which is) due to caching effects */
414 unsigned src_offset
= so
->hw
[i
].src_offset
;
415 src_offset
+= (addr
& 63);
417 /* Also, somewhat obscurely per-instance data needs to be
418 * offset in response to a delayed start in an indexed draw */
420 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
421 src_offset
-= buf
->stride
* start
;
423 target
[i
].src_offset
= src_offset
;
426 /* Let's also include vertex builtins */
428 struct mali_attr_meta builtin
= {
429 .format
= MALI_R32UI
,
430 .swizzle
= panfrost_get_default_swizzle(1)
433 /* See mali_attr_meta specification for the magic number */
434 memcpy(&target
[PAN_VERTEX_ID
], &builtin
, 4);
435 memcpy(&target
[PAN_INSTANCE_ID
], &builtin
, 4);
437 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
441 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
443 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
444 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
446 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
449 if (ctx
->sampler_count
[t
]) {
450 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
452 struct panfrost_transfer transfer
=
453 panfrost_allocate_transient(batch
, transfer_size
);
455 struct mali_sampler_descriptor
*desc
=
456 (struct mali_sampler_descriptor
*) transfer
.cpu
;
458 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
459 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
461 upload
= transfer
.gpu
;
464 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
470 struct panfrost_context
*ctx
,
471 enum pipe_shader_type st
,
472 struct panfrost_sampler_view
*view
)
477 struct pipe_sampler_view
*pview
= &view
->base
;
478 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
479 mali_ptr descriptor_gpu
;
482 /* Do we interleave an explicit stride with every element? */
484 bool has_manual_stride
= view
->manual_stride
;
486 /* For easy access */
488 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
489 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
490 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
491 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
492 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
493 unsigned first_face
= 0;
494 unsigned last_face
= 0;
495 unsigned face_mult
= 1;
497 /* Cubemaps have 6 faces as layers in between each actual layer.
498 * There's a bit of an impedence mismatch between Gallium and the
499 * hardware, let's fixup for it */
501 if (pview
->target
== PIPE_TEXTURE_CUBE
|| pview
->target
== PIPE_TEXTURE_CUBE_ARRAY
) {
502 /* TODO: logic wrong in the asserted out cases ... can they happen? */
504 first_face
= first_layer
% 6;
505 last_face
= last_layer
% 6;
509 assert((first_layer
== last_layer
) || (first_face
== 0 && last_face
== 5));
513 /* Lower-bit is set when sampling from colour AFBC */
514 bool is_afbc
= rsrc
->layout
== MALI_TEXTURE_AFBC
;
515 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
516 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
518 /* Add the BO to the job so it's retained until the job is done. */
519 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
520 panfrost_batch_add_bo(batch
, rsrc
->bo
,
521 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
522 panfrost_bo_access_for_stage(st
));
524 /* Add the usage flags in, since they can change across the CSO
525 * lifetime due to layout switches */
527 view
->hw
.format
.layout
= rsrc
->layout
;
528 view
->hw
.format
.manual_stride
= has_manual_stride
;
530 /* Inject the addresses in, interleaving array indices, mip levels,
531 * cube faces, and strides in that order */
534 unsigned levels
= 1 + last_level
- first_level
;
535 unsigned layers
= 1 + last_layer
- first_layer
;
536 unsigned faces
= 1 + last_face
- first_face
;
537 unsigned num_elements
= levels
* layers
* faces
;
538 if (has_manual_stride
)
541 descriptor
= malloc(sizeof(struct mali_texture_descriptor
) +
542 sizeof(mali_ptr
) * num_elements
);
543 memcpy(descriptor
, &view
->hw
, sizeof(struct mali_texture_descriptor
));
545 mali_ptr
*pointers_and_strides
= descriptor
+
546 sizeof(struct mali_texture_descriptor
);
548 for (unsigned w
= first_layer
; w
<= last_layer
; ++w
) {
549 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
550 for (unsigned f
= first_face
; f
<= last_face
; ++f
) {
551 pointers_and_strides
[idx
++] =
552 panfrost_get_texture_address(rsrc
, l
, w
* face_mult
+ f
)
553 + afbc_bit
+ view
->astc_stretch
;
554 if (has_manual_stride
) {
555 pointers_and_strides
[idx
++] =
556 rsrc
->slices
[l
].stride
;
562 descriptor_gpu
= panfrost_upload_transient(batch
, descriptor
,
563 sizeof(struct mali_texture_descriptor
) +
564 num_elements
* sizeof(*pointers_and_strides
));
567 return descriptor_gpu
;
571 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
573 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
575 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
576 mali_ptr trampoline
= 0;
578 if (ctx
->sampler_view_count
[t
]) {
579 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
581 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
583 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
585 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
588 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
592 struct sysval_uniform
{
601 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
602 struct sysval_uniform
*uniform
)
604 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
606 uniform
->f
[0] = vp
->scale
[0];
607 uniform
->f
[1] = vp
->scale
[1];
608 uniform
->f
[2] = vp
->scale
[2];
611 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
612 struct sysval_uniform
*uniform
)
614 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
616 uniform
->f
[0] = vp
->translate
[0];
617 uniform
->f
[1] = vp
->translate
[1];
618 uniform
->f
[2] = vp
->translate
[2];
621 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
622 enum pipe_shader_type st
,
623 unsigned int sysvalid
,
624 struct sysval_uniform
*uniform
)
626 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
627 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
628 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
629 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
632 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
635 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
636 tex
->u
.tex
.first_level
);
639 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
640 tex
->u
.tex
.first_level
);
643 uniform
->i
[dim
] = tex
->texture
->array_size
;
646 static void panfrost_upload_ssbo_sysval(
647 struct panfrost_context
*ctx
,
648 enum pipe_shader_type st
,
650 struct sysval_uniform
*uniform
)
652 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
653 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
655 /* Compute address */
656 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
657 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
659 panfrost_batch_add_bo(batch
, bo
,
660 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
661 panfrost_bo_access_for_stage(st
));
663 /* Upload address and size as sysval */
664 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
665 uniform
->u
[2] = sb
.buffer_size
;
669 panfrost_upload_sampler_sysval(
670 struct panfrost_context
*ctx
,
671 enum pipe_shader_type st
,
672 unsigned sampler_index
,
673 struct sysval_uniform
*uniform
)
675 struct pipe_sampler_state
*sampl
=
676 &ctx
->samplers
[st
][sampler_index
]->base
;
678 uniform
->f
[0] = sampl
->min_lod
;
679 uniform
->f
[1] = sampl
->max_lod
;
680 uniform
->f
[2] = sampl
->lod_bias
;
682 /* Even without any errata, Midgard represents "no mipmapping" as
683 * fixing the LOD with the clamps; keep behaviour consistent. c.f.
684 * panfrost_create_sampler_state which also explains our choice of
685 * epsilon value (again to keep behaviour consistent) */
687 if (sampl
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
688 uniform
->f
[1] = uniform
->f
[0] + (1.0/256.0);
691 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
692 struct sysval_uniform
*uniform
)
694 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
695 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
696 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
699 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
700 struct panfrost_shader_state
*ss
,
701 enum pipe_shader_type st
)
703 struct sysval_uniform
*uniforms
= (void *)buf
;
705 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
706 int sysval
= ss
->sysval
[i
];
708 switch (PAN_SYSVAL_TYPE(sysval
)) {
709 case PAN_SYSVAL_VIEWPORT_SCALE
:
710 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
712 case PAN_SYSVAL_VIEWPORT_OFFSET
:
713 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
715 case PAN_SYSVAL_TEXTURE_SIZE
:
716 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
719 case PAN_SYSVAL_SSBO
:
720 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
723 case PAN_SYSVAL_NUM_WORK_GROUPS
:
724 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
726 case PAN_SYSVAL_SAMPLER
:
727 panfrost_upload_sampler_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
737 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
739 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
740 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
743 return rsrc
->bo
->cpu
;
744 else if (cb
->user_buffer
)
745 return cb
->user_buffer
;
747 unreachable("No constant buffer");
751 panfrost_map_constant_buffer_gpu(
752 struct panfrost_context
*ctx
,
753 enum pipe_shader_type st
,
754 struct panfrost_constant_buffer
*buf
,
757 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
758 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
759 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
762 panfrost_batch_add_bo(batch
, rsrc
->bo
,
763 PAN_BO_ACCESS_SHARED
|
765 panfrost_bo_access_for_stage(st
));
767 /* Alignment gauranteed by PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */
768 return rsrc
->bo
->gpu
+ cb
->buffer_offset
;
769 } else if (cb
->user_buffer
) {
770 return panfrost_upload_transient(batch
, cb
->user_buffer
+ cb
->buffer_offset
, cb
->buffer_size
);
772 unreachable("No constant buffer");
776 /* Compute number of UBOs active (more specifically, compute the highest UBO
777 * number addressable -- if there are gaps, include them in the count anyway).
778 * We always include UBO #0 in the count, since we *need* uniforms enabled for
782 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
784 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
785 return 32 - __builtin_clz(mask
);
788 /* Fixes up a shader state with current state */
791 panfrost_patch_shader_state(struct panfrost_context
*ctx
,
792 enum pipe_shader_type stage
)
794 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
797 ctx
->payloads
[stage
].postfix
.shader
= 0;
801 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
803 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
804 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
806 ss
->tripipe
->midgard1
.flags_lo
= 0x220;
808 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
809 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
811 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
813 /* Add the shader BO to the batch. */
814 panfrost_batch_add_bo(batch
, ss
->bo
,
815 PAN_BO_ACCESS_PRIVATE
|
817 panfrost_bo_access_for_stage(stage
));
819 ctx
->payloads
[stage
].postfix
.shader
= panfrost_upload_transient(batch
,
821 sizeof(struct mali_shader_meta
));
824 /* Go through dirty flags and actualise them in the cmdstream. */
827 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
829 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
830 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
832 panfrost_batch_add_fbo_bos(batch
);
833 panfrost_attach_vt_framebuffer(ctx
);
835 if (with_vertex_data
) {
836 panfrost_emit_vertex_data(batch
);
838 /* Varyings emitted for -all- geometry */
839 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
840 panfrost_emit_varying_descriptor(ctx
, total_count
);
844 if (ctx
->rasterizer
) {
845 bool msaa
= ctx
->rasterizer
->base
.multisample
;
846 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
848 /* TODO: Sample size */
849 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
850 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
853 panfrost_batch_set_requirements(batch
);
855 if (ctx
->occlusion_query
) {
856 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
;
857 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
860 panfrost_patch_shader_state(ctx
, PIPE_SHADER_VERTEX
);
861 panfrost_patch_shader_state(ctx
, PIPE_SHADER_COMPUTE
);
863 if (ctx
->shader
[PIPE_SHADER_VERTEX
] && ctx
->shader
[PIPE_SHADER_FRAGMENT
]) {
864 /* Check if we need to link the gl_PointSize varying */
865 if (!panfrost_writes_point_size(ctx
)) {
866 /* If the size is constant, write it out. Otherwise,
867 * don't touch primitive_size (since we would clobber
868 * the pointer there) */
870 bool points
= ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
872 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= points
?
873 ctx
->rasterizer
->base
.point_size
:
874 ctx
->rasterizer
->base
.line_width
;
878 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
]) {
879 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
881 panfrost_patch_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
883 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
886 COPY(attribute_count
);
890 COPY(midgard1
.uniform_count
);
891 COPY(midgard1
.uniform_buffer_count
);
892 COPY(midgard1
.work_count
);
893 COPY(midgard1
.flags_lo
);
894 COPY(midgard1
.flags_hi
);
898 /* Get blending setup */
899 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
901 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
902 unsigned shader_offset
= 0;
903 struct panfrost_bo
*shader_bo
= NULL
;
905 for (unsigned c
= 0; c
< rt_count
; ++c
) {
906 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
, &shader_bo
, &shader_offset
);
909 /* If there is a blend shader, work registers are shared. XXX: opt */
911 for (unsigned c
= 0; c
< rt_count
; ++c
) {
912 if (blend
[c
].is_shader
)
913 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
916 /* Depending on whether it's legal to in the given shader, we
917 * try to enable early-z testing (or forward-pixel kill?) */
919 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_EARLY_Z
,
920 !variant
->can_discard
&& !variant
->writes_depth
);
922 /* Add the writes Z/S flags if needed. */
923 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
,
924 MALI_WRITES_Z
, variant
->writes_depth
);
925 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_hi
,
926 MALI_WRITES_S
, variant
->writes_stencil
);
928 /* Any time texturing is used, derivatives are implicitly
929 * calculated, so we need to enable helper invocations */
931 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_HELPER_INVOCATIONS
, variant
->helper_invocations
);
933 /* Assign the stencil refs late */
935 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
936 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
937 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
939 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
940 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
942 /* CAN_DISCARD should be set if the fragment shader possibly
943 * contains a 'discard' instruction. It is likely this is
944 * related to optimizations related to forward-pixel kill, as
945 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
946 * thing?" by Peter Harris
949 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, variant
->can_discard
);
950 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, 0x400, variant
->can_discard
);
952 /* Even on MFBD, the shader descriptor gets blend shaders. It's
953 * *also* copied to the blend_meta appended (by convention),
954 * but this is the field actually read by the hardware. (Or
955 * maybe both are read...?). Specify the last RTi with a blend
958 ctx
->fragment_shader_core
.blend
.shader
= 0;
960 for (signed rt
= (rt_count
- 1); rt
>= 0; --rt
) {
961 if (blend
[rt
].is_shader
) {
962 ctx
->fragment_shader_core
.blend
.shader
=
963 blend
[rt
].shader
.gpu
| blend
[rt
].shader
.first_tag
;
968 if (screen
->quirks
& MIDGARD_SFBD
) {
969 /* When only a single render target platform is used, the blend
970 * information is inside the shader meta itself. We
971 * additionally need to signal CAN_DISCARD for nontrivial blend
972 * modes (so we're able to read back the destination buffer) */
974 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_BLEND_SHADER
, blend
[0].is_shader
);
976 if (!blend
[0].is_shader
) {
977 ctx
->fragment_shader_core
.blend
.equation
=
978 *blend
[0].equation
.equation
;
979 ctx
->fragment_shader_core
.blend
.constant
=
980 blend
[0].equation
.constant
;
983 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, !blend
[0].no_blending
);
986 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
987 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
988 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
990 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.shader
= transfer
.gpu
;
992 if (!(screen
->quirks
& MIDGARD_SFBD
)) {
993 /* Additional blend descriptor tacked on for jobs using MFBD */
995 struct midgard_blend_rt rts
[4];
997 for (unsigned i
= 0; i
< rt_count
; ++i
) {
998 rts
[i
].flags
= 0x200;
1001 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1002 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1003 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1005 SET_BIT(rts
[i
].flags
, MALI_BLEND_MRT_SHADER
, blend
[i
].is_shader
);
1006 SET_BIT(rts
[i
].flags
, MALI_BLEND_LOAD_TIB
, !blend
[i
].no_blending
);
1007 SET_BIT(rts
[i
].flags
, MALI_BLEND_SRGB
, is_srgb
);
1008 SET_BIT(rts
[i
].flags
, MALI_BLEND_NO_DITHER
, !ctx
->blend
->base
.dither
);
1010 if (blend
[i
].is_shader
) {
1011 rts
[i
].blend
.shader
= blend
[i
].shader
.gpu
| blend
[i
].shader
.first_tag
;
1013 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1014 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1018 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1022 /* We stage to transient, so always dirty.. */
1024 panfrost_stage_attributes(ctx
);
1026 panfrost_upload_sampler_descriptors(ctx
);
1027 panfrost_upload_texture_descriptors(ctx
);
1029 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1031 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1032 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1037 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1039 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1041 /* Uniforms are implicitly UBO #0 */
1042 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1044 /* Allocate room for the sysval and the uniforms */
1045 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1046 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1047 size_t size
= sys_size
+ uniform_size
;
1048 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1050 /* Upload sysvals requested by the shader */
1051 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1053 /* Upload uniforms */
1054 if (has_uniforms
&& uniform_size
) {
1055 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1056 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1060 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1062 struct mali_vertex_tiler_postfix
*postfix
=
1063 &ctx
->payloads
[i
].postfix
;
1065 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1068 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1069 assert(ubo_count
>= 1);
1071 size_t sz
= sizeof(uint64_t) * ubo_count
;
1072 uint64_t ubos
[PAN_MAX_CONST_BUFFERS
];
1074 /* Upload uniforms as a UBO */
1075 ubos
[0] = MALI_MAKE_UBO(2 + uniform_count
, transfer
.gpu
);
1077 /* The rest are honest-to-goodness UBOs */
1079 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1080 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1082 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1083 bool empty
= usz
== 0;
1085 if (!enabled
|| empty
) {
1086 /* Stub out disabled UBOs to catch accesses */
1087 ubos
[ubo
] = MALI_MAKE_UBO(0, 0xDEAD0000);
1091 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, i
, buf
, ubo
);
1093 unsigned bytes_per_field
= 16;
1094 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1095 ubos
[ubo
] = MALI_MAKE_UBO(aligned
/ bytes_per_field
, gpu
);
1098 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1099 postfix
->uniforms
= transfer
.gpu
;
1100 postfix
->uniform_buffers
= ubufs
;
1102 buf
->dirty_mask
= 0;
1105 /* TODO: Upload the viewport somewhere more appropriate */
1107 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1108 * (somewhat) asymmetric ints. */
1109 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1111 struct mali_viewport view
= {
1112 /* By default, do no viewport clipping, i.e. clip to (-inf,
1113 * inf) in each direction. Clipping to the viewport in theory
1114 * should work, but in practice causes issues when we're not
1115 * explicitly trying to scissor */
1117 .clip_minx
= -INFINITY
,
1118 .clip_miny
= -INFINITY
,
1119 .clip_maxx
= INFINITY
,
1120 .clip_maxy
= INFINITY
,
1123 /* Always scissor to the viewport by default. */
1124 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1125 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1127 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1128 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1130 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1131 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1133 /* Apply the scissor test */
1135 unsigned minx
, miny
, maxx
, maxy
;
1137 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1138 minx
= MAX2(ss
->minx
, vp_minx
);
1139 miny
= MAX2(ss
->miny
, vp_miny
);
1140 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1141 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1149 /* Hardware needs the min/max to be strictly ordered, so flip if we
1150 * need to. The viewport transformation in the vertex shader will
1151 * handle the negatives if we don't */
1154 unsigned temp
= miny
;
1160 unsigned temp
= minx
;
1171 /* Clamp to the framebuffer size as a last check */
1173 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1174 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1176 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1177 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1179 /* Update the job, unless we're doing wallpapering (whose lack of
1180 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1181 * just... be faster :) */
1183 if (!ctx
->wallpaper_batch
)
1184 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1188 view
.viewport0
[0] = minx
;
1189 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1191 view
.viewport0
[1] = miny
;
1192 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1194 view
.clip_minz
= minz
;
1195 view
.clip_maxz
= maxz
;
1197 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1198 panfrost_upload_transient(batch
,
1200 sizeof(struct mali_viewport
));
1203 /* Corresponds to exactly one draw, but does not submit anything */
1206 panfrost_queue_draw(struct panfrost_context
*ctx
)
1208 /* Handle dirty flags now */
1209 panfrost_emit_for_draw(ctx
, true);
1211 /* If rasterizer discard is enable, only submit the vertex */
1213 bool rasterizer_discard
= ctx
->rasterizer
1214 && ctx
->rasterizer
->base
.rasterizer_discard
;
1217 struct midgard_payload_vertex_tiler
*vertex_payload
= &ctx
->payloads
[PIPE_SHADER_VERTEX
];
1218 struct midgard_payload_vertex_tiler
*tiler_payload
= &ctx
->payloads
[PIPE_SHADER_FRAGMENT
];
1220 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1221 bool wallpapering
= ctx
->wallpaper_batch
&& batch
->tiler_dep
;
1224 /* Inject in reverse order, with "predicted" job indices. THIS IS A HACK XXX */
1225 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, batch
->job_index
+ 2, tiler_payload
, sizeof(*tiler_payload
), true);
1226 panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), true);
1228 unsigned vertex
= panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), false);
1230 if (!rasterizer_discard
)
1231 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, vertex
, tiler_payload
, sizeof(*tiler_payload
), false);
1234 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1235 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1240 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1241 batch
->stack_size
= MAX2(batch
->stack_size
, ss
->stack_size
);
1245 /* The entire frame is in memory -- send it off to the kernel! */
1249 struct pipe_context
*pipe
,
1250 struct pipe_fence_handle
**fence
,
1253 struct panfrost_context
*ctx
= pan_context(pipe
);
1254 struct util_dynarray fences
;
1256 /* We must collect the fences before the flush is done, otherwise we'll
1257 * lose track of them.
1260 util_dynarray_init(&fences
, NULL
);
1261 hash_table_foreach(ctx
->batches
, hentry
) {
1262 struct panfrost_batch
*batch
= hentry
->data
;
1264 panfrost_batch_fence_reference(batch
->out_sync
);
1265 util_dynarray_append(&fences
,
1266 struct panfrost_batch_fence
*,
1271 /* Submit all pending jobs */
1272 panfrost_flush_all_batches(ctx
, false);
1275 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
1276 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1277 *fence
= (struct pipe_fence_handle
*)f
;
1279 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
1280 panfrost_batch_fence_unreference(*fence
);
1282 util_dynarray_fini(&fences
);
1285 if (pan_debug
& PAN_DBG_TRACE
)
1286 pandecode_next_frame();
1289 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1292 g2m_draw_mode(enum pipe_prim_type mode
)
1295 DEFINE_CASE(POINTS
);
1297 DEFINE_CASE(LINE_LOOP
);
1298 DEFINE_CASE(LINE_STRIP
);
1299 DEFINE_CASE(TRIANGLES
);
1300 DEFINE_CASE(TRIANGLE_STRIP
);
1301 DEFINE_CASE(TRIANGLE_FAN
);
1303 DEFINE_CASE(QUAD_STRIP
);
1304 DEFINE_CASE(POLYGON
);
1307 unreachable("Invalid draw mode");
1314 panfrost_translate_index_size(unsigned size
)
1318 return MALI_DRAW_INDEXED_UINT8
;
1321 return MALI_DRAW_INDEXED_UINT16
;
1324 return MALI_DRAW_INDEXED_UINT32
;
1327 unreachable("Invalid index size");
1331 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1332 * good for the duration of the draw (transient), could last longer */
1335 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1337 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1339 off_t offset
= info
->start
* info
->index_size
;
1340 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1342 if (!info
->has_user_indices
) {
1343 /* Only resources can be directly mapped */
1344 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1345 PAN_BO_ACCESS_SHARED
|
1346 PAN_BO_ACCESS_READ
|
1347 PAN_BO_ACCESS_VERTEX_TILER
);
1348 return rsrc
->bo
->gpu
+ offset
;
1350 /* Otherwise, we need to upload to transient memory */
1351 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1352 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1357 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1359 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1361 /* Check if we're scissoring at all */
1363 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1366 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1369 /* Count generated primitives (when there is no geom/tess shaders) for
1370 * transform feedback */
1373 panfrost_statistics_record(
1374 struct panfrost_context
*ctx
,
1375 const struct pipe_draw_info
*info
)
1377 if (!ctx
->active_queries
)
1380 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1381 ctx
->prims_generated
+= prims
;
1383 if (!ctx
->streamout
.num_targets
)
1386 ctx
->tf_prims_generated
+= prims
;
1391 struct pipe_context
*pipe
,
1392 const struct pipe_draw_info
*info
)
1394 struct panfrost_context
*ctx
= pan_context(pipe
);
1396 /* First of all, check the scissor to see if anything is drawn at all.
1397 * If it's not, we drop the draw (mostly a conformance issue;
1398 * well-behaved apps shouldn't hit this) */
1400 if (panfrost_scissor_culls_everything(ctx
))
1403 int mode
= info
->mode
;
1405 /* Fallback unsupported restart index */
1406 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1408 if (info
->primitive_restart
&& info
->index_size
1409 && info
->restart_index
!= primitive_index
) {
1410 util_draw_vbo_without_prim_restart(pipe
, info
);
1414 /* Fallback for unsupported modes */
1416 assert(ctx
->rasterizer
!= NULL
);
1418 if (!(ctx
->draw_modes
& (1 << mode
))) {
1419 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1420 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1422 if (info
->count
< 4) {
1423 /* Degenerate case? */
1427 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1428 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1433 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1434 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1436 /* Now that we have a guaranteed terminating path, find the job.
1437 * Assignment commented out to prevent unused warning */
1439 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1441 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1443 /* Take into account a negative bias */
1444 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1445 ctx
->instance_count
= info
->instance_count
;
1446 ctx
->active_prim
= info
->mode
;
1448 /* For non-indexed draws, they're the same */
1449 unsigned vertex_count
= ctx
->vertex_count
;
1451 unsigned draw_flags
= 0;
1453 /* The draw flags interpret how primitive size is interpreted */
1455 if (panfrost_writes_point_size(ctx
))
1456 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1458 if (info
->primitive_restart
)
1459 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1461 /* These doesn't make much sense */
1463 draw_flags
|= 0x3000;
1465 if (ctx
->rasterizer
&& ctx
->rasterizer
->base
.flatshade_first
)
1466 draw_flags
|= MALI_DRAW_FLATSHADE_FIRST
;
1468 panfrost_statistics_record(ctx
, info
);
1470 if (info
->index_size
) {
1471 /* Calculate the min/max index used so we can figure out how
1472 * many times to invoke the vertex shader */
1474 /* Fetch / calculate index bounds */
1475 unsigned min_index
= 0, max_index
= 0;
1477 if (info
->max_index
== ~0u) {
1478 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1480 min_index
= info
->min_index
;
1481 max_index
= info
->max_index
;
1484 /* Use the corresponding values */
1485 vertex_count
= max_index
- min_index
+ 1;
1486 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1487 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1489 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1490 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1492 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1493 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1495 /* Index count == vertex count, if no indexing is applied, as
1496 * if it is internally indexed in the expected order */
1498 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1499 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1501 /* Reverse index state */
1502 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (mali_ptr
) 0;
1505 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1506 * vertex_count, 1) */
1508 panfrost_pack_work_groups_fused(
1509 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1510 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1511 1, vertex_count
, info
->instance_count
,
1514 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1516 /* Encode the padded vertex count */
1518 if (info
->instance_count
> 1) {
1519 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
1521 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
1522 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
1524 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= shift
;
1525 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= shift
;
1527 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= k
;
1528 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= k
;
1530 ctx
->padded_count
= vertex_count
;
1532 /* Reset instancing state */
1533 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1534 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1535 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1536 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1539 /* Fire off the draw itself */
1540 panfrost_queue_draw(ctx
);
1542 /* Increment transform feedback offsets */
1544 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1545 unsigned output_count
= u_stream_outputs_for_vertices(
1546 ctx
->active_prim
, ctx
->vertex_count
);
1548 ctx
->streamout
.offsets
[i
] += output_count
;
1555 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1561 panfrost_create_rasterizer_state(
1562 struct pipe_context
*pctx
,
1563 const struct pipe_rasterizer_state
*cso
)
1565 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1569 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1570 so
->tiler_gl_enables
= 0x7;
1573 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1575 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1576 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1578 if (cso
->cull_face
& PIPE_FACE_BACK
)
1579 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1585 panfrost_bind_rasterizer_state(
1586 struct pipe_context
*pctx
,
1589 struct panfrost_context
*ctx
= pan_context(pctx
);
1591 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1595 ctx
->rasterizer
= hwcso
;
1597 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
* 2.0f
;
1598 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1600 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1601 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1603 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1605 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1606 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1608 /* Point sprites are emulated */
1610 struct panfrost_shader_state
*variant
=
1611 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1613 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1614 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1618 panfrost_create_vertex_elements_state(
1619 struct pipe_context
*pctx
,
1620 unsigned num_elements
,
1621 const struct pipe_vertex_element
*elements
)
1623 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1625 so
->num_elements
= num_elements
;
1626 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1628 for (int i
= 0; i
< num_elements
; ++i
) {
1629 so
->hw
[i
].index
= i
;
1631 enum pipe_format fmt
= elements
[i
].src_format
;
1632 const struct util_format_description
*desc
= util_format_description(fmt
);
1633 so
->hw
[i
].unknown1
= 0x2;
1634 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1636 so
->hw
[i
].format
= panfrost_find_format(desc
);
1638 /* The field itself should probably be shifted over */
1639 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1646 panfrost_bind_vertex_elements_state(
1647 struct pipe_context
*pctx
,
1650 struct panfrost_context
*ctx
= pan_context(pctx
);
1651 ctx
->vertex
= hwcso
;
1655 panfrost_create_shader_state(
1656 struct pipe_context
*pctx
,
1657 const struct pipe_shader_state
*cso
,
1658 enum pipe_shader_type stage
)
1660 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1663 /* Token deep copy to prevent memory corruption */
1665 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1666 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1668 /* Precompile for shader-db if we need to */
1669 if (unlikely((pan_debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
1670 struct panfrost_context
*ctx
= pan_context(pctx
);
1672 struct mali_shader_meta meta
;
1673 struct panfrost_shader_state state
;
1674 uint64_t outputs_written
;
1676 panfrost_shader_compile(ctx
, &meta
,
1679 tgsi_processor_to_shader_stage(stage
), &state
,
1687 panfrost_delete_shader_state(
1688 struct pipe_context
*pctx
,
1691 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1693 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1694 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1697 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1698 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1699 panfrost_bo_unreference(shader_state
->bo
);
1700 shader_state
->bo
= NULL
;
1702 free(cso
->variants
);
1708 panfrost_create_sampler_state(
1709 struct pipe_context
*pctx
,
1710 const struct pipe_sampler_state
*cso
)
1712 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1715 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1717 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1718 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1719 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1721 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1722 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1723 unsigned mip_filter
= mip_linear
?
1724 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1725 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1727 struct mali_sampler_descriptor sampler_descriptor
= {
1728 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1729 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1730 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1731 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1732 .compare_func
= panfrost_flip_compare_func(
1733 panfrost_translate_compare_func(
1734 cso
->compare_func
)),
1736 cso
->border_color
.f
[0],
1737 cso
->border_color
.f
[1],
1738 cso
->border_color
.f
[2],
1739 cso
->border_color
.f
[3]
1741 .min_lod
= FIXED_16(cso
->min_lod
, false), /* clamp at 0 */
1742 .max_lod
= FIXED_16(cso
->max_lod
, false),
1743 .lod_bias
= FIXED_16(cso
->lod_bias
, true), /* can be negative */
1744 .seamless_cube_map
= cso
->seamless_cube_map
,
1747 /* If necessary, we disable mipmapping in the sampler descriptor by
1748 * clamping the LOD as tight as possible (from 0 to epsilon,
1749 * essentially -- remember these are fixed point numbers, so
1752 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
) {
1753 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1755 /* Enforce that there is something in the middle by adding epsilon*/
1757 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1758 sampler_descriptor
.max_lod
++;
1761 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1764 so
->hw
= sampler_descriptor
;
1770 panfrost_bind_sampler_states(
1771 struct pipe_context
*pctx
,
1772 enum pipe_shader_type shader
,
1773 unsigned start_slot
, unsigned num_sampler
,
1776 assert(start_slot
== 0);
1778 struct panfrost_context
*ctx
= pan_context(pctx
);
1780 /* XXX: Should upload, not just copy? */
1781 ctx
->sampler_count
[shader
] = num_sampler
;
1782 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1786 panfrost_variant_matches(
1787 struct panfrost_context
*ctx
,
1788 struct panfrost_shader_state
*variant
,
1789 enum pipe_shader_type type
)
1791 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1792 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1794 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1796 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1797 /* Make sure enable state is at least the same */
1798 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1802 /* Check that the contents of the test are the same */
1803 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1804 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1806 if (!(same_func
&& same_ref
)) {
1811 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1812 variant
->point_sprite_mask
)) {
1813 /* Ensure the same varyings are turned to point sprites */
1814 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1817 /* Ensure the orientation is correct */
1819 rasterizer
->sprite_coord_mode
==
1820 PIPE_SPRITE_COORD_UPPER_LEFT
;
1822 if (variant
->point_sprite_upper_left
!= upper_left
)
1826 /* Otherwise, we're good to go */
1831 * Fix an uncompiled shader's stream output info, and produce a bitmask
1832 * of which VARYING_SLOT_* are captured for stream output.
1834 * Core Gallium stores output->register_index as a "slot" number, where
1835 * slots are assigned consecutively to all outputs in info->outputs_written.
1836 * This naive packing of outputs doesn't work for us - we too have slots,
1837 * but the layout is defined by the VUE map, which we won't have until we
1838 * compile a specific shader variant. So, we remap these and simply store
1839 * VARYING_SLOT_* in our copy's output->register_index fields.
1841 * We then produce a bitmask of outputs which are used for SO.
1843 * Implementation from iris.
1847 update_so_info(struct pipe_stream_output_info
*so_info
,
1848 uint64_t outputs_written
)
1850 uint64_t so_outputs
= 0;
1851 uint8_t reverse_map
[64] = {0};
1854 while (outputs_written
)
1855 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1857 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1858 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1860 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1861 output
->register_index
= reverse_map
[output
->register_index
];
1863 so_outputs
|= 1ull << output
->register_index
;
1870 panfrost_bind_shader_state(
1871 struct pipe_context
*pctx
,
1873 enum pipe_shader_type type
)
1875 struct panfrost_context
*ctx
= pan_context(pctx
);
1876 ctx
->shader
[type
] = hwcso
;
1880 /* Match the appropriate variant */
1882 signed variant
= -1;
1883 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1885 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1886 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1892 if (variant
== -1) {
1893 /* No variant matched, so create a new one */
1894 variant
= variants
->variant_count
++;
1896 if (variants
->variant_count
> variants
->variant_space
) {
1897 unsigned old_space
= variants
->variant_space
;
1899 variants
->variant_space
*= 2;
1900 if (variants
->variant_space
== 0)
1901 variants
->variant_space
= 1;
1903 /* Arbitrary limit to stop runaway programs from
1904 * creating an unbounded number of shader variants. */
1905 assert(variants
->variant_space
< 1024);
1907 unsigned msize
= sizeof(struct panfrost_shader_state
);
1908 variants
->variants
= realloc(variants
->variants
,
1909 variants
->variant_space
* msize
);
1911 memset(&variants
->variants
[old_space
], 0,
1912 (variants
->variant_space
- old_space
) * msize
);
1915 struct panfrost_shader_state
*v
=
1916 &variants
->variants
[variant
];
1918 if (type
== PIPE_SHADER_FRAGMENT
) {
1919 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1921 if (ctx
->rasterizer
) {
1922 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1923 v
->point_sprite_upper_left
=
1924 ctx
->rasterizer
->base
.sprite_coord_mode
==
1925 PIPE_SPRITE_COORD_UPPER_LEFT
;
1929 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1933 /* Select this variant */
1934 variants
->active_variant
= variant
;
1936 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1937 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1939 /* We finally have a variant, so compile it */
1941 if (!shader_state
->compiled
) {
1942 uint64_t outputs_written
= 0;
1944 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
1945 variants
->base
.type
,
1946 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
1947 variants
->base
.ir
.nir
:
1948 variants
->base
.tokens
,
1949 tgsi_processor_to_shader_stage(type
), shader_state
,
1952 shader_state
->compiled
= true;
1954 /* Fixup the stream out information, since what Gallium returns
1955 * normally is mildly insane */
1957 shader_state
->stream_output
= variants
->base
.stream_output
;
1958 shader_state
->so_mask
=
1959 update_so_info(&shader_state
->stream_output
, outputs_written
);
1964 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1966 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1970 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1972 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1976 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
1978 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1982 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
1984 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1988 panfrost_set_vertex_buffers(
1989 struct pipe_context
*pctx
,
1990 unsigned start_slot
,
1991 unsigned num_buffers
,
1992 const struct pipe_vertex_buffer
*buffers
)
1994 struct panfrost_context
*ctx
= pan_context(pctx
);
1996 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2000 panfrost_set_constant_buffer(
2001 struct pipe_context
*pctx
,
2002 enum pipe_shader_type shader
, uint index
,
2003 const struct pipe_constant_buffer
*buf
)
2005 struct panfrost_context
*ctx
= pan_context(pctx
);
2006 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2008 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2010 unsigned mask
= (1 << index
);
2012 if (unlikely(!buf
)) {
2013 pbuf
->enabled_mask
&= ~mask
;
2014 pbuf
->dirty_mask
&= ~mask
;
2018 pbuf
->enabled_mask
|= mask
;
2019 pbuf
->dirty_mask
|= mask
;
2023 panfrost_set_stencil_ref(
2024 struct pipe_context
*pctx
,
2025 const struct pipe_stencil_ref
*ref
)
2027 struct panfrost_context
*ctx
= pan_context(pctx
);
2028 ctx
->stencil_ref
= *ref
;
2031 static enum mali_texture_type
2032 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2036 case PIPE_TEXTURE_1D
:
2037 case PIPE_TEXTURE_1D_ARRAY
:
2040 case PIPE_TEXTURE_2D
:
2041 case PIPE_TEXTURE_2D_ARRAY
:
2042 case PIPE_TEXTURE_RECT
:
2045 case PIPE_TEXTURE_3D
:
2048 case PIPE_TEXTURE_CUBE
:
2049 case PIPE_TEXTURE_CUBE_ARRAY
:
2050 return MALI_TEX_CUBE
;
2053 unreachable("Unknown target");
2058 panfrost_compute_astc_stretch(
2059 const struct util_format_description
*desc
)
2061 unsigned width
= desc
->block
.width
;
2062 unsigned height
= desc
->block
.height
;
2063 assert(width
>= 4 && width
<= 12);
2064 assert(height
>= 4 && height
<= 12);
2069 return ((height
- 4) * 8) + (width
- 4);
2072 static struct pipe_sampler_view
*
2073 panfrost_create_sampler_view(
2074 struct pipe_context
*pctx
,
2075 struct pipe_resource
*texture
,
2076 const struct pipe_sampler_view
*template)
2078 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2079 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2081 pipe_reference(NULL
, &texture
->reference
);
2083 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2086 so
->base
= *template;
2087 so
->base
.texture
= texture
;
2088 so
->base
.reference
.count
= 1;
2089 so
->base
.context
= pctx
;
2091 /* sampler_views correspond to texture descriptors, minus the texture
2092 * (data) itself. So, we serialise the descriptor here and cache it for
2095 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2097 unsigned char user_swizzle
[4] = {
2098 template->swizzle_r
,
2099 template->swizzle_g
,
2100 template->swizzle_b
,
2104 enum mali_format format
= panfrost_find_format(desc
);
2106 if (format
== MALI_ASTC_HDR_SUPP
|| format
== MALI_ASTC_SRGB_SUPP
)
2107 so
->astc_stretch
= panfrost_compute_astc_stretch(desc
);
2109 /* Check if we need to set a custom stride by computing the "expected"
2110 * stride and comparing it to what the BO actually wants. Only applies
2111 * to linear textures, since tiled/compressed textures have strict
2112 * alignment requirements for their strides as it is */
2114 unsigned first_level
= template->u
.tex
.first_level
;
2115 unsigned last_level
= template->u
.tex
.last_level
;
2117 if (prsrc
->layout
== MALI_TEXTURE_LINEAR
) {
2118 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2119 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2120 unsigned width
= u_minify(texture
->width0
, l
);
2121 unsigned comp_stride
= width
* bytes_per_pixel
;
2123 if (comp_stride
!= actual_stride
) {
2124 so
->manual_stride
= true;
2130 /* In the hardware, array_size refers specifically to array textures,
2131 * whereas in Gallium, it also covers cubemaps */
2133 unsigned array_size
= texture
->array_size
;
2135 if (template->target
== PIPE_TEXTURE_CUBE
) {
2136 /* TODO: Cubemap arrays */
2137 assert(array_size
== 6);
2141 struct mali_texture_descriptor texture_descriptor
= {
2142 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2143 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2144 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2145 .array_size
= MALI_POSITIVE(array_size
),
2148 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2150 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2151 .type
= panfrost_translate_texture_type(template->target
),
2155 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2158 texture_descriptor
.levels
= last_level
- first_level
;
2160 so
->hw
= texture_descriptor
;
2162 return (struct pipe_sampler_view
*) so
;
2166 panfrost_set_sampler_views(
2167 struct pipe_context
*pctx
,
2168 enum pipe_shader_type shader
,
2169 unsigned start_slot
, unsigned num_views
,
2170 struct pipe_sampler_view
**views
)
2172 struct panfrost_context
*ctx
= pan_context(pctx
);
2173 unsigned new_nr
= 0;
2176 assert(start_slot
== 0);
2178 for (i
= 0; i
< num_views
; ++i
) {
2181 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2185 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
2186 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2189 ctx
->sampler_view_count
[shader
] = new_nr
;
2193 panfrost_sampler_view_destroy(
2194 struct pipe_context
*pctx
,
2195 struct pipe_sampler_view
*view
)
2197 pipe_resource_reference(&view
->texture
, NULL
);
2202 panfrost_set_shader_buffers(
2203 struct pipe_context
*pctx
,
2204 enum pipe_shader_type shader
,
2205 unsigned start
, unsigned count
,
2206 const struct pipe_shader_buffer
*buffers
,
2207 unsigned writable_bitmask
)
2209 struct panfrost_context
*ctx
= pan_context(pctx
);
2211 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2212 buffers
, start
, count
);
2215 /* Hints that a framebuffer should use AFBC where possible */
2219 struct panfrost_screen
*screen
,
2220 const struct pipe_framebuffer_state
*fb
)
2222 /* AFBC implemenation incomplete; hide it */
2223 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2225 /* Hint AFBC to the resources bound to each color buffer */
2227 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2228 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2229 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2230 panfrost_resource_hint_layout(screen
, rsrc
, MALI_TEXTURE_AFBC
, 1);
2233 /* Also hint it to the depth buffer */
2236 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2237 panfrost_resource_hint_layout(screen
, rsrc
, MALI_TEXTURE_AFBC
, 1);
2242 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2243 const struct pipe_framebuffer_state
*fb
)
2245 struct panfrost_context
*ctx
= pan_context(pctx
);
2247 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
2248 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2250 panfrost_invalidate_frame(ctx
);
2254 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2255 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2257 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2261 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2264 struct panfrost_context
*ctx
= pan_context(pipe
);
2265 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2266 ctx
->depth_stencil
= depth_stencil
;
2271 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2272 * emulated in the fragment shader */
2274 if (depth_stencil
->alpha
.enabled
) {
2275 /* We need to trigger a new shader (maybe) */
2276 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2280 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2282 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2283 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2285 /* If back-stencil is not enabled, use the front values */
2286 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2287 unsigned back_index
= back_enab
? 1 : 0;
2289 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2290 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2292 /* Depth state (TODO: Refactor) */
2293 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_WRITEMASK
,
2294 depth_stencil
->depth
.writemask
);
2296 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2298 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2299 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2301 /* Bounds test not implemented */
2302 assert(!depth_stencil
->depth
.bounds_test
);
2306 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2312 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2313 unsigned sample_mask
)
2318 panfrost_set_clip_state(struct pipe_context
*pipe
,
2319 const struct pipe_clip_state
*clip
)
2321 //struct panfrost_context *panfrost = pan_context(pipe);
2325 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2326 unsigned start_slot
,
2327 unsigned num_viewports
,
2328 const struct pipe_viewport_state
*viewports
)
2330 struct panfrost_context
*ctx
= pan_context(pipe
);
2332 assert(start_slot
== 0);
2333 assert(num_viewports
== 1);
2335 ctx
->pipe_viewport
= *viewports
;
2339 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2340 unsigned start_slot
,
2341 unsigned num_scissors
,
2342 const struct pipe_scissor_state
*scissors
)
2344 struct panfrost_context
*ctx
= pan_context(pipe
);
2346 assert(start_slot
== 0);
2347 assert(num_scissors
== 1);
2349 ctx
->scissor
= *scissors
;
2353 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2354 const struct pipe_poly_stipple
*stipple
)
2356 //struct panfrost_context *panfrost = pan_context(pipe);
2360 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2363 struct panfrost_context
*ctx
= pan_context(pipe
);
2364 ctx
->active_queries
= enable
;
2368 panfrost_destroy(struct pipe_context
*pipe
)
2370 struct panfrost_context
*panfrost
= pan_context(pipe
);
2372 if (panfrost
->blitter
)
2373 util_blitter_destroy(panfrost
->blitter
);
2375 if (panfrost
->blitter_wallpaper
)
2376 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2378 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
2379 u_upload_destroy(pipe
->stream_uploader
);
2384 static struct pipe_query
*
2385 panfrost_create_query(struct pipe_context
*pipe
,
2389 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2394 return (struct pipe_query
*) q
;
2398 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2400 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2403 panfrost_bo_unreference(query
->bo
);
2411 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2413 struct panfrost_context
*ctx
= pan_context(pipe
);
2414 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2416 switch (query
->type
) {
2417 case PIPE_QUERY_OCCLUSION_COUNTER
:
2418 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2419 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2420 /* Allocate a bo for the query results to be stored */
2422 query
->bo
= panfrost_bo_create(
2423 pan_screen(ctx
->base
.screen
),
2424 sizeof(unsigned), 0);
2427 unsigned *result
= (unsigned *)query
->bo
->cpu
;
2428 *result
= 0; /* Default to 0 if nothing at all drawn. */
2429 ctx
->occlusion_query
= query
;
2432 /* Geometry statistics are computed in the driver. XXX: geom/tess
2435 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2436 query
->start
= ctx
->prims_generated
;
2438 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2439 query
->start
= ctx
->tf_prims_generated
;
2443 DBG("Skipping query %u\n", query
->type
);
2451 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2453 struct panfrost_context
*ctx
= pan_context(pipe
);
2454 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2456 switch (query
->type
) {
2457 case PIPE_QUERY_OCCLUSION_COUNTER
:
2458 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2459 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2460 ctx
->occlusion_query
= NULL
;
2462 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2463 query
->end
= ctx
->prims_generated
;
2465 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2466 query
->end
= ctx
->tf_prims_generated
;
2474 panfrost_get_query_result(struct pipe_context
*pipe
,
2475 struct pipe_query
*q
,
2477 union pipe_query_result
*vresult
)
2479 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2480 struct panfrost_context
*ctx
= pan_context(pipe
);
2483 switch (query
->type
) {
2484 case PIPE_QUERY_OCCLUSION_COUNTER
:
2485 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2486 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2488 panfrost_flush_all_batches(ctx
, true);
2490 /* Read back the query results */
2491 unsigned *result
= (unsigned *) query
->bo
->cpu
;
2492 unsigned passed
= *result
;
2494 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2495 vresult
->u64
= passed
;
2497 vresult
->b
= !!passed
;
2502 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2503 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2504 panfrost_flush_all_batches(ctx
, true);
2505 vresult
->u64
= query
->end
- query
->start
;
2509 DBG("Skipped query get %u\n", query
->type
);
2516 static struct pipe_stream_output_target
*
2517 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2518 struct pipe_resource
*prsc
,
2519 unsigned buffer_offset
,
2520 unsigned buffer_size
)
2522 struct pipe_stream_output_target
*target
;
2524 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2529 pipe_reference_init(&target
->reference
, 1);
2530 pipe_resource_reference(&target
->buffer
, prsc
);
2532 target
->context
= pctx
;
2533 target
->buffer_offset
= buffer_offset
;
2534 target
->buffer_size
= buffer_size
;
2540 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2541 struct pipe_stream_output_target
*target
)
2543 pipe_resource_reference(&target
->buffer
, NULL
);
2544 ralloc_free(target
);
2548 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2549 unsigned num_targets
,
2550 struct pipe_stream_output_target
**targets
,
2551 const unsigned *offsets
)
2553 struct panfrost_context
*ctx
= pan_context(pctx
);
2554 struct panfrost_streamout
*so
= &ctx
->streamout
;
2556 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2558 for (unsigned i
= 0; i
< num_targets
; i
++) {
2559 if (offsets
[i
] != -1)
2560 so
->offsets
[i
] = offsets
[i
];
2562 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2565 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2566 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2568 so
->num_targets
= num_targets
;
2571 struct pipe_context
*
2572 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2574 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2575 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2577 gallium
->screen
= screen
;
2579 gallium
->destroy
= panfrost_destroy
;
2581 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2583 gallium
->flush
= panfrost_flush
;
2584 gallium
->clear
= panfrost_clear
;
2585 gallium
->draw_vbo
= panfrost_draw_vbo
;
2587 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2588 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2589 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2591 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2593 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2594 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2595 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2597 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2598 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2599 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2601 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2602 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2603 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2605 gallium
->create_fs_state
= panfrost_create_fs_state
;
2606 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2607 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2609 gallium
->create_vs_state
= panfrost_create_vs_state
;
2610 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2611 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2613 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2614 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2615 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2617 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2618 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2619 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2621 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2623 gallium
->set_clip_state
= panfrost_set_clip_state
;
2624 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2625 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2626 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2627 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2629 gallium
->create_query
= panfrost_create_query
;
2630 gallium
->destroy_query
= panfrost_destroy_query
;
2631 gallium
->begin_query
= panfrost_begin_query
;
2632 gallium
->end_query
= panfrost_end_query
;
2633 gallium
->get_query_result
= panfrost_get_query_result
;
2635 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2636 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2637 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2639 panfrost_resource_context_init(gallium
);
2640 panfrost_blend_context_init(gallium
);
2641 panfrost_compute_context_init(gallium
);
2644 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2645 gallium
->const_uploader
= gallium
->stream_uploader
;
2646 assert(gallium
->stream_uploader
);
2648 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2649 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2651 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2653 ctx
->blitter
= util_blitter_create(gallium
);
2654 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2656 assert(ctx
->blitter
);
2657 assert(ctx
->blitter_wallpaper
);
2659 /* Prepare for render! */
2661 panfrost_batch_init(ctx
);
2662 panfrost_emit_vertex_payload(ctx
);
2663 panfrost_invalidate_frame(ctx
);
2664 panfrost_default_shader_backend(ctx
);