2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_format.h"
34 #include "util/macros.h"
35 #include "util/u_format.h"
36 #include "util/u_inlines.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_memory.h"
39 #include "util/u_vbuf.h"
40 #include "util/half_float.h"
41 #include "util/u_helpers.h"
42 #include "util/u_format.h"
43 #include "util/u_prim.h"
44 #include "util/u_prim_restart.h"
45 #include "indices/u_primconvert.h"
46 #include "tgsi/tgsi_parse.h"
47 #include "tgsi/tgsi_from_mesa.h"
48 #include "util/u_math.h"
50 #include "pan_screen.h"
51 #include "pan_blending.h"
52 #include "pan_blend_shaders.h"
55 /* Framebuffer descriptor */
57 static struct midgard_tiler_descriptor
58 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
60 struct midgard_tiler_descriptor t
= {};
61 unsigned height
= batch
->key
.height
;
62 unsigned width
= batch
->key
.width
;
65 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
67 /* Compute the polygon header size and use that to offset the body */
69 unsigned header_size
= panfrost_tiler_header_size(
70 width
, height
, t
.hierarchy_mask
);
72 t
.polygon_list_size
= panfrost_tiler_full_size(
73 width
, height
, t
.hierarchy_mask
);
77 if (t
.hierarchy_mask
) {
78 struct panfrost_bo
*tiler_heap
;
80 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
81 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
86 /* Allow the entire tiler heap */
87 t
.heap_start
= tiler_heap
->gpu
;
88 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
90 struct panfrost_bo
*tiler_dummy
;
92 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
94 /* The tiler is disabled, so don't allow the tiler heap */
95 t
.heap_start
= tiler_dummy
->gpu
;
96 t
.heap_end
= t
.heap_start
;
98 /* Use a dummy polygon list */
99 t
.polygon_list
= tiler_dummy
->gpu
;
101 /* Disable the tiler */
102 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
105 t
.polygon_list_body
=
106 t
.polygon_list
+ header_size
;
111 struct mali_single_framebuffer
112 panfrost_emit_sfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
114 unsigned width
= batch
->key
.width
;
115 unsigned height
= batch
->key
.height
;
117 struct mali_single_framebuffer framebuffer
= {
118 .width
= MALI_POSITIVE(width
),
119 .height
= MALI_POSITIVE(height
),
124 .clear_flags
= 0x1000,
125 .unknown_address_0
= panfrost_batch_get_scratchpad(batch
)->gpu
,
126 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
),
132 struct bifrost_framebuffer
133 panfrost_emit_mfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
135 unsigned width
= batch
->key
.width
;
136 unsigned height
= batch
->key
.height
;
138 struct bifrost_framebuffer framebuffer
= {
139 .unk0
= 0x1e5, /* 1e4 if no spill */
140 .width1
= MALI_POSITIVE(width
),
141 .height1
= MALI_POSITIVE(height
),
142 .width2
= MALI_POSITIVE(width
),
143 .height2
= MALI_POSITIVE(height
),
147 .rt_count_1
= MALI_POSITIVE(batch
->key
.nr_cbufs
),
152 .scratchpad
= panfrost_batch_get_scratchpad(batch
)->gpu
,
153 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
)
161 struct pipe_context
*pipe
,
163 const union pipe_color_union
*color
,
164 double depth
, unsigned stencil
)
166 struct panfrost_context
*ctx
= pan_context(pipe
);
168 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
169 * the existing batch targeting this FBO has draws. We could probably
170 * avoid that by replacing plain clears by quad-draws with a specific
171 * color/depth/stencil value, thus avoiding the generation of extra
172 * fragment/set_value jobs.
174 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
176 panfrost_batch_add_fbo_bos(batch
);
177 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
181 panfrost_attach_vt_mfbd(struct panfrost_batch
*batch
)
183 struct bifrost_framebuffer mfbd
= panfrost_emit_mfbd(batch
, ~0);
185 return panfrost_upload_transient(batch
, &mfbd
, sizeof(mfbd
)) | MALI_MFBD
;
189 panfrost_attach_vt_sfbd(struct panfrost_batch
*batch
)
191 struct mali_single_framebuffer sfbd
= panfrost_emit_sfbd(batch
, ~0);
193 return panfrost_upload_transient(batch
, &sfbd
, sizeof(sfbd
)) | MALI_SFBD
;
197 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
199 /* Skip the attach if we can */
201 if (ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
) {
202 assert(ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
206 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
207 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
209 if (!batch
->framebuffer
)
210 batch
->framebuffer
= screen
->require_sfbd
?
211 panfrost_attach_vt_sfbd(batch
) :
212 panfrost_attach_vt_mfbd(batch
);
214 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
215 ctx
->payloads
[i
].postfix
.framebuffer
= batch
->framebuffer
;
218 /* Reset per-frame context, called on context initialisation as well as after
219 * flushing a frame */
222 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
224 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
225 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
228 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
231 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
233 /* TODO: When does this need to be handled? */
234 ctx
->active_queries
= true;
237 /* In practice, every field of these payloads should be configurable
238 * arbitrarily, which means these functions are basically catch-all's for
239 * as-of-yet unwavering unknowns */
242 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
244 /* 0x2 bit clear on 32-bit T6XX */
246 struct midgard_payload_vertex_tiler payload
= {
247 .gl_enables
= 0x4 | 0x2,
250 /* Vertex and compute are closely coupled, so share a payload */
252 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
253 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
257 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
259 struct midgard_payload_vertex_tiler payload
= {
261 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
265 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
269 translate_tex_wrap(enum pipe_tex_wrap w
)
272 case PIPE_TEX_WRAP_REPEAT
:
273 return MALI_WRAP_REPEAT
;
275 /* TODO: lower GL_CLAMP? */
276 case PIPE_TEX_WRAP_CLAMP
:
277 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
278 return MALI_WRAP_CLAMP_TO_EDGE
;
280 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
281 return MALI_WRAP_CLAMP_TO_BORDER
;
283 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
284 return MALI_WRAP_MIRRORED_REPEAT
;
287 unreachable("Invalid wrap");
292 panfrost_translate_compare_func(enum pipe_compare_func in
)
295 case PIPE_FUNC_NEVER
:
296 return MALI_FUNC_NEVER
;
299 return MALI_FUNC_LESS
;
301 case PIPE_FUNC_EQUAL
:
302 return MALI_FUNC_EQUAL
;
304 case PIPE_FUNC_LEQUAL
:
305 return MALI_FUNC_LEQUAL
;
307 case PIPE_FUNC_GREATER
:
308 return MALI_FUNC_GREATER
;
310 case PIPE_FUNC_NOTEQUAL
:
311 return MALI_FUNC_NOTEQUAL
;
313 case PIPE_FUNC_GEQUAL
:
314 return MALI_FUNC_GEQUAL
;
316 case PIPE_FUNC_ALWAYS
:
317 return MALI_FUNC_ALWAYS
;
320 unreachable("Invalid func");
325 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
328 case PIPE_FUNC_NEVER
:
329 return MALI_ALT_FUNC_NEVER
;
332 return MALI_ALT_FUNC_LESS
;
334 case PIPE_FUNC_EQUAL
:
335 return MALI_ALT_FUNC_EQUAL
;
337 case PIPE_FUNC_LEQUAL
:
338 return MALI_ALT_FUNC_LEQUAL
;
340 case PIPE_FUNC_GREATER
:
341 return MALI_ALT_FUNC_GREATER
;
343 case PIPE_FUNC_NOTEQUAL
:
344 return MALI_ALT_FUNC_NOTEQUAL
;
346 case PIPE_FUNC_GEQUAL
:
347 return MALI_ALT_FUNC_GEQUAL
;
349 case PIPE_FUNC_ALWAYS
:
350 return MALI_ALT_FUNC_ALWAYS
;
353 unreachable("Invalid alt func");
358 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
361 case PIPE_STENCIL_OP_KEEP
:
362 return MALI_STENCIL_KEEP
;
364 case PIPE_STENCIL_OP_ZERO
:
365 return MALI_STENCIL_ZERO
;
367 case PIPE_STENCIL_OP_REPLACE
:
368 return MALI_STENCIL_REPLACE
;
370 case PIPE_STENCIL_OP_INCR
:
371 return MALI_STENCIL_INCR
;
373 case PIPE_STENCIL_OP_DECR
:
374 return MALI_STENCIL_DECR
;
376 case PIPE_STENCIL_OP_INCR_WRAP
:
377 return MALI_STENCIL_INCR_WRAP
;
379 case PIPE_STENCIL_OP_DECR_WRAP
:
380 return MALI_STENCIL_DECR_WRAP
;
382 case PIPE_STENCIL_OP_INVERT
:
383 return MALI_STENCIL_INVERT
;
386 unreachable("Invalid stencil op");
391 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
393 out
->ref
= 0; /* Gallium gets it from elsewhere */
395 out
->mask
= in
->valuemask
;
396 out
->func
= panfrost_translate_compare_func(in
->func
);
397 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
398 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
399 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
403 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
405 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
406 struct mali_shader_meta shader
= {
407 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
409 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
410 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
413 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this is
414 * required (independent of 32-bit/64-bit descriptors), or why it's not
415 * used on later GPU revisions. Otherwise, all shader jobs fault on
416 * these earlier chips (perhaps this is a chicken bit of some kind).
417 * More investigation is needed. */
419 if (screen
->require_sfbd
) {
420 shader
.unknown2_4
|= 0x10;
423 struct pipe_stencil_state default_stencil
= {
425 .func
= PIPE_FUNC_ALWAYS
,
426 .fail_op
= MALI_STENCIL_KEEP
,
427 .zfail_op
= MALI_STENCIL_KEEP
,
428 .zpass_op
= MALI_STENCIL_KEEP
,
433 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
434 shader
.stencil_mask_front
= default_stencil
.writemask
;
436 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
437 shader
.stencil_mask_back
= default_stencil
.writemask
;
439 if (default_stencil
.enabled
)
440 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
442 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
445 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
446 * graphics command stream. It should be called once per draw, accordding to
447 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
448 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
451 struct panfrost_transfer
452 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
454 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
455 struct mali_job_descriptor_header job
= {
456 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
457 .job_descriptor_size
= 1,
460 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
462 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sizeof(job
) + sizeof(*payload
));
463 memcpy(transfer
.cpu
, &job
, sizeof(job
));
464 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
469 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
471 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
472 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
474 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
478 panfrost_writes_point_size(struct panfrost_context
*ctx
)
480 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
481 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
483 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
486 /* Stage the attribute descriptors so we can adjust src_offset
487 * to let BOs align nicely */
490 panfrost_stage_attributes(struct panfrost_context
*ctx
)
492 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
493 struct panfrost_vertex_state
*so
= ctx
->vertex
;
495 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
496 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
497 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
499 /* Copy as-is for the first pass */
500 memcpy(target
, so
->hw
, sz
);
502 /* Fixup offsets for the second pass. Recall that the hardware
503 * calculates attribute addresses as:
505 * addr = base + (stride * vtx) + src_offset;
507 * However, on Mali, base must be aligned to 64-bytes, so we
510 * base' = base & ~63 = base - (base & 63)
512 * To compensate when using base' (see emit_vertex_data), we have
513 * to adjust src_offset by the masked off piece:
515 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
516 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
517 * = base + (stride * vtx) + src_offset
523 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
525 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
526 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
527 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
528 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
530 /* Adjust by the masked off bits of the offset */
531 target
[i
].src_offset
+= (addr
& 63);
533 /* Also, somewhat obscurely per-instance data needs to be
534 * offset in response to a delayed start in an indexed draw */
536 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
537 target
[i
].src_offset
-= buf
->stride
* start
;
543 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
547 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
549 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
550 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
552 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
555 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
556 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
558 struct panfrost_transfer transfer
=
559 panfrost_allocate_transient(batch
, transfer_size
);
561 struct mali_sampler_descriptor
*desc
=
562 (struct mali_sampler_descriptor
*) transfer
.cpu
;
564 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
565 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
567 upload
= transfer
.gpu
;
570 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
574 static enum mali_texture_layout
575 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
577 /* TODO: other linear depth textures */
578 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
580 switch (rsrc
->layout
) {
582 return MALI_TEXTURE_AFBC
;
585 return MALI_TEXTURE_TILED
;
587 return is_depth
? MALI_TEXTURE_TILED
: MALI_TEXTURE_LINEAR
;
589 unreachable("Invalid texture layout");
595 struct panfrost_context
*ctx
,
596 enum pipe_shader_type st
,
597 struct panfrost_sampler_view
*view
)
602 struct pipe_sampler_view
*pview
= &view
->base
;
603 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
605 /* Do we interleave an explicit stride with every element? */
607 bool has_manual_stride
= view
->manual_stride
;
609 /* For easy access */
611 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
612 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
613 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
614 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
615 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
617 /* Lower-bit is set when sampling from colour AFBC */
618 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
619 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
620 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
622 /* Add the BO to the job so it's retained until the job is done. */
623 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
624 panfrost_batch_add_bo(batch
, rsrc
->bo
,
625 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
626 panfrost_bo_access_for_stage(st
));
628 /* Add the usage flags in, since they can change across the CSO
629 * lifetime due to layout switches */
631 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
632 view
->hw
.format
.manual_stride
= has_manual_stride
;
634 /* Inject the addresses in, interleaving mip levels, cube faces, and
635 * strides in that order */
639 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
640 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
642 view
->hw
.payload
[idx
++] =
643 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
645 if (has_manual_stride
) {
646 view
->hw
.payload
[idx
++] =
647 rsrc
->slices
[l
].stride
;
652 return panfrost_upload_transient(batch
, &view
->hw
,
653 sizeof(struct mali_texture_descriptor
));
657 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
659 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
661 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
662 mali_ptr trampoline
= 0;
664 if (ctx
->sampler_view_count
[t
]) {
665 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
667 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
669 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
671 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
674 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
678 struct sysval_uniform
{
687 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
688 struct sysval_uniform
*uniform
)
690 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
692 uniform
->f
[0] = vp
->scale
[0];
693 uniform
->f
[1] = vp
->scale
[1];
694 uniform
->f
[2] = vp
->scale
[2];
697 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
698 struct sysval_uniform
*uniform
)
700 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
702 uniform
->f
[0] = vp
->translate
[0];
703 uniform
->f
[1] = vp
->translate
[1];
704 uniform
->f
[2] = vp
->translate
[2];
707 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
708 enum pipe_shader_type st
,
709 unsigned int sysvalid
,
710 struct sysval_uniform
*uniform
)
712 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
713 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
714 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
715 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
718 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
721 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
722 tex
->u
.tex
.first_level
);
725 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
726 tex
->u
.tex
.first_level
);
729 uniform
->i
[dim
] = tex
->texture
->array_size
;
732 static void panfrost_upload_ssbo_sysval(
733 struct panfrost_context
*ctx
,
734 enum pipe_shader_type st
,
736 struct sysval_uniform
*uniform
)
738 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
739 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
741 /* Compute address */
742 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
743 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
745 panfrost_batch_add_bo(batch
, bo
,
746 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
747 panfrost_bo_access_for_stage(st
));
749 /* Upload address and size as sysval */
750 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
751 uniform
->u
[2] = sb
.buffer_size
;
754 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
755 struct sysval_uniform
*uniform
)
757 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
758 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
759 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
762 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
763 struct panfrost_shader_state
*ss
,
764 enum pipe_shader_type st
)
766 struct sysval_uniform
*uniforms
= (void *)buf
;
768 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
769 int sysval
= ss
->sysval
[i
];
771 switch (PAN_SYSVAL_TYPE(sysval
)) {
772 case PAN_SYSVAL_VIEWPORT_SCALE
:
773 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
775 case PAN_SYSVAL_VIEWPORT_OFFSET
:
776 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
778 case PAN_SYSVAL_TEXTURE_SIZE
:
779 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
782 case PAN_SYSVAL_SSBO
:
783 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
786 case PAN_SYSVAL_NUM_WORK_GROUPS
:
787 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
797 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
799 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
800 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
803 return rsrc
->bo
->cpu
;
804 else if (cb
->user_buffer
)
805 return cb
->user_buffer
;
807 unreachable("No constant buffer");
811 panfrost_map_constant_buffer_gpu(
812 struct panfrost_context
*ctx
,
813 enum pipe_shader_type st
,
814 struct panfrost_constant_buffer
*buf
,
817 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
818 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
819 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
822 panfrost_batch_add_bo(batch
, rsrc
->bo
,
823 PAN_BO_ACCESS_SHARED
|
825 panfrost_bo_access_for_stage(st
));
826 return rsrc
->bo
->gpu
;
827 } else if (cb
->user_buffer
) {
828 return panfrost_upload_transient(batch
, cb
->user_buffer
, cb
->buffer_size
);
830 unreachable("No constant buffer");
834 /* Compute number of UBOs active (more specifically, compute the highest UBO
835 * number addressable -- if there are gaps, include them in the count anyway).
836 * We always include UBO #0 in the count, since we *need* uniforms enabled for
840 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
842 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
843 return 32 - __builtin_clz(mask
);
846 /* Fixes up a shader state with current state, returning a GPU address to the
850 panfrost_patch_shader_state(
851 struct panfrost_context
*ctx
,
852 struct panfrost_shader_state
*ss
,
853 enum pipe_shader_type stage
,
856 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
857 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
859 ss
->tripipe
->midgard1
.flags
= 0x220;
861 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
862 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
864 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
866 /* Add the shader BO to the batch. */
867 panfrost_batch_add_bo(batch
, ss
->bo
,
868 PAN_BO_ACCESS_PRIVATE
|
870 panfrost_bo_access_for_stage(stage
));
872 /* We can't reuse over frames; that's not safe. The descriptor must be
873 * transient uploaded */
876 return panfrost_upload_transient(batch
, ss
->tripipe
,
877 sizeof(struct mali_shader_meta
));
880 /* If we don't need an upload, don't bother */
886 panfrost_patch_shader_state_compute(
887 struct panfrost_context
*ctx
,
888 enum pipe_shader_type stage
,
891 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
894 ctx
->payloads
[stage
].postfix
.shader
= 0;
898 struct panfrost_shader_state
*s
= &all
->variants
[all
->active_variant
];
900 ctx
->payloads
[stage
].postfix
.shader
=
901 panfrost_patch_shader_state(ctx
, s
, stage
, should_upload
);
904 /* Go through dirty flags and actualise them in the cmdstream. */
907 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
909 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
910 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
912 panfrost_batch_add_fbo_bos(batch
);
913 panfrost_attach_vt_framebuffer(ctx
);
915 if (with_vertex_data
) {
916 panfrost_emit_vertex_data(batch
);
918 /* Varyings emitted for -all- geometry */
919 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
920 panfrost_emit_varying_descriptor(ctx
, total_count
);
923 bool msaa
= ctx
->rasterizer
->base
.multisample
;
925 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
926 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
928 /* TODO: Sample size */
929 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
930 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
933 panfrost_batch_set_requirements(batch
);
935 if (ctx
->occlusion_query
) {
936 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
;
937 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
940 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_VERTEX
, true);
941 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_COMPUTE
, true);
943 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
944 /* Check if we need to link the gl_PointSize varying */
945 if (!panfrost_writes_point_size(ctx
)) {
946 /* If the size is constant, write it out. Otherwise,
947 * don't touch primitive_size (since we would clobber
948 * the pointer there) */
950 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
954 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
955 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
956 ctx
->dirty
|= PAN_DIRTY_FS
;
958 if (ctx
->dirty
& PAN_DIRTY_FS
) {
959 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
960 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
962 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
964 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
967 COPY(attribute_count
);
971 COPY(midgard1
.uniform_count
);
972 COPY(midgard1
.uniform_buffer_count
);
973 COPY(midgard1
.work_count
);
974 COPY(midgard1
.flags
);
975 COPY(midgard1
.unknown2
);
979 /* Get blending setup */
980 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
982 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
984 for (unsigned c
= 0; c
< rt_count
; ++c
)
985 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
987 /* If there is a blend shader, work registers are shared. XXX: opt */
989 for (unsigned c
= 0; c
< rt_count
; ++c
) {
990 if (blend
[c
].is_shader
)
991 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
994 /* Set late due to depending on render state */
995 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
997 /* Depending on whether it's legal to in the given shader, we
998 * try to enable early-z testing (or forward-pixel kill?) */
1000 if (!variant
->can_discard
)
1001 flags
|= MALI_EARLY_Z
;
1003 /* Any time texturing is used, derivatives are implicitly
1004 * calculated, so we need to enable helper invocations */
1006 if (variant
->helper_invocations
)
1007 flags
|= MALI_HELPER_INVOCATIONS
;
1009 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
1011 /* Assign the stencil refs late */
1013 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
1014 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
1015 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
1017 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
1018 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
1020 /* CAN_DISCARD should be set if the fragment shader possibly
1021 * contains a 'discard' instruction. It is likely this is
1022 * related to optimizations related to forward-pixel kill, as
1023 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1024 * thing?" by Peter Harris
1027 if (variant
->can_discard
) {
1028 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1029 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1032 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1033 * *also* copied to the blend_meta appended (by convention),
1034 * but this is the field actually read by the hardware. (Or
1035 * maybe both are read...?) */
1037 if (blend
[0].is_shader
) {
1038 ctx
->fragment_shader_core
.blend
.shader
=
1039 blend
[0].shader
.bo
->gpu
| blend
[0].shader
.first_tag
;
1041 ctx
->fragment_shader_core
.blend
.shader
= 0;
1044 if (screen
->require_sfbd
) {
1045 /* When only a single render target platform is used, the blend
1046 * information is inside the shader meta itself. We
1047 * additionally need to signal CAN_DISCARD for nontrivial blend
1048 * modes (so we're able to read back the destination buffer) */
1050 if (blend
[0].is_shader
) {
1051 ctx
->fragment_shader_core
.unknown2_3
|= MALI_HAS_BLEND_SHADER
;
1053 ctx
->fragment_shader_core
.blend
.equation
=
1054 *blend
[0].equation
.equation
;
1055 ctx
->fragment_shader_core
.blend
.constant
=
1056 blend
[0].equation
.constant
;
1059 if (!blend
[0].no_blending
) {
1060 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1064 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1065 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1066 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1068 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.shader
= transfer
.gpu
;
1070 if (!screen
->require_sfbd
) {
1071 /* Additional blend descriptor tacked on for jobs using MFBD */
1073 struct midgard_blend_rt rts
[4];
1075 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1076 unsigned blend_count
= 0x200;
1078 if (blend
[i
].is_shader
) {
1079 /* For a blend shader, the bottom nibble corresponds to
1080 * the number of work registers used, which signals the
1081 * -existence- of a blend shader */
1083 assert(blend
[i
].shader
.work_count
>= 2);
1084 blend_count
|= MIN2(blend
[i
].shader
.work_count
, 3);
1086 /* Otherwise, the bottom bit simply specifies if
1087 * blending (anything other than REPLACE) is enabled */
1089 if (!blend
[i
].no_blending
)
1095 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1096 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1097 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1099 rts
[i
].flags
= blend_count
;
1102 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1104 if (!ctx
->blend
->base
.dither
)
1105 rts
[i
].flags
|= MALI_BLEND_NO_DITHER
;
1107 /* TODO: sRGB in blend shaders is currently
1108 * unimplemented. Contact me (Alyssa) if you're
1109 * interested in working on this. We have
1110 * native Midgard ops for helping here, but
1111 * they're not well-understood yet. */
1113 assert(!(is_srgb
&& blend
[i
].is_shader
));
1115 if (blend
[i
].is_shader
) {
1116 rts
[i
].blend
.shader
= blend
[i
].shader
.bo
->gpu
| blend
[i
].shader
.first_tag
;
1118 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1119 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1123 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1127 /* We stage to transient, so always dirty.. */
1129 panfrost_stage_attributes(ctx
);
1131 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1132 panfrost_upload_sampler_descriptors(ctx
);
1134 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1135 panfrost_upload_texture_descriptors(ctx
);
1137 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1139 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1140 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1145 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1147 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1149 /* Uniforms are implicitly UBO #0 */
1150 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1152 /* Allocate room for the sysval and the uniforms */
1153 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1154 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1155 size_t size
= sys_size
+ uniform_size
;
1156 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1158 /* Upload sysvals requested by the shader */
1159 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1161 /* Upload uniforms */
1163 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1164 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1168 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1170 struct mali_vertex_tiler_postfix
*postfix
=
1171 &ctx
->payloads
[i
].postfix
;
1173 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1176 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1177 assert(ubo_count
>= 1);
1179 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1180 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1182 /* Upload uniforms as a UBO */
1183 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1184 ubos
[0].ptr
= transfer
.gpu
>> 2;
1186 /* The rest are honest-to-goodness UBOs */
1188 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1189 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1191 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1192 bool empty
= usz
== 0;
1194 if (!enabled
|| empty
) {
1195 /* Stub out disabled UBOs to catch accesses */
1198 ubos
[ubo
].ptr
= 0xDEAD0000;
1202 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, i
, buf
, ubo
);
1204 unsigned bytes_per_field
= 16;
1205 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1206 unsigned fields
= aligned
/ bytes_per_field
;
1208 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1209 ubos
[ubo
].ptr
= gpu
>> 2;
1212 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1213 postfix
->uniforms
= transfer
.gpu
;
1214 postfix
->uniform_buffers
= ubufs
;
1216 buf
->dirty_mask
= 0;
1219 /* TODO: Upload the viewport somewhere more appropriate */
1221 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1222 * (somewhat) asymmetric ints. */
1223 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1225 struct mali_viewport view
= {
1226 /* By default, do no viewport clipping, i.e. clip to (-inf,
1227 * inf) in each direction. Clipping to the viewport in theory
1228 * should work, but in practice causes issues when we're not
1229 * explicitly trying to scissor */
1231 .clip_minx
= -INFINITY
,
1232 .clip_miny
= -INFINITY
,
1233 .clip_maxx
= INFINITY
,
1234 .clip_maxy
= INFINITY
,
1237 /* Always scissor to the viewport by default. */
1238 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1239 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1241 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1242 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1244 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1245 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1247 /* Apply the scissor test */
1249 unsigned minx
, miny
, maxx
, maxy
;
1251 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1252 minx
= MAX2(ss
->minx
, vp_minx
);
1253 miny
= MAX2(ss
->miny
, vp_miny
);
1254 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1255 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1263 /* Hardware needs the min/max to be strictly ordered, so flip if we
1264 * need to. The viewport transformation in the vertex shader will
1265 * handle the negatives if we don't */
1268 unsigned temp
= miny
;
1274 unsigned temp
= minx
;
1285 /* Clamp to the framebuffer size as a last check */
1287 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1288 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1290 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1291 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1293 /* Update the job, unless we're doing wallpapering (whose lack of
1294 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1295 * just... be faster :) */
1297 if (!ctx
->wallpaper_batch
)
1298 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1302 view
.viewport0
[0] = minx
;
1303 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1305 view
.viewport0
[1] = miny
;
1306 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1308 view
.clip_minz
= minz
;
1309 view
.clip_maxz
= maxz
;
1311 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1312 panfrost_upload_transient(batch
,
1314 sizeof(struct mali_viewport
));
1319 /* Corresponds to exactly one draw, but does not submit anything */
1322 panfrost_queue_draw(struct panfrost_context
*ctx
)
1324 /* Handle dirty flags now */
1325 panfrost_emit_for_draw(ctx
, true);
1327 /* If rasterizer discard is enable, only submit the vertex */
1329 bool rasterizer_discard
= ctx
->rasterizer
1330 && ctx
->rasterizer
->base
.rasterizer_discard
;
1332 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1333 struct panfrost_transfer tiler
;
1335 if (!rasterizer_discard
)
1336 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1338 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1340 if (rasterizer_discard
)
1341 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1342 else if (ctx
->wallpaper_batch
&& batch
->first_tiler
.gpu
)
1343 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1345 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1348 /* The entire frame is in memory -- send it off to the kernel! */
1352 struct pipe_context
*pipe
,
1353 struct pipe_fence_handle
**fence
,
1356 struct panfrost_context
*ctx
= pan_context(pipe
);
1357 struct util_dynarray fences
;
1359 /* We must collect the fences before the flush is done, otherwise we'll
1360 * lose track of them.
1363 util_dynarray_init(&fences
, NULL
);
1364 hash_table_foreach(ctx
->batches
, hentry
) {
1365 struct panfrost_batch
*batch
= hentry
->data
;
1367 panfrost_batch_fence_reference(batch
->out_sync
);
1368 util_dynarray_append(&fences
,
1369 struct panfrost_batch_fence
*,
1374 /* Submit all pending jobs */
1375 panfrost_flush_all_batches(ctx
, false);
1378 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
1379 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1380 *fence
= (struct pipe_fence_handle
*)f
;
1382 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
1383 panfrost_batch_fence_unreference(*fence
);
1385 util_dynarray_fini(&fences
);
1389 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1392 g2m_draw_mode(enum pipe_prim_type mode
)
1395 DEFINE_CASE(POINTS
);
1397 DEFINE_CASE(LINE_LOOP
);
1398 DEFINE_CASE(LINE_STRIP
);
1399 DEFINE_CASE(TRIANGLES
);
1400 DEFINE_CASE(TRIANGLE_STRIP
);
1401 DEFINE_CASE(TRIANGLE_FAN
);
1403 DEFINE_CASE(QUAD_STRIP
);
1404 DEFINE_CASE(POLYGON
);
1407 unreachable("Invalid draw mode");
1414 panfrost_translate_index_size(unsigned size
)
1418 return MALI_DRAW_INDEXED_UINT8
;
1421 return MALI_DRAW_INDEXED_UINT16
;
1424 return MALI_DRAW_INDEXED_UINT32
;
1427 unreachable("Invalid index size");
1431 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1432 * good for the duration of the draw (transient), could last longer */
1435 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1437 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1439 off_t offset
= info
->start
* info
->index_size
;
1440 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1442 if (!info
->has_user_indices
) {
1443 /* Only resources can be directly mapped */
1444 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1445 PAN_BO_ACCESS_SHARED
|
1446 PAN_BO_ACCESS_READ
|
1447 PAN_BO_ACCESS_VERTEX_TILER
);
1448 return rsrc
->bo
->gpu
+ offset
;
1450 /* Otherwise, we need to upload to transient memory */
1451 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1452 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1457 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1459 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1461 /* Check if we're scissoring at all */
1463 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1466 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1469 /* Count generated primitives (when there is no geom/tess shaders) for
1470 * transform feedback */
1473 panfrost_statistics_record(
1474 struct panfrost_context
*ctx
,
1475 const struct pipe_draw_info
*info
)
1477 if (!ctx
->active_queries
)
1480 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1481 ctx
->prims_generated
+= prims
;
1483 if (!ctx
->streamout
.num_targets
)
1486 ctx
->tf_prims_generated
+= prims
;
1491 struct pipe_context
*pipe
,
1492 const struct pipe_draw_info
*info
)
1494 struct panfrost_context
*ctx
= pan_context(pipe
);
1496 /* First of all, check the scissor to see if anything is drawn at all.
1497 * If it's not, we drop the draw (mostly a conformance issue;
1498 * well-behaved apps shouldn't hit this) */
1500 if (panfrost_scissor_culls_everything(ctx
))
1503 int mode
= info
->mode
;
1505 /* Fallback unsupported restart index */
1506 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1508 if (info
->primitive_restart
&& info
->index_size
1509 && info
->restart_index
!= primitive_index
) {
1510 util_draw_vbo_without_prim_restart(pipe
, info
);
1514 /* Fallback for unsupported modes */
1516 assert(ctx
->rasterizer
!= NULL
);
1518 if (!(ctx
->draw_modes
& (1 << mode
))) {
1519 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1520 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1522 if (info
->count
< 4) {
1523 /* Degenerate case? */
1527 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1528 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1533 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1534 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1536 /* Now that we have a guaranteed terminating path, find the job.
1537 * Assignment commented out to prevent unused warning */
1539 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1541 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1543 /* Take into account a negative bias */
1544 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1545 ctx
->instance_count
= info
->instance_count
;
1546 ctx
->active_prim
= info
->mode
;
1548 /* For non-indexed draws, they're the same */
1549 unsigned vertex_count
= ctx
->vertex_count
;
1551 unsigned draw_flags
= 0;
1553 /* The draw flags interpret how primitive size is interpreted */
1555 if (panfrost_writes_point_size(ctx
))
1556 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1558 if (info
->primitive_restart
)
1559 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1561 /* For higher amounts of vertices (greater than what fits in a 16-bit
1562 * short), the other value is needed, otherwise there will be bizarre
1563 * rendering artefacts. It's not clear what these values mean yet. This
1564 * change is also needed for instancing and sometimes points (perhaps
1565 * related to dynamically setting gl_PointSize) */
1567 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1568 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1569 bool instanced
= ctx
->instance_count
> 1;
1571 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1573 /* This doesn't make much sense */
1574 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1575 draw_flags
|= 0x800;
1578 panfrost_statistics_record(ctx
, info
);
1580 if (info
->index_size
) {
1581 /* Calculate the min/max index used so we can figure out how
1582 * many times to invoke the vertex shader */
1584 /* Fetch / calculate index bounds */
1585 unsigned min_index
= 0, max_index
= 0;
1587 if (info
->max_index
== ~0u) {
1588 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1590 min_index
= info
->min_index
;
1591 max_index
= info
->max_index
;
1594 /* Use the corresponding values */
1595 vertex_count
= max_index
- min_index
+ 1;
1596 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1597 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1599 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1600 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1602 //assert(!info->restart_index); /* TODO: Research */
1604 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1605 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1607 /* Index count == vertex count, if no indexing is applied, as
1608 * if it is internally indexed in the expected order */
1610 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1611 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1613 /* Reverse index state */
1614 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1617 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1618 * vertex_count, 1) */
1620 panfrost_pack_work_groups_fused(
1621 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1622 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1623 1, vertex_count
, info
->instance_count
,
1626 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1628 /* Encode the padded vertex count */
1630 if (info
->instance_count
> 1) {
1631 /* Triangles have non-even vertex counts so they change how
1632 * padding works internally */
1635 mode
== PIPE_PRIM_TRIANGLES
||
1636 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1637 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1639 struct pan_shift_odd so
=
1640 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1642 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= so
.shift
;
1643 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= so
.shift
;
1645 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= so
.odd
;
1646 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= so
.odd
;
1648 ctx
->padded_count
= pan_expand_shift_odd(so
);
1650 ctx
->padded_count
= vertex_count
;
1652 /* Reset instancing state */
1653 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1654 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1655 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1656 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1659 /* Fire off the draw itself */
1660 panfrost_queue_draw(ctx
);
1662 /* Increment transform feedback offsets */
1664 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1665 unsigned output_count
= u_stream_outputs_for_vertices(
1666 ctx
->active_prim
, ctx
->vertex_count
);
1668 ctx
->streamout
.offsets
[i
] += output_count
;
1675 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1681 panfrost_create_rasterizer_state(
1682 struct pipe_context
*pctx
,
1683 const struct pipe_rasterizer_state
*cso
)
1685 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1689 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1690 so
->tiler_gl_enables
= 0x7;
1693 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1695 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1696 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1698 if (cso
->cull_face
& PIPE_FACE_BACK
)
1699 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1705 panfrost_bind_rasterizer_state(
1706 struct pipe_context
*pctx
,
1709 struct panfrost_context
*ctx
= pan_context(pctx
);
1711 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1715 ctx
->rasterizer
= hwcso
;
1716 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1718 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1719 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1721 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1722 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1724 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1726 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1727 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1729 /* Point sprites are emulated */
1731 struct panfrost_shader_state
*variant
=
1732 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1734 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1735 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1739 panfrost_create_vertex_elements_state(
1740 struct pipe_context
*pctx
,
1741 unsigned num_elements
,
1742 const struct pipe_vertex_element
*elements
)
1744 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1746 so
->num_elements
= num_elements
;
1747 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1749 for (int i
= 0; i
< num_elements
; ++i
) {
1750 so
->hw
[i
].index
= i
;
1752 enum pipe_format fmt
= elements
[i
].src_format
;
1753 const struct util_format_description
*desc
= util_format_description(fmt
);
1754 so
->hw
[i
].unknown1
= 0x2;
1755 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1757 so
->hw
[i
].format
= panfrost_find_format(desc
);
1759 /* The field itself should probably be shifted over */
1760 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1767 panfrost_bind_vertex_elements_state(
1768 struct pipe_context
*pctx
,
1771 struct panfrost_context
*ctx
= pan_context(pctx
);
1773 ctx
->vertex
= hwcso
;
1774 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1778 panfrost_create_shader_state(
1779 struct pipe_context
*pctx
,
1780 const struct pipe_shader_state
*cso
)
1782 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1785 /* Token deep copy to prevent memory corruption */
1787 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1788 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1794 panfrost_delete_shader_state(
1795 struct pipe_context
*pctx
,
1798 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1800 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1801 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1804 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1805 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1806 panfrost_bo_unreference(shader_state
->bo
);
1807 shader_state
->bo
= NULL
;
1814 panfrost_create_sampler_state(
1815 struct pipe_context
*pctx
,
1816 const struct pipe_sampler_state
*cso
)
1818 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1821 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1823 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1824 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1825 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1827 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1828 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1829 unsigned mip_filter
= mip_linear
?
1830 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1831 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1833 struct mali_sampler_descriptor sampler_descriptor
= {
1834 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1835 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1836 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1837 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1838 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1840 cso
->border_color
.f
[0],
1841 cso
->border_color
.f
[1],
1842 cso
->border_color
.f
[2],
1843 cso
->border_color
.f
[3]
1845 .min_lod
= FIXED_16(cso
->min_lod
),
1846 .max_lod
= FIXED_16(cso
->max_lod
),
1847 .seamless_cube_map
= cso
->seamless_cube_map
,
1850 /* If necessary, we disable mipmapping in the sampler descriptor by
1851 * clamping the LOD as tight as possible (from 0 to epsilon,
1852 * essentially -- remember these are fixed point numbers, so
1855 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1856 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1858 /* Enforce that there is something in the middle by adding epsilon*/
1860 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1861 sampler_descriptor
.max_lod
++;
1864 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1866 so
->hw
= sampler_descriptor
;
1872 panfrost_bind_sampler_states(
1873 struct pipe_context
*pctx
,
1874 enum pipe_shader_type shader
,
1875 unsigned start_slot
, unsigned num_sampler
,
1878 assert(start_slot
== 0);
1880 struct panfrost_context
*ctx
= pan_context(pctx
);
1882 /* XXX: Should upload, not just copy? */
1883 ctx
->sampler_count
[shader
] = num_sampler
;
1884 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1886 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1890 panfrost_variant_matches(
1891 struct panfrost_context
*ctx
,
1892 struct panfrost_shader_state
*variant
,
1893 enum pipe_shader_type type
)
1895 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1896 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1898 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1900 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1901 /* Make sure enable state is at least the same */
1902 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1906 /* Check that the contents of the test are the same */
1907 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1908 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1910 if (!(same_func
&& same_ref
)) {
1915 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1916 variant
->point_sprite_mask
)) {
1917 /* Ensure the same varyings are turned to point sprites */
1918 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1921 /* Ensure the orientation is correct */
1923 rasterizer
->sprite_coord_mode
==
1924 PIPE_SPRITE_COORD_UPPER_LEFT
;
1926 if (variant
->point_sprite_upper_left
!= upper_left
)
1930 /* Otherwise, we're good to go */
1935 * Fix an uncompiled shader's stream output info, and produce a bitmask
1936 * of which VARYING_SLOT_* are captured for stream output.
1938 * Core Gallium stores output->register_index as a "slot" number, where
1939 * slots are assigned consecutively to all outputs in info->outputs_written.
1940 * This naive packing of outputs doesn't work for us - we too have slots,
1941 * but the layout is defined by the VUE map, which we won't have until we
1942 * compile a specific shader variant. So, we remap these and simply store
1943 * VARYING_SLOT_* in our copy's output->register_index fields.
1945 * We then produce a bitmask of outputs which are used for SO.
1947 * Implementation from iris.
1951 update_so_info(struct pipe_stream_output_info
*so_info
,
1952 uint64_t outputs_written
)
1954 uint64_t so_outputs
= 0;
1955 uint8_t reverse_map
[64] = {};
1958 while (outputs_written
)
1959 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1961 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1962 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1964 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1965 output
->register_index
= reverse_map
[output
->register_index
];
1967 so_outputs
|= 1ull << output
->register_index
;
1974 panfrost_bind_shader_state(
1975 struct pipe_context
*pctx
,
1977 enum pipe_shader_type type
)
1979 struct panfrost_context
*ctx
= pan_context(pctx
);
1981 ctx
->shader
[type
] = hwcso
;
1983 if (type
== PIPE_SHADER_FRAGMENT
)
1984 ctx
->dirty
|= PAN_DIRTY_FS
;
1986 ctx
->dirty
|= PAN_DIRTY_VS
;
1990 /* Match the appropriate variant */
1992 signed variant
= -1;
1993 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1995 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1996 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
2002 if (variant
== -1) {
2003 /* No variant matched, so create a new one */
2004 variant
= variants
->variant_count
++;
2005 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2007 struct panfrost_shader_state
*v
=
2008 &variants
->variants
[variant
];
2010 if (type
== PIPE_SHADER_FRAGMENT
) {
2011 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
2013 if (ctx
->rasterizer
) {
2014 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
2015 v
->point_sprite_upper_left
=
2016 ctx
->rasterizer
->base
.sprite_coord_mode
==
2017 PIPE_SPRITE_COORD_UPPER_LEFT
;
2021 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
2025 /* Select this variant */
2026 variants
->active_variant
= variant
;
2028 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2029 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2031 /* We finally have a variant, so compile it */
2033 if (!shader_state
->compiled
) {
2034 uint64_t outputs_written
= 0;
2036 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
2037 variants
->base
.type
,
2038 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
2039 variants
->base
.ir
.nir
:
2040 variants
->base
.tokens
,
2041 tgsi_processor_to_shader_stage(type
), shader_state
,
2044 shader_state
->compiled
= true;
2046 /* Fixup the stream out information, since what Gallium returns
2047 * normally is mildly insane */
2049 shader_state
->stream_output
= variants
->base
.stream_output
;
2050 shader_state
->so_mask
=
2051 update_so_info(&shader_state
->stream_output
, outputs_written
);
2056 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2058 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2062 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2064 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2068 panfrost_set_vertex_buffers(
2069 struct pipe_context
*pctx
,
2070 unsigned start_slot
,
2071 unsigned num_buffers
,
2072 const struct pipe_vertex_buffer
*buffers
)
2074 struct panfrost_context
*ctx
= pan_context(pctx
);
2076 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2080 panfrost_set_constant_buffer(
2081 struct pipe_context
*pctx
,
2082 enum pipe_shader_type shader
, uint index
,
2083 const struct pipe_constant_buffer
*buf
)
2085 struct panfrost_context
*ctx
= pan_context(pctx
);
2086 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2088 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2090 unsigned mask
= (1 << index
);
2092 if (unlikely(!buf
)) {
2093 pbuf
->enabled_mask
&= ~mask
;
2094 pbuf
->dirty_mask
&= ~mask
;
2098 pbuf
->enabled_mask
|= mask
;
2099 pbuf
->dirty_mask
|= mask
;
2103 panfrost_set_stencil_ref(
2104 struct pipe_context
*pctx
,
2105 const struct pipe_stencil_ref
*ref
)
2107 struct panfrost_context
*ctx
= pan_context(pctx
);
2108 ctx
->stencil_ref
= *ref
;
2110 /* Shader core dirty */
2111 ctx
->dirty
|= PAN_DIRTY_FS
;
2114 static enum mali_texture_type
2115 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2119 case PIPE_TEXTURE_1D
:
2120 case PIPE_TEXTURE_1D_ARRAY
:
2123 case PIPE_TEXTURE_2D
:
2124 case PIPE_TEXTURE_2D_ARRAY
:
2125 case PIPE_TEXTURE_RECT
:
2128 case PIPE_TEXTURE_3D
:
2131 case PIPE_TEXTURE_CUBE
:
2132 case PIPE_TEXTURE_CUBE_ARRAY
:
2133 return MALI_TEX_CUBE
;
2136 unreachable("Unknown target");
2140 static struct pipe_sampler_view
*
2141 panfrost_create_sampler_view(
2142 struct pipe_context
*pctx
,
2143 struct pipe_resource
*texture
,
2144 const struct pipe_sampler_view
*template)
2146 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2147 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2149 pipe_reference(NULL
, &texture
->reference
);
2151 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2154 so
->base
= *template;
2155 so
->base
.texture
= texture
;
2156 so
->base
.reference
.count
= 1;
2157 so
->base
.context
= pctx
;
2159 /* sampler_views correspond to texture descriptors, minus the texture
2160 * (data) itself. So, we serialise the descriptor here and cache it for
2163 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2165 unsigned char user_swizzle
[4] = {
2166 template->swizzle_r
,
2167 template->swizzle_g
,
2168 template->swizzle_b
,
2172 enum mali_format format
= panfrost_find_format(desc
);
2174 /* Check if we need to set a custom stride by computing the "expected"
2175 * stride and comparing it to what the BO actually wants. Only applies
2176 * to linear textures, since tiled/compressed textures have strict
2177 * alignment requirements for their strides as it is */
2179 unsigned first_level
= template->u
.tex
.first_level
;
2180 unsigned last_level
= template->u
.tex
.last_level
;
2182 if (prsrc
->layout
== PAN_LINEAR
) {
2183 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2184 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2185 unsigned width
= u_minify(texture
->width0
, l
);
2186 unsigned comp_stride
= width
* bytes_per_pixel
;
2188 if (comp_stride
!= actual_stride
) {
2189 so
->manual_stride
= true;
2195 /* In the hardware, array_size refers specifically to array textures,
2196 * whereas in Gallium, it also covers cubemaps */
2198 unsigned array_size
= texture
->array_size
;
2200 if (template->target
== PIPE_TEXTURE_CUBE
) {
2201 /* TODO: Cubemap arrays */
2202 assert(array_size
== 6);
2206 struct mali_texture_descriptor texture_descriptor
= {
2207 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2208 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2209 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2210 .array_size
= MALI_POSITIVE(array_size
),
2213 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2215 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2216 .type
= panfrost_translate_texture_type(template->target
),
2220 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2223 texture_descriptor
.levels
= last_level
- first_level
;
2225 so
->hw
= texture_descriptor
;
2227 return (struct pipe_sampler_view
*) so
;
2231 panfrost_set_sampler_views(
2232 struct pipe_context
*pctx
,
2233 enum pipe_shader_type shader
,
2234 unsigned start_slot
, unsigned num_views
,
2235 struct pipe_sampler_view
**views
)
2237 struct panfrost_context
*ctx
= pan_context(pctx
);
2239 assert(start_slot
== 0);
2241 unsigned new_nr
= 0;
2242 for (unsigned i
= 0; i
< num_views
; ++i
) {
2247 ctx
->sampler_view_count
[shader
] = new_nr
;
2248 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2250 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2254 panfrost_sampler_view_destroy(
2255 struct pipe_context
*pctx
,
2256 struct pipe_sampler_view
*view
)
2258 pipe_resource_reference(&view
->texture
, NULL
);
2263 panfrost_set_shader_buffers(
2264 struct pipe_context
*pctx
,
2265 enum pipe_shader_type shader
,
2266 unsigned start
, unsigned count
,
2267 const struct pipe_shader_buffer
*buffers
,
2268 unsigned writable_bitmask
)
2270 struct panfrost_context
*ctx
= pan_context(pctx
);
2272 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2273 buffers
, start
, count
);
2276 /* Hints that a framebuffer should use AFBC where possible */
2280 struct panfrost_screen
*screen
,
2281 const struct pipe_framebuffer_state
*fb
)
2283 /* AFBC implemenation incomplete; hide it */
2284 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2286 /* Hint AFBC to the resources bound to each color buffer */
2288 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2289 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2290 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2291 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2294 /* Also hint it to the depth buffer */
2297 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2298 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2303 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2304 const struct pipe_framebuffer_state
*fb
)
2306 struct panfrost_context
*ctx
= pan_context(pctx
);
2308 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
2309 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2311 panfrost_invalidate_frame(ctx
);
2315 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2316 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2318 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2322 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2325 struct panfrost_context
*ctx
= pan_context(pipe
);
2326 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2327 ctx
->depth_stencil
= depth_stencil
;
2332 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2333 * emulated in the fragment shader */
2335 if (depth_stencil
->alpha
.enabled
) {
2336 /* We need to trigger a new shader (maybe) */
2337 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2341 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2343 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2344 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2346 /* If back-stencil is not enabled, use the front values */
2347 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2348 unsigned back_index
= back_enab
? 1 : 0;
2350 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2351 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2353 /* Depth state (TODO: Refactor) */
2354 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_WRITEMASK
,
2355 depth_stencil
->depth
.writemask
);
2357 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2359 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2360 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2362 /* Bounds test not implemented */
2363 assert(!depth_stencil
->depth
.bounds_test
);
2365 ctx
->dirty
|= PAN_DIRTY_FS
;
2369 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2375 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2376 unsigned sample_mask
)
2381 panfrost_set_clip_state(struct pipe_context
*pipe
,
2382 const struct pipe_clip_state
*clip
)
2384 //struct panfrost_context *panfrost = pan_context(pipe);
2388 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2389 unsigned start_slot
,
2390 unsigned num_viewports
,
2391 const struct pipe_viewport_state
*viewports
)
2393 struct panfrost_context
*ctx
= pan_context(pipe
);
2395 assert(start_slot
== 0);
2396 assert(num_viewports
== 1);
2398 ctx
->pipe_viewport
= *viewports
;
2402 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2403 unsigned start_slot
,
2404 unsigned num_scissors
,
2405 const struct pipe_scissor_state
*scissors
)
2407 struct panfrost_context
*ctx
= pan_context(pipe
);
2409 assert(start_slot
== 0);
2410 assert(num_scissors
== 1);
2412 ctx
->scissor
= *scissors
;
2416 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2417 const struct pipe_poly_stipple
*stipple
)
2419 //struct panfrost_context *panfrost = pan_context(pipe);
2423 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2426 struct panfrost_context
*ctx
= pan_context(pipe
);
2427 ctx
->active_queries
= enable
;
2431 panfrost_destroy(struct pipe_context
*pipe
)
2433 struct panfrost_context
*panfrost
= pan_context(pipe
);
2435 if (panfrost
->blitter
)
2436 util_blitter_destroy(panfrost
->blitter
);
2438 if (panfrost
->blitter_wallpaper
)
2439 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2444 static struct pipe_query
*
2445 panfrost_create_query(struct pipe_context
*pipe
,
2449 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2454 return (struct pipe_query
*) q
;
2458 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2460 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2463 panfrost_bo_unreference(query
->bo
);
2471 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2473 struct panfrost_context
*ctx
= pan_context(pipe
);
2474 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2476 switch (query
->type
) {
2477 case PIPE_QUERY_OCCLUSION_COUNTER
:
2478 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2479 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2480 /* Allocate a bo for the query results to be stored */
2482 query
->bo
= panfrost_bo_create(
2483 pan_screen(ctx
->base
.screen
),
2484 sizeof(unsigned), 0);
2487 unsigned *result
= (unsigned *)query
->bo
->cpu
;
2488 *result
= 0; /* Default to 0 if nothing at all drawn. */
2489 ctx
->occlusion_query
= query
;
2492 /* Geometry statistics are computed in the driver. XXX: geom/tess
2495 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2496 query
->start
= ctx
->prims_generated
;
2498 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2499 query
->start
= ctx
->tf_prims_generated
;
2503 fprintf(stderr
, "Skipping query %u\n", query
->type
);
2511 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2513 struct panfrost_context
*ctx
= pan_context(pipe
);
2514 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2516 switch (query
->type
) {
2517 case PIPE_QUERY_OCCLUSION_COUNTER
:
2518 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2519 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2520 ctx
->occlusion_query
= NULL
;
2522 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2523 query
->end
= ctx
->prims_generated
;
2525 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2526 query
->end
= ctx
->tf_prims_generated
;
2534 panfrost_get_query_result(struct pipe_context
*pipe
,
2535 struct pipe_query
*q
,
2537 union pipe_query_result
*vresult
)
2539 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2540 struct panfrost_context
*ctx
= pan_context(pipe
);
2543 switch (query
->type
) {
2544 case PIPE_QUERY_OCCLUSION_COUNTER
:
2545 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2546 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2548 panfrost_flush_all_batches(ctx
, true);
2550 /* Read back the query results */
2551 unsigned *result
= (unsigned *) query
->bo
->cpu
;
2552 unsigned passed
= *result
;
2554 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2555 vresult
->u64
= passed
;
2557 vresult
->b
= !!passed
;
2562 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2563 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2564 panfrost_flush_all_batches(ctx
, true);
2565 vresult
->u64
= query
->end
- query
->start
;
2569 DBG("Skipped query get %u\n", query
->type
);
2576 static struct pipe_stream_output_target
*
2577 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2578 struct pipe_resource
*prsc
,
2579 unsigned buffer_offset
,
2580 unsigned buffer_size
)
2582 struct pipe_stream_output_target
*target
;
2584 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2589 pipe_reference_init(&target
->reference
, 1);
2590 pipe_resource_reference(&target
->buffer
, prsc
);
2592 target
->context
= pctx
;
2593 target
->buffer_offset
= buffer_offset
;
2594 target
->buffer_size
= buffer_size
;
2600 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2601 struct pipe_stream_output_target
*target
)
2603 pipe_resource_reference(&target
->buffer
, NULL
);
2604 ralloc_free(target
);
2608 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2609 unsigned num_targets
,
2610 struct pipe_stream_output_target
**targets
,
2611 const unsigned *offsets
)
2613 struct panfrost_context
*ctx
= pan_context(pctx
);
2614 struct panfrost_streamout
*so
= &ctx
->streamout
;
2616 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2618 for (unsigned i
= 0; i
< num_targets
; i
++) {
2619 if (offsets
[i
] != -1)
2620 so
->offsets
[i
] = offsets
[i
];
2622 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2625 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2626 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2628 so
->num_targets
= num_targets
;
2631 struct pipe_context
*
2632 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2634 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2635 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2636 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2638 gallium
->screen
= screen
;
2640 gallium
->destroy
= panfrost_destroy
;
2642 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2644 gallium
->flush
= panfrost_flush
;
2645 gallium
->clear
= panfrost_clear
;
2646 gallium
->draw_vbo
= panfrost_draw_vbo
;
2648 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2649 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2650 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2652 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2654 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2655 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2656 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2658 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2659 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2660 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2662 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2663 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2664 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2666 gallium
->create_fs_state
= panfrost_create_shader_state
;
2667 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2668 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2670 gallium
->create_vs_state
= panfrost_create_shader_state
;
2671 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2672 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2674 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2675 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2676 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2678 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2679 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2680 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2682 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2684 gallium
->set_clip_state
= panfrost_set_clip_state
;
2685 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2686 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2687 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2688 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2690 gallium
->create_query
= panfrost_create_query
;
2691 gallium
->destroy_query
= panfrost_destroy_query
;
2692 gallium
->begin_query
= panfrost_begin_query
;
2693 gallium
->end_query
= panfrost_end_query
;
2694 gallium
->get_query_result
= panfrost_get_query_result
;
2696 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2697 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2698 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2700 panfrost_resource_context_init(gallium
);
2701 panfrost_blend_context_init(gallium
);
2702 panfrost_compute_context_init(gallium
);
2705 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2706 gallium
->const_uploader
= gallium
->stream_uploader
;
2707 assert(gallium
->stream_uploader
);
2709 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2710 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2712 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2714 ctx
->blitter
= util_blitter_create(gallium
);
2715 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2717 assert(ctx
->blitter
);
2718 assert(ctx
->blitter_wallpaper
);
2720 /* Prepare for render! */
2722 panfrost_batch_init(ctx
);
2723 panfrost_emit_vertex_payload(ctx
);
2724 panfrost_emit_tiler_payload(ctx
);
2725 panfrost_invalidate_frame(ctx
);
2726 panfrost_default_shader_backend(ctx
);