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panfrost: Guard vertex upload by ctx->vertex != NULL
[mesa.git] / src / gallium / drivers / panfrost / pan_context.c
1 /*
2 * © Copyright 2018 Alyssa Rosenzweig
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 */
24
25 #include <sys/poll.h>
26 #include <errno.h>
27
28 #include "pan_context.h"
29 #include "pan_format.h"
30
31 #include "util/macros.h"
32 #include "util/u_format.h"
33 #include "util/u_inlines.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_memory.h"
36 #include "util/u_vbuf.h"
37 #include "util/half_float.h"
38 #include "util/u_helpers.h"
39 #include "util/u_format.h"
40 #include "util/u_prim_restart.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "util/u_math.h"
44
45 #include "pan_screen.h"
46 #include "pan_blending.h"
47 #include "pan_blend_shaders.h"
48 #include "pan_util.h"
49 #include "pan_tiler.h"
50
51 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
52 //#define DRY_RUN
53
54 static enum mali_job_type
55 panfrost_job_type_for_pipe(enum pipe_shader_type type) {
56 switch (type)
57 {
58 case PIPE_SHADER_VERTEX:
59 return JOB_TYPE_VERTEX;
60
61 case PIPE_SHADER_FRAGMENT:
62 /* Note: JOB_TYPE_FRAGMENT is different.
63 * JOB_TYPE_FRAGMENT actually executes the
64 * fragment shader, but JOB_TYPE_TILER is how you
65 * specify it*/
66 return JOB_TYPE_TILER;
67
68 case PIPE_SHADER_GEOMETRY:
69 return JOB_TYPE_GEOMETRY;
70
71 case PIPE_SHADER_COMPUTE:
72 return JOB_TYPE_COMPUTE;
73
74 default:
75 unreachable("Unsupported shader stage");
76 }
77 }
78
79 /* Framebuffer descriptor */
80
81 static struct midgard_tiler_descriptor
82 panfrost_emit_midg_tiler(
83 struct panfrost_context *ctx,
84 unsigned width,
85 unsigned height,
86 unsigned vertex_count)
87 {
88 struct midgard_tiler_descriptor t = {};
89
90 t.hierarchy_mask =
91 panfrost_choose_hierarchy_mask(width, height, vertex_count);
92
93 /* Compute the polygon header size and use that to offset the body */
94
95 unsigned header_size = panfrost_tiler_header_size(
96 width, height, t.hierarchy_mask);
97
98 unsigned body_size = panfrost_tiler_body_size(
99 width, height, t.hierarchy_mask);
100
101 /* Sanity check */
102
103 if (t.hierarchy_mask) {
104 assert(ctx->tiler_polygon_list.bo->size >= (header_size + body_size));
105
106 /* Specify allocated tiler structures */
107 t.polygon_list = ctx->tiler_polygon_list.bo->gpu;
108
109 /* Allow the entire tiler heap */
110 t.heap_start = ctx->tiler_heap.bo->gpu;
111 t.heap_end =
112 ctx->tiler_heap.bo->gpu + ctx->tiler_heap.bo->size;
113 } else {
114 /* The tiler is disabled, so don't allow the tiler heap */
115 t.heap_start = ctx->tiler_heap.bo->gpu;
116 t.heap_end = t.heap_start;
117
118 /* Use a dummy polygon list */
119 t.polygon_list = ctx->tiler_dummy.bo->gpu;
120
121 /* Also, set a "tiler disabled?" flag? */
122 t.hierarchy_mask |= 0x1000;
123 }
124
125 t.polygon_list_body =
126 t.polygon_list + header_size;
127
128 t.polygon_list_size =
129 header_size + body_size;
130
131 return t;
132 }
133
134 struct mali_single_framebuffer
135 panfrost_emit_sfbd(struct panfrost_context *ctx, unsigned vertex_count)
136 {
137 unsigned width = ctx->pipe_framebuffer.width;
138 unsigned height = ctx->pipe_framebuffer.height;
139
140 struct mali_single_framebuffer framebuffer = {
141 .width = MALI_POSITIVE(width),
142 .height = MALI_POSITIVE(height),
143 .unknown2 = 0x1f,
144 .format = 0x30000000,
145 .clear_flags = 0x1000,
146 .unknown_address_0 = ctx->scratchpad.bo->gpu,
147 .tiler = panfrost_emit_midg_tiler(ctx,
148 width, height, vertex_count),
149 };
150
151 return framebuffer;
152 }
153
154 struct bifrost_framebuffer
155 panfrost_emit_mfbd(struct panfrost_context *ctx, unsigned vertex_count)
156 {
157 unsigned width = ctx->pipe_framebuffer.width;
158 unsigned height = ctx->pipe_framebuffer.height;
159
160 struct bifrost_framebuffer framebuffer = {
161 .unk0 = 0x1e5, /* 1e4 if no spill */
162 .width1 = MALI_POSITIVE(width),
163 .height1 = MALI_POSITIVE(height),
164 .width2 = MALI_POSITIVE(width),
165 .height2 = MALI_POSITIVE(height),
166
167 .unk1 = 0x1080,
168
169 .rt_count_1 = MALI_POSITIVE(ctx->pipe_framebuffer.nr_cbufs),
170 .rt_count_2 = 4,
171
172 .unknown2 = 0x1f,
173
174 .scratchpad = ctx->scratchpad.bo->gpu,
175 .tiler = panfrost_emit_midg_tiler(ctx,
176 width, height, vertex_count)
177 };
178
179 return framebuffer;
180 }
181
182 /* Are we currently rendering to the screen (rather than an FBO)? */
183
184 bool
185 panfrost_is_scanout(struct panfrost_context *ctx)
186 {
187 /* If there is no color buffer, it's an FBO */
188 if (ctx->pipe_framebuffer.nr_cbufs != 1)
189 return false;
190
191 /* If we're too early that no framebuffer was sent, it's scanout */
192 if (!ctx->pipe_framebuffer.cbufs[0])
193 return true;
194
195 return ctx->pipe_framebuffer.cbufs[0]->texture->bind & PIPE_BIND_DISPLAY_TARGET ||
196 ctx->pipe_framebuffer.cbufs[0]->texture->bind & PIPE_BIND_SCANOUT ||
197 ctx->pipe_framebuffer.cbufs[0]->texture->bind & PIPE_BIND_SHARED;
198 }
199
200 static void
201 panfrost_clear(
202 struct pipe_context *pipe,
203 unsigned buffers,
204 const union pipe_color_union *color,
205 double depth, unsigned stencil)
206 {
207 struct panfrost_context *ctx = pan_context(pipe);
208 struct panfrost_job *job = panfrost_get_job_for_fbo(ctx);
209
210 panfrost_job_clear(ctx, job, buffers, color, depth, stencil);
211 }
212
213 static mali_ptr
214 panfrost_attach_vt_mfbd(struct panfrost_context *ctx)
215 {
216 return panfrost_upload_transient(ctx, &ctx->vt_framebuffer_mfbd, sizeof(ctx->vt_framebuffer_mfbd)) | MALI_MFBD;
217 }
218
219 static mali_ptr
220 panfrost_attach_vt_sfbd(struct panfrost_context *ctx)
221 {
222 return panfrost_upload_transient(ctx, &ctx->vt_framebuffer_sfbd, sizeof(ctx->vt_framebuffer_sfbd)) | MALI_SFBD;
223 }
224
225 static void
226 panfrost_attach_vt_framebuffer(struct panfrost_context *ctx, bool skippable)
227 {
228 /* Skip the attach if we can */
229
230 if (skippable && ctx->payloads[PIPE_SHADER_VERTEX].postfix.framebuffer) {
231 assert(ctx->payloads[PIPE_SHADER_FRAGMENT].postfix.framebuffer);
232 return;
233 }
234
235 struct panfrost_screen *screen = pan_screen(ctx->base.screen);
236 mali_ptr framebuffer = screen->require_sfbd ?
237 panfrost_attach_vt_sfbd(ctx) :
238 panfrost_attach_vt_mfbd(ctx);
239
240 for (unsigned i = 0; i < PIPE_SHADER_TYPES; ++i)
241 ctx->payloads[i].postfix.framebuffer = framebuffer;
242 }
243
244 /* Reset per-frame context, called on context initialisation as well as after
245 * flushing a frame */
246
247 static void
248 panfrost_invalidate_frame(struct panfrost_context *ctx)
249 {
250 struct panfrost_screen *screen = pan_screen(ctx->base.screen);
251
252 if (screen->require_sfbd)
253 ctx->vt_framebuffer_sfbd = panfrost_emit_sfbd(ctx, ~0);
254 else
255 ctx->vt_framebuffer_mfbd = panfrost_emit_mfbd(ctx, ~0);
256
257 for (unsigned i = 0; i < PIPE_SHADER_TYPES; ++i)
258 ctx->payloads[i].postfix.framebuffer = 0;
259
260 if (ctx->rasterizer)
261 ctx->dirty |= PAN_DIRTY_RASTERIZER;
262
263 /* XXX */
264 ctx->dirty |= PAN_DIRTY_SAMPLERS | PAN_DIRTY_TEXTURES;
265 }
266
267 /* In practice, every field of these payloads should be configurable
268 * arbitrarily, which means these functions are basically catch-all's for
269 * as-of-yet unwavering unknowns */
270
271 static void
272 panfrost_emit_vertex_payload(struct panfrost_context *ctx)
273 {
274 /* 0x2 bit clear on 32-bit T6XX */
275
276 struct midgard_payload_vertex_tiler payload = {
277 .gl_enables = 0x4 | 0x2,
278 };
279
280 /* Vertex and compute are closely coupled, so share a payload */
281
282 memcpy(&ctx->payloads[PIPE_SHADER_VERTEX], &payload, sizeof(payload));
283 memcpy(&ctx->payloads[PIPE_SHADER_COMPUTE], &payload, sizeof(payload));
284 }
285
286 static void
287 panfrost_emit_tiler_payload(struct panfrost_context *ctx)
288 {
289 struct midgard_payload_vertex_tiler payload = {
290 .prefix = {
291 .zero1 = 0xffff, /* Why is this only seen on test-quad-textured? */
292 },
293 };
294
295 memcpy(&ctx->payloads[PIPE_SHADER_FRAGMENT], &payload, sizeof(payload));
296 }
297
298 static unsigned
299 translate_tex_wrap(enum pipe_tex_wrap w)
300 {
301 switch (w) {
302 case PIPE_TEX_WRAP_REPEAT:
303 return MALI_WRAP_REPEAT;
304
305 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
306 return MALI_WRAP_CLAMP_TO_EDGE;
307
308 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
309 return MALI_WRAP_CLAMP_TO_BORDER;
310
311 case PIPE_TEX_WRAP_MIRROR_REPEAT:
312 return MALI_WRAP_MIRRORED_REPEAT;
313
314 default:
315 unreachable("Invalid wrap");
316 }
317 }
318
319 static unsigned
320 panfrost_translate_compare_func(enum pipe_compare_func in)
321 {
322 switch (in) {
323 case PIPE_FUNC_NEVER:
324 return MALI_FUNC_NEVER;
325
326 case PIPE_FUNC_LESS:
327 return MALI_FUNC_LESS;
328
329 case PIPE_FUNC_EQUAL:
330 return MALI_FUNC_EQUAL;
331
332 case PIPE_FUNC_LEQUAL:
333 return MALI_FUNC_LEQUAL;
334
335 case PIPE_FUNC_GREATER:
336 return MALI_FUNC_GREATER;
337
338 case PIPE_FUNC_NOTEQUAL:
339 return MALI_FUNC_NOTEQUAL;
340
341 case PIPE_FUNC_GEQUAL:
342 return MALI_FUNC_GEQUAL;
343
344 case PIPE_FUNC_ALWAYS:
345 return MALI_FUNC_ALWAYS;
346
347 default:
348 unreachable("Invalid func");
349 }
350 }
351
352 static unsigned
353 panfrost_translate_alt_compare_func(enum pipe_compare_func in)
354 {
355 switch (in) {
356 case PIPE_FUNC_NEVER:
357 return MALI_ALT_FUNC_NEVER;
358
359 case PIPE_FUNC_LESS:
360 return MALI_ALT_FUNC_LESS;
361
362 case PIPE_FUNC_EQUAL:
363 return MALI_ALT_FUNC_EQUAL;
364
365 case PIPE_FUNC_LEQUAL:
366 return MALI_ALT_FUNC_LEQUAL;
367
368 case PIPE_FUNC_GREATER:
369 return MALI_ALT_FUNC_GREATER;
370
371 case PIPE_FUNC_NOTEQUAL:
372 return MALI_ALT_FUNC_NOTEQUAL;
373
374 case PIPE_FUNC_GEQUAL:
375 return MALI_ALT_FUNC_GEQUAL;
376
377 case PIPE_FUNC_ALWAYS:
378 return MALI_ALT_FUNC_ALWAYS;
379
380 default:
381 unreachable("Invalid alt func");
382 }
383 }
384
385 static unsigned
386 panfrost_translate_stencil_op(enum pipe_stencil_op in)
387 {
388 switch (in) {
389 case PIPE_STENCIL_OP_KEEP:
390 return MALI_STENCIL_KEEP;
391
392 case PIPE_STENCIL_OP_ZERO:
393 return MALI_STENCIL_ZERO;
394
395 case PIPE_STENCIL_OP_REPLACE:
396 return MALI_STENCIL_REPLACE;
397
398 case PIPE_STENCIL_OP_INCR:
399 return MALI_STENCIL_INCR;
400
401 case PIPE_STENCIL_OP_DECR:
402 return MALI_STENCIL_DECR;
403
404 case PIPE_STENCIL_OP_INCR_WRAP:
405 return MALI_STENCIL_INCR_WRAP;
406
407 case PIPE_STENCIL_OP_DECR_WRAP:
408 return MALI_STENCIL_DECR_WRAP;
409
410 case PIPE_STENCIL_OP_INVERT:
411 return MALI_STENCIL_INVERT;
412
413 default:
414 unreachable("Invalid stencil op");
415 }
416 }
417
418 static void
419 panfrost_make_stencil_state(const struct pipe_stencil_state *in, struct mali_stencil_test *out)
420 {
421 out->ref = 0; /* Gallium gets it from elsewhere */
422
423 out->mask = in->valuemask;
424 out->func = panfrost_translate_compare_func(in->func);
425 out->sfail = panfrost_translate_stencil_op(in->fail_op);
426 out->dpfail = panfrost_translate_stencil_op(in->zfail_op);
427 out->dppass = panfrost_translate_stencil_op(in->zpass_op);
428 }
429
430 static void
431 panfrost_default_shader_backend(struct panfrost_context *ctx)
432 {
433 struct mali_shader_meta shader = {
434 .alpha_coverage = ~MALI_ALPHA_COVERAGE(0.000000),
435
436 .unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x3010,
437 .unknown2_4 = MALI_NO_MSAA | 0x4e0,
438 };
439
440 /* unknown2_4 has 0x10 bit set on T6XX. We don't know why this is
441 * required (independent of 32-bit/64-bit descriptors), or why it's not
442 * used on later GPU revisions. Otherwise, all shader jobs fault on
443 * these earlier chips (perhaps this is a chicken bit of some kind).
444 * More investigation is needed. */
445
446 if (ctx->is_t6xx) {
447 shader.unknown2_4 |= 0x10;
448 }
449
450 struct pipe_stencil_state default_stencil = {
451 .enabled = 0,
452 .func = PIPE_FUNC_ALWAYS,
453 .fail_op = MALI_STENCIL_KEEP,
454 .zfail_op = MALI_STENCIL_KEEP,
455 .zpass_op = MALI_STENCIL_KEEP,
456 .writemask = 0xFF,
457 .valuemask = 0xFF
458 };
459
460 panfrost_make_stencil_state(&default_stencil, &shader.stencil_front);
461 shader.stencil_mask_front = default_stencil.writemask;
462
463 panfrost_make_stencil_state(&default_stencil, &shader.stencil_back);
464 shader.stencil_mask_back = default_stencil.writemask;
465
466 if (default_stencil.enabled)
467 shader.unknown2_4 |= MALI_STENCIL_TEST;
468
469 memcpy(&ctx->fragment_shader_core, &shader, sizeof(shader));
470 }
471
472 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
473 * graphics command stream. It should be called once per draw, accordding to
474 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
475 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
476 * vertex jobs. */
477
478 struct panfrost_transfer
479 panfrost_vertex_tiler_job(struct panfrost_context *ctx, bool is_tiler)
480 {
481 struct mali_job_descriptor_header job = {
482 .job_type = is_tiler ? JOB_TYPE_TILER : JOB_TYPE_VERTEX,
483 .job_descriptor_size = 1,
484 };
485
486 struct midgard_payload_vertex_tiler *payload = is_tiler ? &ctx->payloads[PIPE_SHADER_FRAGMENT] : &ctx->payloads[PIPE_SHADER_VERTEX];
487
488 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(job) + sizeof(*payload));
489 memcpy(transfer.cpu, &job, sizeof(job));
490 memcpy(transfer.cpu + sizeof(job), payload, sizeof(*payload));
491 return transfer;
492 }
493
494 static mali_ptr
495 panfrost_emit_varyings(
496 struct panfrost_context *ctx,
497 union mali_attr *slot,
498 unsigned stride,
499 unsigned count)
500 {
501 /* Fill out the descriptor */
502 slot->stride = stride;
503 slot->size = stride * count;
504 slot->shift = slot->extra_flags = 0;
505
506 struct panfrost_transfer transfer =
507 panfrost_allocate_transient(ctx, slot->size);
508
509 slot->elements = transfer.gpu | MALI_ATTR_LINEAR;
510
511 return transfer.gpu;
512 }
513
514 static void
515 panfrost_emit_point_coord(union mali_attr *slot)
516 {
517 slot->elements = MALI_VARYING_POINT_COORD | MALI_ATTR_LINEAR;
518 slot->stride = slot->size = slot->shift = slot->extra_flags = 0;
519 }
520
521 static void
522 panfrost_emit_front_face(union mali_attr *slot)
523 {
524 slot->elements = MALI_VARYING_FRONT_FACING | MALI_ATTR_INTERNAL;
525 }
526
527 static void
528 panfrost_emit_varying_descriptor(
529 struct panfrost_context *ctx,
530 unsigned vertex_count)
531 {
532 /* Load the shaders */
533
534 struct panfrost_shader_state *vs = &ctx->shader[PIPE_SHADER_VERTEX]->variants[ctx->shader[PIPE_SHADER_VERTEX]->active_variant];
535 struct panfrost_shader_state *fs = &ctx->shader[PIPE_SHADER_FRAGMENT]->variants[ctx->shader[PIPE_SHADER_FRAGMENT]->active_variant];
536 unsigned int num_gen_varyings = 0;
537
538 /* Allocate the varying descriptor */
539
540 size_t vs_size = sizeof(struct mali_attr_meta) * vs->tripipe->varying_count;
541 size_t fs_size = sizeof(struct mali_attr_meta) * fs->tripipe->varying_count;
542
543 struct panfrost_transfer trans = panfrost_allocate_transient(ctx,
544 vs_size + fs_size);
545
546 /*
547 * Assign ->src_offset now that we know about all the general purpose
548 * varyings that will be used by the fragment and vertex shaders.
549 */
550 for (unsigned i = 0; i < vs->tripipe->varying_count; i++) {
551 /*
552 * General purpose varyings have ->index set to 0, skip other
553 * entries.
554 */
555 if (vs->varyings[i].index)
556 continue;
557
558 vs->varyings[i].src_offset = 16 * (num_gen_varyings++);
559 }
560
561 for (unsigned i = 0; i < fs->tripipe->varying_count; i++) {
562 unsigned j;
563
564 /* If we have a point sprite replacement, handle that here. We
565 * have to translate location first. TODO: Flip y in shader.
566 * We're already keying ... just time crunch .. */
567
568 unsigned loc = fs->varyings_loc[i];
569 unsigned pnt_loc =
570 (loc >= VARYING_SLOT_VAR0) ? (loc - VARYING_SLOT_VAR0) :
571 (loc == VARYING_SLOT_PNTC) ? 8 :
572 ~0;
573
574 if (~pnt_loc && fs->point_sprite_mask & (1 << pnt_loc)) {
575 /* gl_PointCoord index by convention */
576 fs->varyings[i].index = 3;
577 fs->reads_point_coord = true;
578
579 /* Swizzle out the z/w to 0/1 */
580 fs->varyings[i].format = MALI_RG16F;
581 fs->varyings[i].swizzle =
582 panfrost_get_default_swizzle(2);
583
584 continue;
585 }
586
587 if (fs->varyings[i].index)
588 continue;
589
590 /*
591 * Re-use the VS general purpose varying pos if it exists,
592 * create a new one otherwise.
593 */
594 for (j = 0; j < vs->tripipe->varying_count; j++) {
595 if (fs->varyings_loc[i] == vs->varyings_loc[j])
596 break;
597 }
598
599 if (j < vs->tripipe->varying_count)
600 fs->varyings[i].src_offset = vs->varyings[j].src_offset;
601 else
602 fs->varyings[i].src_offset = 16 * (num_gen_varyings++);
603 }
604
605 memcpy(trans.cpu, vs->varyings, vs_size);
606 memcpy(trans.cpu + vs_size, fs->varyings, fs_size);
607
608 ctx->payloads[PIPE_SHADER_VERTEX].postfix.varying_meta = trans.gpu;
609 ctx->payloads[PIPE_SHADER_FRAGMENT].postfix.varying_meta = trans.gpu + vs_size;
610
611 /* Buffer indices must be in this order per our convention */
612 union mali_attr varyings[PIPE_MAX_ATTRIBS];
613 unsigned idx = 0;
614
615 panfrost_emit_varyings(ctx, &varyings[idx++], num_gen_varyings * 16,
616 vertex_count);
617
618 /* fp32 vec4 gl_Position */
619 ctx->payloads[PIPE_SHADER_FRAGMENT].postfix.position_varying =
620 panfrost_emit_varyings(ctx, &varyings[idx++],
621 sizeof(float) * 4, vertex_count);
622
623
624 if (vs->writes_point_size || fs->reads_point_coord) {
625 /* fp16 vec1 gl_PointSize */
626 ctx->payloads[PIPE_SHADER_FRAGMENT].primitive_size.pointer =
627 panfrost_emit_varyings(ctx, &varyings[idx++],
628 2, vertex_count);
629 } else if (fs->reads_face) {
630 /* Dummy to advance index */
631 ++idx;
632 }
633
634 if (fs->reads_point_coord) {
635 /* Special descriptor */
636 panfrost_emit_point_coord(&varyings[idx++]);
637 } else if (fs->reads_face) {
638 ++idx;
639 }
640
641 if (fs->reads_face) {
642 panfrost_emit_front_face(&varyings[idx++]);
643 }
644
645 mali_ptr varyings_p = panfrost_upload_transient(ctx, &varyings, idx * sizeof(union mali_attr));
646 ctx->payloads[PIPE_SHADER_VERTEX].postfix.varyings = varyings_p;
647 ctx->payloads[PIPE_SHADER_FRAGMENT].postfix.varyings = varyings_p;
648 }
649
650 mali_ptr
651 panfrost_vertex_buffer_address(struct panfrost_context *ctx, unsigned i)
652 {
653 struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[i];
654 struct panfrost_resource *rsrc = (struct panfrost_resource *) (buf->buffer.resource);
655
656 return rsrc->bo->gpu + buf->buffer_offset;
657 }
658
659 static bool
660 panfrost_writes_point_size(struct panfrost_context *ctx)
661 {
662 assert(ctx->shader[PIPE_SHADER_VERTEX]);
663 struct panfrost_shader_state *vs = &ctx->shader[PIPE_SHADER_VERTEX]->variants[ctx->shader[PIPE_SHADER_VERTEX]->active_variant];
664
665 return vs->writes_point_size && ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.draw_mode == MALI_POINTS;
666 }
667
668 /* Stage the attribute descriptors so we can adjust src_offset
669 * to let BOs align nicely */
670
671 static void
672 panfrost_stage_attributes(struct panfrost_context *ctx)
673 {
674 struct panfrost_vertex_state *so = ctx->vertex;
675
676 size_t sz = sizeof(struct mali_attr_meta) * so->num_elements;
677 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sz);
678 struct mali_attr_meta *target = (struct mali_attr_meta *) transfer.cpu;
679
680 /* Copy as-is for the first pass */
681 memcpy(target, so->hw, sz);
682
683 /* Fixup offsets for the second pass. Recall that the hardware
684 * calculates attribute addresses as:
685 *
686 * addr = base + (stride * vtx) + src_offset;
687 *
688 * However, on Mali, base must be aligned to 64-bytes, so we
689 * instead let:
690 *
691 * base' = base & ~63 = base - (base & 63)
692 *
693 * To compensate when using base' (see emit_vertex_data), we have
694 * to adjust src_offset by the masked off piece:
695 *
696 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
697 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
698 * = base + (stride * vtx) + src_offset
699 * = addr;
700 *
701 * QED.
702 */
703
704 unsigned start = ctx->payloads[PIPE_SHADER_VERTEX].draw_start;
705
706 for (unsigned i = 0; i < so->num_elements; ++i) {
707 unsigned vbi = so->pipe[i].vertex_buffer_index;
708 struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi];
709 mali_ptr addr = panfrost_vertex_buffer_address(ctx, vbi);
710
711 /* Adjust by the masked off bits of the offset */
712 target[i].src_offset += (addr & 63);
713
714 /* Also, somewhat obscurely per-instance data needs to be
715 * offset in response to a delayed start in an indexed draw */
716
717 if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start) {
718 target[i].src_offset -= buf->stride * start;
719 }
720
721
722 }
723
724 ctx->payloads[PIPE_SHADER_VERTEX].postfix.attribute_meta = transfer.gpu;
725 }
726
727 static void
728 panfrost_upload_sampler_descriptors(struct panfrost_context *ctx)
729 {
730 size_t desc_size = sizeof(struct mali_sampler_descriptor);
731
732 for (int t = 0; t <= PIPE_SHADER_FRAGMENT; ++t) {
733 mali_ptr upload = 0;
734
735 if (ctx->sampler_count[t] && ctx->sampler_view_count[t]) {
736 size_t transfer_size = desc_size * ctx->sampler_count[t];
737
738 struct panfrost_transfer transfer =
739 panfrost_allocate_transient(ctx, transfer_size);
740
741 struct mali_sampler_descriptor *desc =
742 (struct mali_sampler_descriptor *) transfer.cpu;
743
744 for (int i = 0; i < ctx->sampler_count[t]; ++i)
745 desc[i] = ctx->samplers[t][i]->hw;
746
747 upload = transfer.gpu;
748 }
749
750 ctx->payloads[t].postfix.sampler_descriptor = upload;
751 }
752 }
753
754 static unsigned
755 panfrost_layout_for_texture(struct panfrost_resource *rsrc, bool manual_stride)
756 {
757 /* TODO: other linear depth textures */
758 bool is_depth = rsrc->base.format == PIPE_FORMAT_Z32_UNORM;
759
760 unsigned usage2_layout = 0x10;
761
762 switch (rsrc->layout) {
763 case PAN_AFBC:
764 usage2_layout |= 0x8 | 0x4;
765 break;
766 case PAN_TILED:
767 usage2_layout |= 0x1;
768 break;
769 case PAN_LINEAR:
770 usage2_layout |= is_depth ? 0x1 : 0x2;
771 break;
772 default:
773 assert(0);
774 break;
775 }
776
777 if (manual_stride)
778 usage2_layout |= MALI_TEX_MANUAL_STRIDE;
779
780 return usage2_layout;
781 }
782
783 static mali_ptr
784 panfrost_upload_tex(
785 struct panfrost_context *ctx,
786 struct panfrost_sampler_view *view)
787 {
788 if (!view)
789 return (mali_ptr) 0;
790
791 struct pipe_sampler_view *pview = &view->base;
792 struct panfrost_resource *rsrc = pan_resource(pview->texture);
793
794 /* Do we interleave an explicit stride with every element? */
795
796 bool has_manual_stride = view->manual_stride;
797
798 /* For easy access */
799
800 assert(pview->target != PIPE_BUFFER);
801 unsigned first_level = pview->u.tex.first_level;
802 unsigned last_level = pview->u.tex.last_level;
803 unsigned first_layer = pview->u.tex.first_layer;
804 unsigned last_layer = pview->u.tex.last_layer;
805
806 /* Lower-bit is set when sampling from colour AFBC */
807 bool is_afbc = rsrc->layout == PAN_AFBC;
808 bool is_zs = rsrc->base.bind & PIPE_BIND_DEPTH_STENCIL;
809 unsigned afbc_bit = (is_afbc && !is_zs) ? 1 : 0;
810
811 /* Add the BO to the job so it's retained until the job is done. */
812 struct panfrost_job *job = panfrost_get_job_for_fbo(ctx);
813 panfrost_job_add_bo(job, rsrc->bo);
814
815 /* Add the usage flags in, since they can change across the CSO
816 * lifetime due to layout switches */
817
818 view->hw.format.usage2 = panfrost_layout_for_texture(rsrc, has_manual_stride);
819
820 /* Inject the addresses in, interleaving mip levels, cube faces, and
821 * strides in that order */
822
823 unsigned idx = 0;
824
825 for (unsigned l = first_level; l <= last_level; ++l) {
826 for (unsigned f = first_layer; f <= last_layer; ++f) {
827
828 view->hw.payload[idx++] =
829 panfrost_get_texture_address(rsrc, l, f) + afbc_bit;
830
831 if (has_manual_stride) {
832 view->hw.payload[idx++] =
833 rsrc->slices[l].stride;
834 }
835 }
836 }
837
838 return panfrost_upload_transient(ctx, &view->hw,
839 sizeof(struct mali_texture_descriptor));
840 }
841
842 static void
843 panfrost_upload_texture_descriptors(struct panfrost_context *ctx)
844 {
845 for (int t = 0; t <= PIPE_SHADER_FRAGMENT; ++t) {
846 mali_ptr trampoline = 0;
847
848 if (ctx->sampler_view_count[t]) {
849 uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS];
850
851 for (int i = 0; i < ctx->sampler_view_count[t]; ++i)
852 trampolines[i] =
853 panfrost_upload_tex(ctx, ctx->sampler_views[t][i]);
854
855 trampoline = panfrost_upload_transient(ctx, trampolines, sizeof(uint64_t) * ctx->sampler_view_count[t]);
856 }
857
858 ctx->payloads[t].postfix.texture_trampoline = trampoline;
859 }
860 }
861
862 struct sysval_uniform {
863 union {
864 float f[4];
865 int32_t i[4];
866 uint32_t u[4];
867 };
868 };
869
870 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context *ctx,
871 struct sysval_uniform *uniform)
872 {
873 const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
874
875 uniform->f[0] = vp->scale[0];
876 uniform->f[1] = vp->scale[1];
877 uniform->f[2] = vp->scale[2];
878 }
879
880 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context *ctx,
881 struct sysval_uniform *uniform)
882 {
883 const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
884
885 uniform->f[0] = vp->translate[0];
886 uniform->f[1] = vp->translate[1];
887 uniform->f[2] = vp->translate[2];
888 }
889
890 static void panfrost_upload_txs_sysval(struct panfrost_context *ctx,
891 enum pipe_shader_type st,
892 unsigned int sysvalid,
893 struct sysval_uniform *uniform)
894 {
895 unsigned texidx = PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid);
896 unsigned dim = PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid);
897 bool is_array = PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid);
898 struct pipe_sampler_view *tex = &ctx->sampler_views[st][texidx]->base;
899
900 assert(dim);
901 uniform->i[0] = u_minify(tex->texture->width0, tex->u.tex.first_level);
902
903 if (dim > 1)
904 uniform->i[1] = u_minify(tex->texture->height0,
905 tex->u.tex.first_level);
906
907 if (dim > 2)
908 uniform->i[2] = u_minify(tex->texture->depth0,
909 tex->u.tex.first_level);
910
911 if (is_array)
912 uniform->i[dim] = tex->texture->array_size;
913 }
914
915 static void panfrost_upload_sysvals(struct panfrost_context *ctx, void *buf,
916 struct panfrost_shader_state *ss,
917 enum pipe_shader_type st)
918 {
919 struct sysval_uniform *uniforms = (void *)buf;
920
921 for (unsigned i = 0; i < ss->sysval_count; ++i) {
922 int sysval = ss->sysval[i];
923
924 switch (PAN_SYSVAL_TYPE(sysval)) {
925 case PAN_SYSVAL_VIEWPORT_SCALE:
926 panfrost_upload_viewport_scale_sysval(ctx, &uniforms[i]);
927 break;
928 case PAN_SYSVAL_VIEWPORT_OFFSET:
929 panfrost_upload_viewport_offset_sysval(ctx, &uniforms[i]);
930 break;
931 case PAN_SYSVAL_TEXTURE_SIZE:
932 panfrost_upload_txs_sysval(ctx, st, PAN_SYSVAL_ID(sysval),
933 &uniforms[i]);
934 break;
935 default:
936 assert(0);
937 }
938 }
939 }
940
941 static const void *
942 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer *buf, unsigned index)
943 {
944 struct pipe_constant_buffer *cb = &buf->cb[index];
945 struct panfrost_resource *rsrc = pan_resource(cb->buffer);
946
947 if (rsrc)
948 return rsrc->bo->cpu;
949 else if (cb->user_buffer)
950 return cb->user_buffer;
951 else
952 unreachable("No constant buffer");
953 }
954
955 static mali_ptr
956 panfrost_map_constant_buffer_gpu(
957 struct panfrost_context *ctx,
958 struct panfrost_constant_buffer *buf,
959 unsigned index)
960 {
961 struct pipe_constant_buffer *cb = &buf->cb[index];
962 struct panfrost_resource *rsrc = pan_resource(cb->buffer);
963
964 if (rsrc)
965 return rsrc->bo->gpu;
966 else if (cb->user_buffer)
967 return panfrost_upload_transient(ctx, cb->user_buffer, cb->buffer_size);
968 else
969 unreachable("No constant buffer");
970 }
971
972 /* Compute number of UBOs active (more specifically, compute the highest UBO
973 * number addressable -- if there are gaps, include them in the count anyway).
974 * We always include UBO #0 in the count, since we *need* uniforms enabled for
975 * sysvals. */
976
977 static unsigned
978 panfrost_ubo_count(struct panfrost_context *ctx, enum pipe_shader_type stage)
979 {
980 unsigned mask = ctx->constant_buffer[stage].enabled_mask | 1;
981 return 32 - __builtin_clz(mask);
982 }
983
984 /* Fixes up a shader state with current state, returning a GPU address to the
985 * patched shader */
986
987 static mali_ptr
988 panfrost_patch_shader_state(
989 struct panfrost_context *ctx,
990 struct panfrost_shader_state *ss,
991 enum pipe_shader_type stage,
992 bool should_upload)
993 {
994 ss->tripipe->texture_count = ctx->sampler_view_count[stage];
995 ss->tripipe->sampler_count = ctx->sampler_count[stage];
996
997 ss->tripipe->midgard1.flags = 0x220;
998
999 unsigned ubo_count = panfrost_ubo_count(ctx, stage);
1000 ss->tripipe->midgard1.uniform_buffer_count = ubo_count;
1001
1002 /* We can't reuse over frames; that's not safe. The descriptor must be
1003 * transient uploaded */
1004
1005 if (should_upload) {
1006 return panfrost_upload_transient(ctx,
1007 ss->tripipe,
1008 sizeof(struct mali_shader_meta));
1009 }
1010
1011 /* If we don't need an upload, don't bother */
1012 return 0;
1013
1014 }
1015
1016 static void
1017 panfrost_patch_shader_state_compute(
1018 struct panfrost_context *ctx,
1019 enum pipe_shader_type stage,
1020 bool should_upload)
1021 {
1022 struct panfrost_shader_variants *all = ctx->shader[stage];
1023
1024 if (!all) {
1025 ctx->payloads[stage].postfix._shader_upper = 0;
1026 return;
1027 }
1028
1029 struct panfrost_shader_state *s = &all->variants[all->active_variant];
1030
1031 ctx->payloads[stage].postfix._shader_upper =
1032 panfrost_patch_shader_state(ctx, s, stage, should_upload) >> 4;
1033 }
1034
1035 /* Go through dirty flags and actualise them in the cmdstream. */
1036
1037 void
1038 panfrost_emit_for_draw(struct panfrost_context *ctx, bool with_vertex_data)
1039 {
1040 struct panfrost_job *job = panfrost_get_job_for_fbo(ctx);
1041 struct panfrost_screen *screen = pan_screen(ctx->base.screen);
1042
1043 panfrost_attach_vt_framebuffer(ctx, true);
1044
1045 if (with_vertex_data) {
1046 panfrost_emit_vertex_data(job);
1047
1048 /* Varyings emitted for -all- geometry */
1049 unsigned total_count = ctx->padded_count * ctx->instance_count;
1050 panfrost_emit_varying_descriptor(ctx, total_count);
1051 }
1052
1053 bool msaa = ctx->rasterizer->base.multisample;
1054
1055 if (ctx->dirty & PAN_DIRTY_RASTERIZER) {
1056 ctx->payloads[PIPE_SHADER_FRAGMENT].gl_enables = ctx->rasterizer->tiler_gl_enables;
1057
1058 /* TODO: Sample size */
1059 SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_HAS_MSAA, msaa);
1060 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_NO_MSAA, !msaa);
1061 }
1062
1063 panfrost_job_set_requirements(ctx, job);
1064
1065 if (ctx->occlusion_query) {
1066 ctx->payloads[PIPE_SHADER_FRAGMENT].gl_enables |= MALI_OCCLUSION_QUERY | MALI_OCCLUSION_PRECISE;
1067 ctx->payloads[PIPE_SHADER_FRAGMENT].postfix.occlusion_counter = ctx->occlusion_query->transfer.gpu;
1068 }
1069
1070 panfrost_patch_shader_state_compute(ctx, PIPE_SHADER_VERTEX, true);
1071 panfrost_patch_shader_state_compute(ctx, PIPE_SHADER_COMPUTE, true);
1072
1073 if (ctx->dirty & (PAN_DIRTY_RASTERIZER | PAN_DIRTY_VS)) {
1074 /* Check if we need to link the gl_PointSize varying */
1075 if (!panfrost_writes_point_size(ctx)) {
1076 /* If the size is constant, write it out. Otherwise,
1077 * don't touch primitive_size (since we would clobber
1078 * the pointer there) */
1079
1080 ctx->payloads[PIPE_SHADER_FRAGMENT].primitive_size.constant = ctx->rasterizer->base.line_width;
1081 }
1082 }
1083
1084 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1085 if (ctx->shader[PIPE_SHADER_FRAGMENT])
1086 ctx->dirty |= PAN_DIRTY_FS;
1087
1088 if (ctx->dirty & PAN_DIRTY_FS) {
1089 assert(ctx->shader[PIPE_SHADER_FRAGMENT]);
1090 struct panfrost_shader_state *variant = &ctx->shader[PIPE_SHADER_FRAGMENT]->variants[ctx->shader[PIPE_SHADER_FRAGMENT]->active_variant];
1091
1092 panfrost_patch_shader_state(ctx, variant, PIPE_SHADER_FRAGMENT, false);
1093
1094 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1095
1096 COPY(shader);
1097 COPY(attribute_count);
1098 COPY(varying_count);
1099 COPY(texture_count);
1100 COPY(sampler_count);
1101 COPY(sampler_count);
1102 COPY(midgard1.uniform_count);
1103 COPY(midgard1.uniform_buffer_count);
1104 COPY(midgard1.work_count);
1105 COPY(midgard1.flags);
1106 COPY(midgard1.unknown2);
1107
1108 #undef COPY
1109
1110 /* Get blending setup */
1111 struct panfrost_blend_final blend =
1112 panfrost_get_blend_for_context(ctx, 0);
1113
1114 /* If there is a blend shader, work registers are shared */
1115
1116 if (blend.is_shader)
1117 ctx->fragment_shader_core.midgard1.work_count = /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1118
1119 /* Set late due to depending on render state */
1120 unsigned flags = ctx->fragment_shader_core.midgard1.flags;
1121
1122 /* Depending on whether it's legal to in the given shader, we
1123 * try to enable early-z testing (or forward-pixel kill?) */
1124
1125 if (!variant->can_discard)
1126 flags |= MALI_EARLY_Z;
1127
1128 /* Any time texturing is used, derivatives are implicitly
1129 * calculated, so we need to enable helper invocations */
1130
1131 if (variant->helper_invocations)
1132 flags |= MALI_HELPER_INVOCATIONS;
1133
1134 ctx->fragment_shader_core.midgard1.flags = flags;
1135
1136 /* Assign the stencil refs late */
1137
1138 unsigned front_ref = ctx->stencil_ref.ref_value[0];
1139 unsigned back_ref = ctx->stencil_ref.ref_value[1];
1140 bool back_enab = ctx->depth_stencil->stencil[1].enabled;
1141
1142 ctx->fragment_shader_core.stencil_front.ref = front_ref;
1143 ctx->fragment_shader_core.stencil_back.ref = back_enab ? back_ref : front_ref;
1144
1145 /* CAN_DISCARD should be set if the fragment shader possibly
1146 * contains a 'discard' instruction. It is likely this is
1147 * related to optimizations related to forward-pixel kill, as
1148 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1149 * thing?" by Peter Harris
1150 */
1151
1152 if (variant->can_discard) {
1153 ctx->fragment_shader_core.unknown2_3 |= MALI_CAN_DISCARD;
1154 ctx->fragment_shader_core.midgard1.flags |= 0x400;
1155 }
1156
1157 /* Check if we're using the default blend descriptor (fast path) */
1158
1159 bool no_blending =
1160 !blend.is_shader &&
1161 (blend.equation.equation->rgb_mode == 0x122) &&
1162 (blend.equation.equation->alpha_mode == 0x122) &&
1163 (blend.equation.equation->color_mask == 0xf);
1164
1165 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1166 * *also* copied to the blend_meta appended (by convention),
1167 * but this is the field actually read by the hardware. (Or
1168 * maybe both are read...?) */
1169
1170 if (blend.is_shader) {
1171 ctx->fragment_shader_core.blend.shader =
1172 blend.shader.gpu;
1173 } else {
1174 ctx->fragment_shader_core.blend.shader = 0;
1175 }
1176
1177 if (screen->require_sfbd) {
1178 /* When only a single render target platform is used, the blend
1179 * information is inside the shader meta itself. We
1180 * additionally need to signal CAN_DISCARD for nontrivial blend
1181 * modes (so we're able to read back the destination buffer) */
1182
1183 if (!blend.is_shader) {
1184 ctx->fragment_shader_core.blend.equation =
1185 *blend.equation.equation;
1186 ctx->fragment_shader_core.blend.constant =
1187 blend.equation.constant;
1188 }
1189
1190 if (!no_blending) {
1191 ctx->fragment_shader_core.unknown2_3 |= MALI_CAN_DISCARD;
1192 }
1193 }
1194
1195 size_t size = sizeof(struct mali_shader_meta) + sizeof(struct midgard_blend_rt);
1196 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, size);
1197 memcpy(transfer.cpu, &ctx->fragment_shader_core, sizeof(struct mali_shader_meta));
1198
1199 ctx->payloads[PIPE_SHADER_FRAGMENT].postfix._shader_upper = (transfer.gpu) >> 4;
1200
1201 if (!screen->require_sfbd) {
1202 /* Additional blend descriptor tacked on for jobs using MFBD */
1203
1204 unsigned blend_count = 0x200;
1205
1206 if (blend.is_shader) {
1207 /* For a blend shader, the bottom nibble corresponds to
1208 * the number of work registers used, which signals the
1209 * -existence- of a blend shader */
1210
1211 assert(blend.shader.work_count >= 2);
1212 blend_count |= MIN2(blend.shader.work_count, 3);
1213 } else {
1214 /* Otherwise, the bottom bit simply specifies if
1215 * blending (anything other than REPLACE) is enabled */
1216
1217
1218 if (!no_blending)
1219 blend_count |= 0x1;
1220 }
1221
1222 struct midgard_blend_rt rts[4];
1223
1224 for (unsigned i = 0; i < ctx->pipe_framebuffer.nr_cbufs; ++i) {
1225 bool is_srgb =
1226 (ctx->pipe_framebuffer.nr_cbufs > i) &&
1227 (ctx->pipe_framebuffer.cbufs[i]) &&
1228 util_format_is_srgb(ctx->pipe_framebuffer.cbufs[i]->format);
1229
1230 rts[i].flags = blend_count;
1231
1232 if (is_srgb)
1233 rts[i].flags |= MALI_BLEND_SRGB;
1234
1235 if (!ctx->blend->base.dither)
1236 rts[i].flags |= MALI_BLEND_NO_DITHER;
1237
1238 /* TODO: sRGB in blend shaders is currently
1239 * unimplemented. Contact me (Alyssa) if you're
1240 * interested in working on this. We have
1241 * native Midgard ops for helping here, but
1242 * they're not well-understood yet. */
1243
1244 assert(!(is_srgb && blend.is_shader));
1245
1246 if (blend.is_shader) {
1247 rts[i].blend.shader = blend.shader.gpu;
1248 } else {
1249 rts[i].blend.equation = *blend.equation.equation;
1250 rts[i].blend.constant = blend.equation.constant;
1251 }
1252 }
1253
1254 memcpy(transfer.cpu + sizeof(struct mali_shader_meta), rts, sizeof(rts[0]) * 1);
1255 }
1256 }
1257
1258 /* We stage to transient, so always dirty.. */
1259 if (ctx->vertex)
1260 panfrost_stage_attributes(ctx);
1261
1262 if (ctx->dirty & PAN_DIRTY_SAMPLERS)
1263 panfrost_upload_sampler_descriptors(ctx);
1264
1265 if (ctx->dirty & PAN_DIRTY_TEXTURES)
1266 panfrost_upload_texture_descriptors(ctx);
1267
1268 const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
1269
1270 for (int i = 0; i <= PIPE_SHADER_FRAGMENT; ++i) {
1271 struct panfrost_constant_buffer *buf = &ctx->constant_buffer[i];
1272
1273 struct panfrost_shader_state *vs = &ctx->shader[PIPE_SHADER_VERTEX]->variants[ctx->shader[PIPE_SHADER_VERTEX]->active_variant];
1274 struct panfrost_shader_state *fs = &ctx->shader[PIPE_SHADER_FRAGMENT]->variants[ctx->shader[PIPE_SHADER_FRAGMENT]->active_variant];
1275 struct panfrost_shader_state *ss = (i == PIPE_SHADER_FRAGMENT) ? fs : vs;
1276
1277 /* Uniforms are implicitly UBO #0 */
1278 bool has_uniforms = buf->enabled_mask & (1 << 0);
1279
1280 /* Allocate room for the sysval and the uniforms */
1281 size_t sys_size = sizeof(float) * 4 * ss->sysval_count;
1282 size_t uniform_size = has_uniforms ? (buf->cb[0].buffer_size) : 0;
1283 size_t size = sys_size + uniform_size;
1284 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, size);
1285
1286 /* Upload sysvals requested by the shader */
1287 panfrost_upload_sysvals(ctx, transfer.cpu, ss, i);
1288
1289 /* Upload uniforms */
1290 if (has_uniforms) {
1291 const void *cpu = panfrost_map_constant_buffer_cpu(buf, 0);
1292 memcpy(transfer.cpu + sys_size, cpu, uniform_size);
1293 }
1294
1295 int uniform_count =
1296 ctx->shader[i]->variants[ctx->shader[i]->active_variant].uniform_count;
1297
1298 struct mali_vertex_tiler_postfix *postfix =
1299 &ctx->payloads[i].postfix;
1300
1301 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1302 * uploaded */
1303
1304 unsigned ubo_count = panfrost_ubo_count(ctx, i);
1305 assert(ubo_count >= 1);
1306
1307 size_t sz = sizeof(struct mali_uniform_buffer_meta) * ubo_count;
1308 struct mali_uniform_buffer_meta ubos[PAN_MAX_CONST_BUFFERS];
1309
1310 /* Upload uniforms as a UBO */
1311 ubos[0].size = MALI_POSITIVE((2 + uniform_count));
1312 ubos[0].ptr = transfer.gpu >> 2;
1313
1314 /* The rest are honest-to-goodness UBOs */
1315
1316 for (unsigned ubo = 1; ubo < ubo_count; ++ubo) {
1317 size_t sz = buf->cb[ubo].buffer_size;
1318
1319 bool enabled = buf->enabled_mask & (1 << ubo);
1320 bool empty = sz == 0;
1321
1322 if (!enabled || empty) {
1323 /* Stub out disabled UBOs to catch accesses */
1324
1325 ubos[ubo].size = 0;
1326 ubos[ubo].ptr = 0xDEAD0000;
1327 continue;
1328 }
1329
1330 mali_ptr gpu = panfrost_map_constant_buffer_gpu(ctx, buf, ubo);
1331
1332 unsigned bytes_per_field = 16;
1333 unsigned aligned = ALIGN_POT(sz, bytes_per_field);
1334 unsigned fields = aligned / bytes_per_field;
1335
1336 ubos[ubo].size = MALI_POSITIVE(fields);
1337 ubos[ubo].ptr = gpu >> 2;
1338 }
1339
1340 mali_ptr ubufs = panfrost_upload_transient(ctx, ubos, sz);
1341 postfix->uniforms = transfer.gpu;
1342 postfix->uniform_buffers = ubufs;
1343
1344 buf->dirty_mask = 0;
1345 }
1346
1347 /* TODO: Upload the viewport somewhere more appropriate */
1348
1349 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1350 * (somewhat) asymmetric ints. */
1351 const struct pipe_scissor_state *ss = &ctx->scissor;
1352
1353 struct mali_viewport view = {
1354 /* By default, do no viewport clipping, i.e. clip to (-inf,
1355 * inf) in each direction. Clipping to the viewport in theory
1356 * should work, but in practice causes issues when we're not
1357 * explicitly trying to scissor */
1358
1359 .clip_minx = -INFINITY,
1360 .clip_miny = -INFINITY,
1361 .clip_maxx = INFINITY,
1362 .clip_maxy = INFINITY,
1363
1364 .clip_minz = 0.0,
1365 .clip_maxz = 1.0,
1366 };
1367
1368 /* Always scissor to the viewport by default. */
1369 float vp_minx = (int) (vp->translate[0] - fabsf(vp->scale[0]));
1370 float vp_maxx = (int) (vp->translate[0] + fabsf(vp->scale[0]));
1371
1372 float vp_miny = (int) (vp->translate[1] - fabsf(vp->scale[1]));
1373 float vp_maxy = (int) (vp->translate[1] + fabsf(vp->scale[1]));
1374
1375 /* Apply the scissor test */
1376
1377 unsigned minx, miny, maxx, maxy;
1378
1379 if (ss && ctx->rasterizer && ctx->rasterizer->base.scissor) {
1380 minx = MAX2(ss->minx, vp_minx);
1381 miny = MAX2(ss->miny, vp_miny);
1382 maxx = MIN2(ss->maxx, vp_maxx);
1383 maxy = MIN2(ss->maxy, vp_maxy);
1384 } else {
1385 minx = vp_minx;
1386 miny = vp_miny;
1387 maxx = vp_maxx;
1388 maxy = vp_maxy;
1389 }
1390
1391 /* Hardware needs the min/max to be strictly ordered, so flip if we
1392 * need to. The viewport transformation in the vertex shader will
1393 * handle the negatives if we don't */
1394
1395 if (miny > maxy) {
1396 int temp = miny;
1397 miny = maxy;
1398 maxy = temp;
1399 }
1400
1401 if (minx > maxx) {
1402 int temp = minx;
1403 minx = maxx;
1404 maxx = temp;
1405 }
1406
1407 /* Clamp everything positive, just in case */
1408
1409 maxx = MAX2(0, maxx);
1410 maxy = MAX2(0, maxy);
1411 minx = MAX2(0, minx);
1412 miny = MAX2(0, miny);
1413
1414 /* Clamp to the framebuffer size as a last check */
1415
1416 minx = MIN2(ctx->pipe_framebuffer.width, minx);
1417 maxx = MIN2(ctx->pipe_framebuffer.width, maxx);
1418
1419 miny = MIN2(ctx->pipe_framebuffer.height, miny);
1420 maxy = MIN2(ctx->pipe_framebuffer.height, maxy);
1421
1422 /* Update the job, unless we're doing wallpapering (whose lack of
1423 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1424 * just... be faster :) */
1425
1426 if (!ctx->wallpaper_batch)
1427 panfrost_job_union_scissor(job, minx, miny, maxx, maxy);
1428
1429 /* Upload */
1430
1431 view.viewport0[0] = minx;
1432 view.viewport1[0] = MALI_POSITIVE(maxx);
1433
1434 view.viewport0[1] = miny;
1435 view.viewport1[1] = MALI_POSITIVE(maxy);
1436
1437 ctx->payloads[PIPE_SHADER_FRAGMENT].postfix.viewport =
1438 panfrost_upload_transient(ctx,
1439 &view,
1440 sizeof(struct mali_viewport));
1441
1442 ctx->dirty = 0;
1443 }
1444
1445 /* Corresponds to exactly one draw, but does not submit anything */
1446
1447 static void
1448 panfrost_queue_draw(struct panfrost_context *ctx)
1449 {
1450 /* Handle dirty flags now */
1451 panfrost_emit_for_draw(ctx, true);
1452
1453 /* If rasterizer discard is enable, only submit the vertex */
1454
1455 bool rasterizer_discard = ctx->rasterizer
1456 && ctx->rasterizer->base.rasterizer_discard;
1457
1458 struct panfrost_transfer vertex = panfrost_vertex_tiler_job(ctx, false);
1459 struct panfrost_transfer tiler;
1460
1461 if (!rasterizer_discard)
1462 tiler = panfrost_vertex_tiler_job(ctx, true);
1463
1464 struct panfrost_job *batch = panfrost_get_job_for_fbo(ctx);
1465
1466 if (rasterizer_discard)
1467 panfrost_scoreboard_queue_vertex_job(batch, vertex, FALSE);
1468 else if (ctx->wallpaper_batch)
1469 panfrost_scoreboard_queue_fused_job_prepend(batch, vertex, tiler);
1470 else
1471 panfrost_scoreboard_queue_fused_job(batch, vertex, tiler);
1472 }
1473
1474 /* The entire frame is in memory -- send it off to the kernel! */
1475
1476 static void
1477 panfrost_submit_frame(struct panfrost_context *ctx, bool flush_immediate,
1478 struct pipe_fence_handle **fence,
1479 struct panfrost_job *job)
1480 {
1481 struct pipe_context *gallium = (struct pipe_context *) ctx;
1482 struct panfrost_screen *screen = pan_screen(gallium->screen);
1483
1484 #ifndef DRY_RUN
1485
1486 panfrost_job_submit(ctx, job);
1487
1488 /* If visual, we can stall a frame */
1489
1490 if (!flush_immediate)
1491 panfrost_drm_force_flush_fragment(ctx, fence);
1492
1493 screen->last_fragment_flushed = false;
1494 screen->last_job = job;
1495
1496 /* If readback, flush now (hurts the pipelined performance) */
1497 if (flush_immediate)
1498 panfrost_drm_force_flush_fragment(ctx, fence);
1499 #endif
1500 }
1501
1502 static void
1503 panfrost_draw_wallpaper(struct pipe_context *pipe)
1504 {
1505 struct panfrost_context *ctx = pan_context(pipe);
1506
1507 /* Nothing to reload? TODO: MRT wallpapers */
1508 if (ctx->pipe_framebuffer.cbufs[0] == NULL)
1509 return;
1510
1511 /* Check if the buffer has any content on it worth preserving */
1512
1513 struct pipe_surface *surf = ctx->pipe_framebuffer.cbufs[0];
1514 struct panfrost_resource *rsrc = pan_resource(surf->texture);
1515 unsigned level = surf->u.tex.level;
1516
1517 if (!rsrc->slices[level].initialized)
1518 return;
1519
1520 /* Save the batch */
1521 struct panfrost_job *batch = panfrost_get_job_for_fbo(ctx);
1522
1523 ctx->wallpaper_batch = batch;
1524 panfrost_blit_wallpaper(ctx);
1525 ctx->wallpaper_batch = NULL;
1526 }
1527
1528 void
1529 panfrost_flush(
1530 struct pipe_context *pipe,
1531 struct pipe_fence_handle **fence,
1532 unsigned flags)
1533 {
1534 struct panfrost_context *ctx = pan_context(pipe);
1535 struct panfrost_job *job = panfrost_get_job_for_fbo(ctx);
1536
1537 /* Nothing to do! */
1538 if (!job->last_job.gpu && !job->clear) return;
1539
1540 if (!job->clear && job->last_tiler.gpu)
1541 panfrost_draw_wallpaper(&ctx->base);
1542
1543 /* Whether to stall the pipeline for immediately correct results. Since
1544 * pipelined rendering is quite broken right now (to be fixed by the
1545 * panfrost_job refactor, just take the perf hit for correctness) */
1546 bool flush_immediate = /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1547
1548 /* Submit the frame itself */
1549 panfrost_submit_frame(ctx, flush_immediate, fence, job);
1550
1551 /* Prepare for the next frame */
1552 panfrost_invalidate_frame(ctx);
1553 }
1554
1555 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1556
1557 static int
1558 g2m_draw_mode(enum pipe_prim_type mode)
1559 {
1560 switch (mode) {
1561 DEFINE_CASE(POINTS);
1562 DEFINE_CASE(LINES);
1563 DEFINE_CASE(LINE_LOOP);
1564 DEFINE_CASE(LINE_STRIP);
1565 DEFINE_CASE(TRIANGLES);
1566 DEFINE_CASE(TRIANGLE_STRIP);
1567 DEFINE_CASE(TRIANGLE_FAN);
1568 DEFINE_CASE(QUADS);
1569 DEFINE_CASE(QUAD_STRIP);
1570 DEFINE_CASE(POLYGON);
1571
1572 default:
1573 unreachable("Invalid draw mode");
1574 }
1575 }
1576
1577 #undef DEFINE_CASE
1578
1579 static unsigned
1580 panfrost_translate_index_size(unsigned size)
1581 {
1582 switch (size) {
1583 case 1:
1584 return MALI_DRAW_INDEXED_UINT8;
1585
1586 case 2:
1587 return MALI_DRAW_INDEXED_UINT16;
1588
1589 case 4:
1590 return MALI_DRAW_INDEXED_UINT32;
1591
1592 default:
1593 unreachable("Invalid index size");
1594 }
1595 }
1596
1597 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1598 * good for the duration of the draw (transient), could last longer */
1599
1600 static mali_ptr
1601 panfrost_get_index_buffer_mapped(struct panfrost_context *ctx, const struct pipe_draw_info *info)
1602 {
1603 struct panfrost_resource *rsrc = (struct panfrost_resource *) (info->index.resource);
1604
1605 off_t offset = info->start * info->index_size;
1606 struct panfrost_job *batch = panfrost_get_job_for_fbo(ctx);
1607
1608 if (!info->has_user_indices) {
1609 /* Only resources can be directly mapped */
1610 panfrost_job_add_bo(batch, rsrc->bo);
1611 return rsrc->bo->gpu + offset;
1612 } else {
1613 /* Otherwise, we need to upload to transient memory */
1614 const uint8_t *ibuf8 = (const uint8_t *) info->index.user;
1615 return panfrost_upload_transient(ctx, ibuf8 + offset, info->count * info->index_size);
1616 }
1617 }
1618
1619 static bool
1620 panfrost_scissor_culls_everything(struct panfrost_context *ctx)
1621 {
1622 const struct pipe_scissor_state *ss = &ctx->scissor;
1623
1624 /* Check if we're scissoring at all */
1625
1626 if (!(ctx->rasterizer && ctx->rasterizer->base.scissor))
1627 return false;
1628
1629 return (ss->minx == ss->maxx) || (ss->miny == ss->maxy);
1630 }
1631
1632 static void
1633 panfrost_draw_vbo(
1634 struct pipe_context *pipe,
1635 const struct pipe_draw_info *info)
1636 {
1637 struct panfrost_context *ctx = pan_context(pipe);
1638
1639 /* First of all, check the scissor to see if anything is drawn at all.
1640 * If it's not, we drop the draw (mostly a conformance issue;
1641 * well-behaved apps shouldn't hit this) */
1642
1643 if (panfrost_scissor_culls_everything(ctx))
1644 return;
1645
1646 ctx->payloads[PIPE_SHADER_VERTEX].draw_start = info->start;
1647 ctx->payloads[PIPE_SHADER_FRAGMENT].draw_start = info->start;
1648
1649 int mode = info->mode;
1650
1651 /* Fallback unsupported restart index */
1652 unsigned primitive_index = (1 << (info->index_size * 8)) - 1;
1653
1654 if (info->primitive_restart && info->index_size
1655 && info->restart_index != primitive_index) {
1656 util_draw_vbo_without_prim_restart(pipe, info);
1657 return;
1658 }
1659
1660 /* Fallback for unsupported modes */
1661
1662 if (!(ctx->draw_modes & (1 << mode))) {
1663 if (mode == PIPE_PRIM_QUADS && info->count == 4 && ctx->rasterizer && !ctx->rasterizer->base.flatshade) {
1664 mode = PIPE_PRIM_TRIANGLE_FAN;
1665 } else {
1666 if (info->count < 4) {
1667 /* Degenerate case? */
1668 return;
1669 }
1670
1671 util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base);
1672 util_primconvert_draw_vbo(ctx->primconvert, info);
1673 return;
1674 }
1675 }
1676
1677 /* Now that we have a guaranteed terminating path, find the job.
1678 * Assignment commented out to prevent unused warning */
1679
1680 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx);
1681
1682 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.draw_mode = g2m_draw_mode(mode);
1683
1684 ctx->vertex_count = info->count;
1685 ctx->instance_count = info->instance_count;
1686
1687 /* For non-indexed draws, they're the same */
1688 unsigned vertex_count = ctx->vertex_count;
1689
1690 unsigned draw_flags = 0;
1691
1692 /* The draw flags interpret how primitive size is interpreted */
1693
1694 if (panfrost_writes_point_size(ctx))
1695 draw_flags |= MALI_DRAW_VARYING_SIZE;
1696
1697 if (info->primitive_restart)
1698 draw_flags |= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX;
1699
1700 /* For higher amounts of vertices (greater than what fits in a 16-bit
1701 * short), the other value is needed, otherwise there will be bizarre
1702 * rendering artefacts. It's not clear what these values mean yet. This
1703 * change is also needed for instancing and sometimes points (perhaps
1704 * related to dynamically setting gl_PointSize) */
1705
1706 bool is_points = mode == PIPE_PRIM_POINTS;
1707 bool many_verts = ctx->vertex_count > 0xFFFF;
1708 bool instanced = ctx->instance_count > 1;
1709
1710 draw_flags |= (is_points || many_verts || instanced) ? 0x3000 : 0x18000;
1711
1712 /* This doesn't make much sense */
1713 if (mode == PIPE_PRIM_LINE_STRIP) {
1714 draw_flags |= 0x800;
1715 }
1716
1717 if (info->index_size) {
1718 /* Calculate the min/max index used so we can figure out how
1719 * many times to invoke the vertex shader */
1720
1721 /* Fetch / calculate index bounds */
1722 unsigned min_index = 0, max_index = 0;
1723
1724 if (info->max_index == ~0u) {
1725 u_vbuf_get_minmax_index(pipe, info, &min_index, &max_index);
1726 } else {
1727 min_index = info->min_index;
1728 max_index = info->max_index;
1729 }
1730
1731 /* Use the corresponding values */
1732 vertex_count = max_index - min_index + 1;
1733 ctx->payloads[PIPE_SHADER_VERTEX].draw_start = min_index;
1734 ctx->payloads[PIPE_SHADER_FRAGMENT].draw_start = min_index;
1735
1736 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.negative_start = -min_index;
1737 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.index_count = MALI_POSITIVE(info->count);
1738
1739 //assert(!info->restart_index); /* TODO: Research */
1740 assert(!info->index_bias);
1741
1742 draw_flags |= panfrost_translate_index_size(info->index_size);
1743 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.indices = panfrost_get_index_buffer_mapped(ctx, info);
1744 } else {
1745 /* Index count == vertex count, if no indexing is applied, as
1746 * if it is internally indexed in the expected order */
1747
1748 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.negative_start = 0;
1749 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.index_count = MALI_POSITIVE(ctx->vertex_count);
1750
1751 /* Reverse index state */
1752 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.indices = (u64) NULL;
1753 }
1754
1755 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1756 * vertex_count, 1) */
1757
1758 panfrost_pack_work_groups_fused(
1759 &ctx->payloads[PIPE_SHADER_VERTEX].prefix,
1760 &ctx->payloads[PIPE_SHADER_FRAGMENT].prefix,
1761 1, vertex_count, info->instance_count,
1762 1, 1, 1);
1763
1764 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.unknown_draw = draw_flags;
1765
1766 /* Encode the padded vertex count */
1767
1768 if (info->instance_count > 1) {
1769 /* Triangles have non-even vertex counts so they change how
1770 * padding works internally */
1771
1772 bool is_triangle =
1773 mode == PIPE_PRIM_TRIANGLES ||
1774 mode == PIPE_PRIM_TRIANGLE_STRIP ||
1775 mode == PIPE_PRIM_TRIANGLE_FAN;
1776
1777 struct pan_shift_odd so =
1778 panfrost_padded_vertex_count(vertex_count, !is_triangle);
1779
1780 ctx->payloads[PIPE_SHADER_VERTEX].instance_shift = so.shift;
1781 ctx->payloads[PIPE_SHADER_FRAGMENT].instance_shift = so.shift;
1782
1783 ctx->payloads[PIPE_SHADER_VERTEX].instance_odd = so.odd;
1784 ctx->payloads[PIPE_SHADER_FRAGMENT].instance_odd = so.odd;
1785
1786 ctx->padded_count = pan_expand_shift_odd(so);
1787 } else {
1788 ctx->padded_count = ctx->vertex_count;
1789
1790 /* Reset instancing state */
1791 ctx->payloads[PIPE_SHADER_VERTEX].instance_shift = 0;
1792 ctx->payloads[PIPE_SHADER_VERTEX].instance_odd = 0;
1793 ctx->payloads[PIPE_SHADER_FRAGMENT].instance_shift = 0;
1794 ctx->payloads[PIPE_SHADER_FRAGMENT].instance_odd = 0;
1795 }
1796
1797 /* Fire off the draw itself */
1798 panfrost_queue_draw(ctx);
1799 }
1800
1801 /* CSO state */
1802
1803 static void
1804 panfrost_generic_cso_delete(struct pipe_context *pctx, void *hwcso)
1805 {
1806 free(hwcso);
1807 }
1808
1809 static void *
1810 panfrost_create_rasterizer_state(
1811 struct pipe_context *pctx,
1812 const struct pipe_rasterizer_state *cso)
1813 {
1814 struct panfrost_rasterizer *so = CALLOC_STRUCT(panfrost_rasterizer);
1815
1816 so->base = *cso;
1817
1818 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1819 so->tiler_gl_enables = 0x7;
1820
1821 if (cso->front_ccw)
1822 so->tiler_gl_enables |= MALI_FRONT_CCW_TOP;
1823
1824 if (cso->cull_face & PIPE_FACE_FRONT)
1825 so->tiler_gl_enables |= MALI_CULL_FACE_FRONT;
1826
1827 if (cso->cull_face & PIPE_FACE_BACK)
1828 so->tiler_gl_enables |= MALI_CULL_FACE_BACK;
1829
1830 return so;
1831 }
1832
1833 static void
1834 panfrost_bind_rasterizer_state(
1835 struct pipe_context *pctx,
1836 void *hwcso)
1837 {
1838 struct panfrost_context *ctx = pan_context(pctx);
1839
1840 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1841 if (!hwcso)
1842 return;
1843
1844 ctx->rasterizer = hwcso;
1845 ctx->dirty |= PAN_DIRTY_RASTERIZER;
1846
1847 ctx->fragment_shader_core.depth_units = ctx->rasterizer->base.offset_units;
1848 ctx->fragment_shader_core.depth_factor = ctx->rasterizer->base.offset_scale;
1849
1850 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1851 assert(ctx->rasterizer->base.offset_clamp == 0.0);
1852
1853 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1854
1855 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_DEPTH_RANGE_A, ctx->rasterizer->base.offset_tri);
1856 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_DEPTH_RANGE_B, ctx->rasterizer->base.offset_tri);
1857
1858 /* Point sprites are emulated */
1859
1860 struct panfrost_shader_state *variant =
1861 ctx->shader[PIPE_SHADER_FRAGMENT] ? &ctx->shader[PIPE_SHADER_FRAGMENT]->variants[ctx->shader[PIPE_SHADER_FRAGMENT]->active_variant] : NULL;
1862
1863 if (ctx->rasterizer->base.sprite_coord_enable || (variant && variant->point_sprite_mask))
1864 ctx->base.bind_fs_state(&ctx->base, ctx->shader[PIPE_SHADER_FRAGMENT]);
1865 }
1866
1867 static void *
1868 panfrost_create_vertex_elements_state(
1869 struct pipe_context *pctx,
1870 unsigned num_elements,
1871 const struct pipe_vertex_element *elements)
1872 {
1873 struct panfrost_vertex_state *so = CALLOC_STRUCT(panfrost_vertex_state);
1874
1875 so->num_elements = num_elements;
1876 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
1877
1878 for (int i = 0; i < num_elements; ++i) {
1879 so->hw[i].index = i;
1880
1881 enum pipe_format fmt = elements[i].src_format;
1882 const struct util_format_description *desc = util_format_description(fmt);
1883 so->hw[i].unknown1 = 0x2;
1884 so->hw[i].swizzle = panfrost_get_default_swizzle(desc->nr_channels);
1885
1886 so->hw[i].format = panfrost_find_format(desc);
1887
1888 /* The field itself should probably be shifted over */
1889 so->hw[i].src_offset = elements[i].src_offset;
1890 }
1891
1892 return so;
1893 }
1894
1895 static void
1896 panfrost_bind_vertex_elements_state(
1897 struct pipe_context *pctx,
1898 void *hwcso)
1899 {
1900 struct panfrost_context *ctx = pan_context(pctx);
1901
1902 ctx->vertex = hwcso;
1903 ctx->dirty |= PAN_DIRTY_VERTEX;
1904 }
1905
1906 static void *
1907 panfrost_create_shader_state(
1908 struct pipe_context *pctx,
1909 const struct pipe_shader_state *cso)
1910 {
1911 struct panfrost_shader_variants *so = CALLOC_STRUCT(panfrost_shader_variants);
1912 so->base = *cso;
1913
1914 /* Token deep copy to prevent memory corruption */
1915
1916 if (cso->type == PIPE_SHADER_IR_TGSI)
1917 so->base.tokens = tgsi_dup_tokens(so->base.tokens);
1918
1919 return so;
1920 }
1921
1922 static void
1923 panfrost_delete_shader_state(
1924 struct pipe_context *pctx,
1925 void *so)
1926 {
1927 struct panfrost_shader_variants *cso = (struct panfrost_shader_variants *) so;
1928
1929 if (cso->base.type == PIPE_SHADER_IR_TGSI) {
1930 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1931 }
1932
1933 free(so);
1934 }
1935
1936 static void *
1937 panfrost_create_sampler_state(
1938 struct pipe_context *pctx,
1939 const struct pipe_sampler_state *cso)
1940 {
1941 struct panfrost_sampler_state *so = CALLOC_STRUCT(panfrost_sampler_state);
1942 so->base = *cso;
1943
1944 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1945
1946 bool min_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST;
1947 bool mag_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST;
1948 bool mip_linear = cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR;
1949
1950 unsigned min_filter = min_nearest ? MALI_SAMP_MIN_NEAREST : 0;
1951 unsigned mag_filter = mag_nearest ? MALI_SAMP_MAG_NEAREST : 0;
1952 unsigned mip_filter = mip_linear ?
1953 (MALI_SAMP_MIP_LINEAR_1 | MALI_SAMP_MIP_LINEAR_2) : 0;
1954 unsigned normalized = cso->normalized_coords ? MALI_SAMP_NORM_COORDS : 0;
1955
1956 struct mali_sampler_descriptor sampler_descriptor = {
1957 .filter_mode = min_filter | mag_filter | mip_filter | normalized,
1958 .wrap_s = translate_tex_wrap(cso->wrap_s),
1959 .wrap_t = translate_tex_wrap(cso->wrap_t),
1960 .wrap_r = translate_tex_wrap(cso->wrap_r),
1961 .compare_func = panfrost_translate_alt_compare_func(cso->compare_func),
1962 .border_color = {
1963 cso->border_color.f[0],
1964 cso->border_color.f[1],
1965 cso->border_color.f[2],
1966 cso->border_color.f[3]
1967 },
1968 .min_lod = FIXED_16(cso->min_lod),
1969 .max_lod = FIXED_16(cso->max_lod),
1970 .seamless_cube_map = cso->seamless_cube_map,
1971 };
1972
1973 /* If necessary, we disable mipmapping in the sampler descriptor by
1974 * clamping the LOD as tight as possible (from 0 to epsilon,
1975 * essentially -- remember these are fixed point numbers, so
1976 * epsilon=1/256) */
1977
1978 if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE)
1979 sampler_descriptor.max_lod = sampler_descriptor.min_lod;
1980
1981 /* Enforce that there is something in the middle by adding epsilon*/
1982
1983 if (sampler_descriptor.min_lod == sampler_descriptor.max_lod)
1984 sampler_descriptor.max_lod++;
1985
1986 /* Sanity check */
1987 assert(sampler_descriptor.max_lod > sampler_descriptor.min_lod);
1988
1989 so->hw = sampler_descriptor;
1990
1991 return so;
1992 }
1993
1994 static void
1995 panfrost_bind_sampler_states(
1996 struct pipe_context *pctx,
1997 enum pipe_shader_type shader,
1998 unsigned start_slot, unsigned num_sampler,
1999 void **sampler)
2000 {
2001 assert(start_slot == 0);
2002
2003 struct panfrost_context *ctx = pan_context(pctx);
2004
2005 /* XXX: Should upload, not just copy? */
2006 ctx->sampler_count[shader] = num_sampler;
2007 memcpy(ctx->samplers[shader], sampler, num_sampler * sizeof (void *));
2008
2009 ctx->dirty |= PAN_DIRTY_SAMPLERS;
2010 }
2011
2012 static bool
2013 panfrost_variant_matches(
2014 struct panfrost_context *ctx,
2015 struct panfrost_shader_state *variant,
2016 enum pipe_shader_type type)
2017 {
2018 struct pipe_rasterizer_state *rasterizer = &ctx->rasterizer->base;
2019 struct pipe_alpha_state *alpha = &ctx->depth_stencil->alpha;
2020
2021 bool is_fragment = (type == PIPE_SHADER_FRAGMENT);
2022
2023 if (is_fragment && (alpha->enabled || variant->alpha_state.enabled)) {
2024 /* Make sure enable state is at least the same */
2025 if (alpha->enabled != variant->alpha_state.enabled) {
2026 return false;
2027 }
2028
2029 /* Check that the contents of the test are the same */
2030 bool same_func = alpha->func == variant->alpha_state.func;
2031 bool same_ref = alpha->ref_value == variant->alpha_state.ref_value;
2032
2033 if (!(same_func && same_ref)) {
2034 return false;
2035 }
2036 }
2037
2038 if (is_fragment && rasterizer && (rasterizer->sprite_coord_enable |
2039 variant->point_sprite_mask)) {
2040 /* Ensure the same varyings are turned to point sprites */
2041 if (rasterizer->sprite_coord_enable != variant->point_sprite_mask)
2042 return false;
2043
2044 /* Ensure the orientation is correct */
2045 bool upper_left =
2046 rasterizer->sprite_coord_mode ==
2047 PIPE_SPRITE_COORD_UPPER_LEFT;
2048
2049 if (variant->point_sprite_upper_left != upper_left)
2050 return false;
2051 }
2052
2053 /* Otherwise, we're good to go */
2054 return true;
2055 }
2056
2057 static void
2058 panfrost_bind_shader_state(
2059 struct pipe_context *pctx,
2060 void *hwcso,
2061 enum pipe_shader_type type)
2062 {
2063 struct panfrost_context *ctx = pan_context(pctx);
2064
2065 ctx->shader[type] = hwcso;
2066
2067 if (type == PIPE_SHADER_FRAGMENT)
2068 ctx->dirty |= PAN_DIRTY_FS;
2069 else
2070 ctx->dirty |= PAN_DIRTY_VS;
2071
2072 if (!hwcso) return;
2073
2074 /* Match the appropriate variant */
2075
2076 signed variant = -1;
2077 struct panfrost_shader_variants *variants = (struct panfrost_shader_variants *) hwcso;
2078
2079 for (unsigned i = 0; i < variants->variant_count; ++i) {
2080 if (panfrost_variant_matches(ctx, &variants->variants[i], type)) {
2081 variant = i;
2082 break;
2083 }
2084 }
2085
2086 if (variant == -1) {
2087 /* No variant matched, so create a new one */
2088 variant = variants->variant_count++;
2089 assert(variants->variant_count < MAX_SHADER_VARIANTS);
2090
2091 struct panfrost_shader_state *v =
2092 &variants->variants[variant];
2093
2094 v->base = hwcso;
2095
2096 if (type == PIPE_SHADER_FRAGMENT) {
2097 v->alpha_state = ctx->depth_stencil->alpha;
2098
2099 if (ctx->rasterizer) {
2100 v->point_sprite_mask = ctx->rasterizer->base.sprite_coord_enable;
2101 v->point_sprite_upper_left =
2102 ctx->rasterizer->base.sprite_coord_mode ==
2103 PIPE_SPRITE_COORD_UPPER_LEFT;
2104 }
2105 }
2106
2107 variants->variants[variant].tripipe = malloc(sizeof(struct mali_shader_meta));
2108
2109 }
2110
2111 /* Select this variant */
2112 variants->active_variant = variant;
2113
2114 struct panfrost_shader_state *shader_state = &variants->variants[variant];
2115 assert(panfrost_variant_matches(ctx, shader_state, type));
2116
2117 /* We finally have a variant, so compile it */
2118
2119 if (!shader_state->compiled) {
2120 panfrost_shader_compile(ctx, shader_state->tripipe, NULL,
2121 panfrost_job_type_for_pipe(type), shader_state);
2122
2123 shader_state->compiled = true;
2124 }
2125 }
2126
2127 static void
2128 panfrost_bind_vs_state(struct pipe_context *pctx, void *hwcso)
2129 {
2130 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
2131 }
2132
2133 static void
2134 panfrost_bind_fs_state(struct pipe_context *pctx, void *hwcso)
2135 {
2136 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
2137 }
2138
2139 static void
2140 panfrost_set_vertex_buffers(
2141 struct pipe_context *pctx,
2142 unsigned start_slot,
2143 unsigned num_buffers,
2144 const struct pipe_vertex_buffer *buffers)
2145 {
2146 struct panfrost_context *ctx = pan_context(pctx);
2147
2148 util_set_vertex_buffers_mask(ctx->vertex_buffers, &ctx->vb_mask, buffers, start_slot, num_buffers);
2149 }
2150
2151 static void
2152 panfrost_set_constant_buffer(
2153 struct pipe_context *pctx,
2154 enum pipe_shader_type shader, uint index,
2155 const struct pipe_constant_buffer *buf)
2156 {
2157 struct panfrost_context *ctx = pan_context(pctx);
2158 struct panfrost_constant_buffer *pbuf = &ctx->constant_buffer[shader];
2159
2160 util_copy_constant_buffer(&pbuf->cb[index], buf);
2161
2162 unsigned mask = (1 << index);
2163
2164 if (unlikely(!buf)) {
2165 pbuf->enabled_mask &= ~mask;
2166 pbuf->dirty_mask &= ~mask;
2167 return;
2168 }
2169
2170 pbuf->enabled_mask |= mask;
2171 pbuf->dirty_mask |= mask;
2172 }
2173
2174 static void
2175 panfrost_set_stencil_ref(
2176 struct pipe_context *pctx,
2177 const struct pipe_stencil_ref *ref)
2178 {
2179 struct panfrost_context *ctx = pan_context(pctx);
2180 ctx->stencil_ref = *ref;
2181
2182 /* Shader core dirty */
2183 ctx->dirty |= PAN_DIRTY_FS;
2184 }
2185
2186 static enum mali_texture_type
2187 panfrost_translate_texture_type(enum pipe_texture_target t) {
2188 switch (t)
2189 {
2190 case PIPE_BUFFER:
2191 case PIPE_TEXTURE_1D:
2192 case PIPE_TEXTURE_1D_ARRAY:
2193 return MALI_TEX_1D;
2194
2195 case PIPE_TEXTURE_2D:
2196 case PIPE_TEXTURE_2D_ARRAY:
2197 case PIPE_TEXTURE_RECT:
2198 return MALI_TEX_2D;
2199
2200 case PIPE_TEXTURE_3D:
2201 return MALI_TEX_3D;
2202
2203 case PIPE_TEXTURE_CUBE:
2204 case PIPE_TEXTURE_CUBE_ARRAY:
2205 return MALI_TEX_CUBE;
2206
2207 default:
2208 unreachable("Unknown target");
2209 }
2210 }
2211
2212 static struct pipe_sampler_view *
2213 panfrost_create_sampler_view(
2214 struct pipe_context *pctx,
2215 struct pipe_resource *texture,
2216 const struct pipe_sampler_view *template)
2217 {
2218 struct panfrost_sampler_view *so = rzalloc(pctx, struct panfrost_sampler_view);
2219 int bytes_per_pixel = util_format_get_blocksize(texture->format);
2220
2221 pipe_reference(NULL, &texture->reference);
2222
2223 struct panfrost_resource *prsrc = (struct panfrost_resource *) texture;
2224 assert(prsrc->bo);
2225
2226 so->base = *template;
2227 so->base.texture = texture;
2228 so->base.reference.count = 1;
2229 so->base.context = pctx;
2230
2231 /* sampler_views correspond to texture descriptors, minus the texture
2232 * (data) itself. So, we serialise the descriptor here and cache it for
2233 * later. */
2234
2235 /* TODO: Detect from format better */
2236 const struct util_format_description *desc = util_format_description(prsrc->base.format);
2237
2238 unsigned char user_swizzle[4] = {
2239 template->swizzle_r,
2240 template->swizzle_g,
2241 template->swizzle_b,
2242 template->swizzle_a
2243 };
2244
2245 enum mali_format format = panfrost_find_format(desc);
2246
2247 /* Check if we need to set a custom stride by computing the "expected"
2248 * stride and comparing it to what the BO actually wants. Only applies
2249 * to linear textures, since tiled/compressed textures have strict
2250 * alignment requirements for their strides as it is */
2251
2252 unsigned first_level = template->u.tex.first_level;
2253 unsigned last_level = template->u.tex.last_level;
2254
2255 if (prsrc->layout == PAN_LINEAR) {
2256 for (unsigned l = first_level; l <= last_level; ++l) {
2257 unsigned actual_stride = prsrc->slices[l].stride;
2258 unsigned width = u_minify(texture->width0, l);
2259 unsigned comp_stride = width * bytes_per_pixel;
2260
2261 if (comp_stride != actual_stride) {
2262 so->manual_stride = true;
2263 break;
2264 }
2265 }
2266 }
2267
2268 /* In the hardware, array_size refers specifically to array textures,
2269 * whereas in Gallium, it also covers cubemaps */
2270
2271 unsigned array_size = texture->array_size;
2272
2273 if (template->target == PIPE_TEXTURE_CUBE) {
2274 /* TODO: Cubemap arrays */
2275 assert(array_size == 6);
2276 array_size /= 6;
2277 }
2278
2279 struct mali_texture_descriptor texture_descriptor = {
2280 .width = MALI_POSITIVE(u_minify(texture->width0, first_level)),
2281 .height = MALI_POSITIVE(u_minify(texture->height0, first_level)),
2282 .depth = MALI_POSITIVE(u_minify(texture->depth0, first_level)),
2283 .array_size = MALI_POSITIVE(array_size),
2284
2285 /* TODO: Decode */
2286 .format = {
2287 .swizzle = panfrost_translate_swizzle_4(desc->swizzle),
2288 .format = format,
2289
2290 .srgb = desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB,
2291 .type = panfrost_translate_texture_type(template->target),
2292 },
2293
2294 .swizzle = panfrost_translate_swizzle_4(user_swizzle)
2295 };
2296
2297 texture_descriptor.nr_mipmap_levels = last_level - first_level;
2298
2299 so->hw = texture_descriptor;
2300
2301 return (struct pipe_sampler_view *) so;
2302 }
2303
2304 static void
2305 panfrost_set_sampler_views(
2306 struct pipe_context *pctx,
2307 enum pipe_shader_type shader,
2308 unsigned start_slot, unsigned num_views,
2309 struct pipe_sampler_view **views)
2310 {
2311 struct panfrost_context *ctx = pan_context(pctx);
2312
2313 assert(start_slot == 0);
2314
2315 unsigned new_nr = 0;
2316 for (unsigned i = 0; i < num_views; ++i) {
2317 if (views[i])
2318 new_nr = i + 1;
2319 }
2320
2321 ctx->sampler_view_count[shader] = new_nr;
2322 memcpy(ctx->sampler_views[shader], views, num_views * sizeof (void *));
2323
2324 ctx->dirty |= PAN_DIRTY_TEXTURES;
2325 }
2326
2327 static void
2328 panfrost_sampler_view_destroy(
2329 struct pipe_context *pctx,
2330 struct pipe_sampler_view *view)
2331 {
2332 pipe_resource_reference(&view->texture, NULL);
2333 ralloc_free(view);
2334 }
2335
2336 static void
2337 panfrost_set_shader_buffers(
2338 struct pipe_context *pctx,
2339 enum pipe_shader_type shader,
2340 unsigned start, unsigned count,
2341 const struct pipe_shader_buffer *buffers,
2342 unsigned writable_bitmask)
2343 {
2344 struct panfrost_context *ctx = pan_context(pctx);
2345
2346 util_set_shader_buffers_mask(ctx->ssbo[shader], &ctx->ssbo_mask[shader],
2347 buffers, start, count);
2348 }
2349
2350 /* Hints that a framebuffer should use AFBC where possible */
2351
2352 static void
2353 panfrost_hint_afbc(
2354 struct panfrost_screen *screen,
2355 const struct pipe_framebuffer_state *fb)
2356 {
2357 /* AFBC implemenation incomplete; hide it */
2358 if (!(pan_debug & PAN_DBG_AFBC)) return;
2359
2360 /* Hint AFBC to the resources bound to each color buffer */
2361
2362 for (unsigned i = 0; i < fb->nr_cbufs; ++i) {
2363 struct pipe_surface *surf = fb->cbufs[i];
2364 struct panfrost_resource *rsrc = pan_resource(surf->texture);
2365 panfrost_resource_hint_layout(screen, rsrc, PAN_AFBC, 1);
2366 }
2367
2368 /* Also hint it to the depth buffer */
2369
2370 if (fb->zsbuf) {
2371 struct panfrost_resource *rsrc = pan_resource(fb->zsbuf->texture);
2372 panfrost_resource_hint_layout(screen, rsrc, PAN_AFBC, 1);
2373 }
2374 }
2375
2376 static void
2377 panfrost_set_framebuffer_state(struct pipe_context *pctx,
2378 const struct pipe_framebuffer_state *fb)
2379 {
2380 struct panfrost_context *ctx = pan_context(pctx);
2381
2382 /* Flush when switching framebuffers, but not if the framebuffer
2383 * state is being restored by u_blitter
2384 */
2385
2386 struct panfrost_job *job = panfrost_get_job_for_fbo(ctx);
2387 bool is_scanout = panfrost_is_scanout(ctx);
2388 bool has_draws = job->last_job.gpu;
2389
2390 if (!ctx->wallpaper_batch && (!is_scanout || has_draws)) {
2391 panfrost_flush(pctx, NULL, PIPE_FLUSH_END_OF_FRAME);
2392 }
2393
2394 util_copy_framebuffer_state(&ctx->pipe_framebuffer, fb);
2395
2396 /* Given that we're rendering, we'd love to have compression */
2397 struct panfrost_screen *screen = pan_screen(ctx->base.screen);
2398
2399 panfrost_hint_afbc(screen, &ctx->pipe_framebuffer);
2400
2401 if (screen->require_sfbd)
2402 ctx->vt_framebuffer_sfbd = panfrost_emit_sfbd(ctx, ~0);
2403 else
2404 ctx->vt_framebuffer_mfbd = panfrost_emit_mfbd(ctx, ~0);
2405
2406 panfrost_attach_vt_framebuffer(ctx, false);
2407 }
2408
2409 static void *
2410 panfrost_create_depth_stencil_state(struct pipe_context *pipe,
2411 const struct pipe_depth_stencil_alpha_state *depth_stencil)
2412 {
2413 return mem_dup(depth_stencil, sizeof(*depth_stencil));
2414 }
2415
2416 static void
2417 panfrost_bind_depth_stencil_state(struct pipe_context *pipe,
2418 void *cso)
2419 {
2420 struct panfrost_context *ctx = pan_context(pipe);
2421 struct pipe_depth_stencil_alpha_state *depth_stencil = cso;
2422 ctx->depth_stencil = depth_stencil;
2423
2424 if (!depth_stencil)
2425 return;
2426
2427 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2428 * emulated in the fragment shader */
2429
2430 if (depth_stencil->alpha.enabled) {
2431 /* We need to trigger a new shader (maybe) */
2432 ctx->base.bind_fs_state(&ctx->base, ctx->shader[PIPE_SHADER_FRAGMENT]);
2433 }
2434
2435 /* Stencil state */
2436 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_STENCIL_TEST, depth_stencil->stencil[0].enabled);
2437
2438 panfrost_make_stencil_state(&depth_stencil->stencil[0], &ctx->fragment_shader_core.stencil_front);
2439 ctx->fragment_shader_core.stencil_mask_front = depth_stencil->stencil[0].writemask;
2440
2441 /* If back-stencil is not enabled, use the front values */
2442 bool back_enab = ctx->depth_stencil->stencil[1].enabled;
2443 unsigned back_index = back_enab ? 1 : 0;
2444
2445 panfrost_make_stencil_state(&depth_stencil->stencil[back_index], &ctx->fragment_shader_core.stencil_back);
2446 ctx->fragment_shader_core.stencil_mask_back = depth_stencil->stencil[back_index].writemask;
2447
2448 /* Depth state (TODO: Refactor) */
2449 SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_DEPTH_TEST, depth_stencil->depth.enabled);
2450
2451 int func = depth_stencil->depth.enabled ? depth_stencil->depth.func : PIPE_FUNC_ALWAYS;
2452
2453 ctx->fragment_shader_core.unknown2_3 &= ~MALI_DEPTH_FUNC_MASK;
2454 ctx->fragment_shader_core.unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func));
2455
2456 /* Bounds test not implemented */
2457 assert(!depth_stencil->depth.bounds_test);
2458
2459 ctx->dirty |= PAN_DIRTY_FS;
2460 }
2461
2462 static void
2463 panfrost_delete_depth_stencil_state(struct pipe_context *pipe, void *depth)
2464 {
2465 free( depth );
2466 }
2467
2468 static void
2469 panfrost_set_sample_mask(struct pipe_context *pipe,
2470 unsigned sample_mask)
2471 {
2472 }
2473
2474 static void
2475 panfrost_set_clip_state(struct pipe_context *pipe,
2476 const struct pipe_clip_state *clip)
2477 {
2478 //struct panfrost_context *panfrost = pan_context(pipe);
2479 }
2480
2481 static void
2482 panfrost_set_viewport_states(struct pipe_context *pipe,
2483 unsigned start_slot,
2484 unsigned num_viewports,
2485 const struct pipe_viewport_state *viewports)
2486 {
2487 struct panfrost_context *ctx = pan_context(pipe);
2488
2489 assert(start_slot == 0);
2490 assert(num_viewports == 1);
2491
2492 ctx->pipe_viewport = *viewports;
2493 }
2494
2495 static void
2496 panfrost_set_scissor_states(struct pipe_context *pipe,
2497 unsigned start_slot,
2498 unsigned num_scissors,
2499 const struct pipe_scissor_state *scissors)
2500 {
2501 struct panfrost_context *ctx = pan_context(pipe);
2502
2503 assert(start_slot == 0);
2504 assert(num_scissors == 1);
2505
2506 ctx->scissor = *scissors;
2507 }
2508
2509 static void
2510 panfrost_set_polygon_stipple(struct pipe_context *pipe,
2511 const struct pipe_poly_stipple *stipple)
2512 {
2513 //struct panfrost_context *panfrost = pan_context(pipe);
2514 }
2515
2516 static void
2517 panfrost_set_active_query_state(struct pipe_context *pipe,
2518 bool enable)
2519 {
2520 //struct panfrost_context *panfrost = pan_context(pipe);
2521 }
2522
2523 static void
2524 panfrost_destroy(struct pipe_context *pipe)
2525 {
2526 struct panfrost_context *panfrost = pan_context(pipe);
2527 struct panfrost_screen *screen = pan_screen(pipe->screen);
2528
2529 if (panfrost->blitter)
2530 util_blitter_destroy(panfrost->blitter);
2531
2532 if (panfrost->blitter_wallpaper)
2533 util_blitter_destroy(panfrost->blitter_wallpaper);
2534
2535 panfrost_drm_free_slab(screen, &panfrost->scratchpad);
2536 panfrost_drm_free_slab(screen, &panfrost->shaders);
2537 panfrost_drm_free_slab(screen, &panfrost->tiler_heap);
2538 panfrost_drm_free_slab(screen, &panfrost->tiler_polygon_list);
2539 panfrost_drm_free_slab(screen, &panfrost->tiler_dummy);
2540
2541 ralloc_free(pipe);
2542 }
2543
2544 static struct pipe_query *
2545 panfrost_create_query(struct pipe_context *pipe,
2546 unsigned type,
2547 unsigned index)
2548 {
2549 struct panfrost_query *q = rzalloc(pipe, struct panfrost_query);
2550
2551 q->type = type;
2552 q->index = index;
2553
2554 return (struct pipe_query *) q;
2555 }
2556
2557 static void
2558 panfrost_destroy_query(struct pipe_context *pipe, struct pipe_query *q)
2559 {
2560 ralloc_free(q);
2561 }
2562
2563 static bool
2564 panfrost_begin_query(struct pipe_context *pipe, struct pipe_query *q)
2565 {
2566 struct panfrost_context *ctx = pan_context(pipe);
2567 struct panfrost_query *query = (struct panfrost_query *) q;
2568
2569 switch (query->type) {
2570 case PIPE_QUERY_OCCLUSION_COUNTER:
2571 case PIPE_QUERY_OCCLUSION_PREDICATE:
2572 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
2573 /* Allocate a word for the query results to be stored */
2574 query->transfer = panfrost_allocate_transient(ctx, sizeof(unsigned));
2575
2576 ctx->occlusion_query = query;
2577
2578 break;
2579 }
2580
2581 default:
2582 DBG("Skipping query %d\n", query->type);
2583 break;
2584 }
2585
2586 return true;
2587 }
2588
2589 static bool
2590 panfrost_end_query(struct pipe_context *pipe, struct pipe_query *q)
2591 {
2592 struct panfrost_context *ctx = pan_context(pipe);
2593 ctx->occlusion_query = NULL;
2594 return true;
2595 }
2596
2597 static bool
2598 panfrost_get_query_result(struct pipe_context *pipe,
2599 struct pipe_query *q,
2600 bool wait,
2601 union pipe_query_result *vresult)
2602 {
2603 /* STUB */
2604 struct panfrost_query *query = (struct panfrost_query *) q;
2605
2606 /* We need to flush out the jobs to actually run the counter, TODO
2607 * check wait, TODO wallpaper after if needed */
2608
2609 panfrost_flush(pipe, NULL, PIPE_FLUSH_END_OF_FRAME);
2610
2611 switch (query->type) {
2612 case PIPE_QUERY_OCCLUSION_COUNTER:
2613 case PIPE_QUERY_OCCLUSION_PREDICATE:
2614 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
2615 /* Read back the query results */
2616 unsigned *result = (unsigned *) query->transfer.cpu;
2617 unsigned passed = *result;
2618
2619 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
2620 vresult->u64 = passed;
2621 } else {
2622 vresult->b = !!passed;
2623 }
2624
2625 break;
2626 }
2627 default:
2628 DBG("Skipped query get %d\n", query->type);
2629 break;
2630 }
2631
2632 return true;
2633 }
2634
2635 static struct pipe_stream_output_target *
2636 panfrost_create_stream_output_target(struct pipe_context *pctx,
2637 struct pipe_resource *prsc,
2638 unsigned buffer_offset,
2639 unsigned buffer_size)
2640 {
2641 struct pipe_stream_output_target *target;
2642
2643 target = rzalloc(pctx, struct pipe_stream_output_target);
2644
2645 if (!target)
2646 return NULL;
2647
2648 pipe_reference_init(&target->reference, 1);
2649 pipe_resource_reference(&target->buffer, prsc);
2650
2651 target->context = pctx;
2652 target->buffer_offset = buffer_offset;
2653 target->buffer_size = buffer_size;
2654
2655 return target;
2656 }
2657
2658 static void
2659 panfrost_stream_output_target_destroy(struct pipe_context *pctx,
2660 struct pipe_stream_output_target *target)
2661 {
2662 pipe_resource_reference(&target->buffer, NULL);
2663 ralloc_free(target);
2664 }
2665
2666 static void
2667 panfrost_set_stream_output_targets(struct pipe_context *pctx,
2668 unsigned num_targets,
2669 struct pipe_stream_output_target **targets,
2670 const unsigned *offsets)
2671 {
2672 /* STUB */
2673 }
2674
2675 static void
2676 panfrost_setup_hardware(struct panfrost_context *ctx)
2677 {
2678 struct pipe_context *gallium = (struct pipe_context *) ctx;
2679 struct panfrost_screen *screen = pan_screen(gallium->screen);
2680
2681 panfrost_drm_allocate_slab(screen, &ctx->scratchpad, 64*4, false, 0, 0, 0);
2682 panfrost_drm_allocate_slab(screen, &ctx->shaders, 4096, true, PAN_ALLOCATE_EXECUTE, 0, 0);
2683 panfrost_drm_allocate_slab(screen, &ctx->tiler_heap, 4096, false, PAN_ALLOCATE_INVISIBLE | PAN_ALLOCATE_GROWABLE, 1, 128);
2684 panfrost_drm_allocate_slab(screen, &ctx->tiler_polygon_list, 128*128, false, PAN_ALLOCATE_INVISIBLE | PAN_ALLOCATE_GROWABLE, 1, 128);
2685 panfrost_drm_allocate_slab(screen, &ctx->tiler_dummy, 1, false, PAN_ALLOCATE_INVISIBLE, 0, 0);
2686 }
2687
2688 /* New context creation, which also does hardware initialisation since I don't
2689 * know the better way to structure this :smirk: */
2690
2691 struct pipe_context *
2692 panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags)
2693 {
2694 struct panfrost_context *ctx = rzalloc(screen, struct panfrost_context);
2695 struct panfrost_screen *pscreen = pan_screen(screen);
2696 memset(ctx, 0, sizeof(*ctx));
2697 struct pipe_context *gallium = (struct pipe_context *) ctx;
2698
2699 ctx->is_t6xx = pscreen->gpu_id < 0x0700; /* Literally, "earlier than T700" */
2700
2701 gallium->screen = screen;
2702
2703 gallium->destroy = panfrost_destroy;
2704
2705 gallium->set_framebuffer_state = panfrost_set_framebuffer_state;
2706
2707 gallium->flush = panfrost_flush;
2708 gallium->clear = panfrost_clear;
2709 gallium->draw_vbo = panfrost_draw_vbo;
2710
2711 gallium->set_vertex_buffers = panfrost_set_vertex_buffers;
2712 gallium->set_constant_buffer = panfrost_set_constant_buffer;
2713 gallium->set_shader_buffers = panfrost_set_shader_buffers;
2714
2715 gallium->set_stencil_ref = panfrost_set_stencil_ref;
2716
2717 gallium->create_sampler_view = panfrost_create_sampler_view;
2718 gallium->set_sampler_views = panfrost_set_sampler_views;
2719 gallium->sampler_view_destroy = panfrost_sampler_view_destroy;
2720
2721 gallium->create_rasterizer_state = panfrost_create_rasterizer_state;
2722 gallium->bind_rasterizer_state = panfrost_bind_rasterizer_state;
2723 gallium->delete_rasterizer_state = panfrost_generic_cso_delete;
2724
2725 gallium->create_vertex_elements_state = panfrost_create_vertex_elements_state;
2726 gallium->bind_vertex_elements_state = panfrost_bind_vertex_elements_state;
2727 gallium->delete_vertex_elements_state = panfrost_generic_cso_delete;
2728
2729 gallium->create_fs_state = panfrost_create_shader_state;
2730 gallium->delete_fs_state = panfrost_delete_shader_state;
2731 gallium->bind_fs_state = panfrost_bind_fs_state;
2732
2733 gallium->create_vs_state = panfrost_create_shader_state;
2734 gallium->delete_vs_state = panfrost_delete_shader_state;
2735 gallium->bind_vs_state = panfrost_bind_vs_state;
2736
2737 gallium->create_sampler_state = panfrost_create_sampler_state;
2738 gallium->delete_sampler_state = panfrost_generic_cso_delete;
2739 gallium->bind_sampler_states = panfrost_bind_sampler_states;
2740
2741 gallium->create_depth_stencil_alpha_state = panfrost_create_depth_stencil_state;
2742 gallium->bind_depth_stencil_alpha_state = panfrost_bind_depth_stencil_state;
2743 gallium->delete_depth_stencil_alpha_state = panfrost_delete_depth_stencil_state;
2744
2745 gallium->set_sample_mask = panfrost_set_sample_mask;
2746
2747 gallium->set_clip_state = panfrost_set_clip_state;
2748 gallium->set_viewport_states = panfrost_set_viewport_states;
2749 gallium->set_scissor_states = panfrost_set_scissor_states;
2750 gallium->set_polygon_stipple = panfrost_set_polygon_stipple;
2751 gallium->set_active_query_state = panfrost_set_active_query_state;
2752
2753 gallium->create_query = panfrost_create_query;
2754 gallium->destroy_query = panfrost_destroy_query;
2755 gallium->begin_query = panfrost_begin_query;
2756 gallium->end_query = panfrost_end_query;
2757 gallium->get_query_result = panfrost_get_query_result;
2758
2759 gallium->create_stream_output_target = panfrost_create_stream_output_target;
2760 gallium->stream_output_target_destroy = panfrost_stream_output_target_destroy;
2761 gallium->set_stream_output_targets = panfrost_set_stream_output_targets;
2762
2763 panfrost_resource_context_init(gallium);
2764 panfrost_blend_context_init(gallium);
2765 panfrost_compute_context_init(gallium);
2766
2767 panfrost_drm_init_context(ctx);
2768
2769 panfrost_setup_hardware(ctx);
2770
2771 /* XXX: leaks */
2772 gallium->stream_uploader = u_upload_create_default(gallium);
2773 gallium->const_uploader = gallium->stream_uploader;
2774 assert(gallium->stream_uploader);
2775
2776 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2777 ctx->draw_modes = (1 << (PIPE_PRIM_POLYGON + 1)) - 1;
2778
2779 ctx->primconvert = util_primconvert_create(gallium, ctx->draw_modes);
2780
2781 ctx->blitter = util_blitter_create(gallium);
2782 ctx->blitter_wallpaper = util_blitter_create(gallium);
2783
2784 assert(ctx->blitter);
2785 assert(ctx->blitter_wallpaper);
2786
2787 /* Prepare for render! */
2788
2789 panfrost_job_init(ctx);
2790 panfrost_emit_vertex_payload(ctx);
2791 panfrost_emit_tiler_payload(ctx);
2792 panfrost_invalidate_frame(ctx);
2793 panfrost_default_shader_backend(ctx);
2794
2795 return gallium;
2796 }