2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
57 #include "util/pan_lower_framebuffer.h"
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
62 struct panfrost_device
*device
= pan_device(batch
->ctx
->base
.screen
);
63 bool hierarchy
= !(device
->quirks
& MIDGARD_NO_HIER_TILING
);
64 struct midgard_tiler_descriptor t
= {0};
65 unsigned height
= batch
->key
.height
;
66 unsigned width
= batch
->key
.width
;
69 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
71 /* Compute the polygon header size and use that to offset the body */
73 unsigned header_size
= panfrost_tiler_header_size(
74 width
, height
, t
.hierarchy_mask
, hierarchy
);
76 t
.polygon_list_size
= panfrost_tiler_full_size(
77 width
, height
, t
.hierarchy_mask
, hierarchy
);
82 struct panfrost_bo
*tiler_heap
;
84 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
85 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
90 /* Allow the entire tiler heap */
91 t
.heap_start
= tiler_heap
->gpu
;
92 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
94 struct panfrost_bo
*tiler_dummy
;
96 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
97 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
99 /* The tiler is disabled, so don't allow the tiler heap */
100 t
.heap_start
= tiler_dummy
->gpu
;
101 t
.heap_end
= t
.heap_start
;
103 /* Use a dummy polygon list */
104 t
.polygon_list
= tiler_dummy
->gpu
;
106 /* Disable the tiler */
108 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
110 t
.hierarchy_mask
= MALI_TILER_USER
;
111 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
113 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
114 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
115 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
119 t
.polygon_list_body
=
120 t
.polygon_list
+ header_size
;
127 struct pipe_context
*pipe
,
129 const struct pipe_scissor_state
*scissor_state
,
130 const union pipe_color_union
*color
,
131 double depth
, unsigned stencil
)
133 struct panfrost_context
*ctx
= pan_context(pipe
);
135 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
136 * the existing batch targeting this FBO has draws. We could probably
137 * avoid that by replacing plain clears by quad-draws with a specific
138 * color/depth/stencil value, thus avoiding the generation of extra
141 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
143 panfrost_batch_add_fbo_bos(batch
);
144 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
147 /* Reset per-frame context, called on context initialisation as well as after
148 * flushing a frame */
151 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
153 /* TODO: When does this need to be handled? */
154 ctx
->active_queries
= true;
158 panfrost_writes_point_size(struct panfrost_context
*ctx
)
160 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
161 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
163 return vs
->writes_point_size
&& ctx
->active_prim
== PIPE_PRIM_POINTS
;
167 panfrost_vertex_state_upd_attr_offs(struct panfrost_context
*ctx
,
168 struct mali_vertex_tiler_postfix
*vertex_postfix
)
173 struct panfrost_vertex_state
*so
= ctx
->vertex
;
175 /* Fixup offsets for the second pass. Recall that the hardware
176 * calculates attribute addresses as:
178 * addr = base + (stride * vtx) + src_offset;
180 * However, on Mali, base must be aligned to 64-bytes, so we
183 * base' = base & ~63 = base - (base & 63)
185 * To compensate when using base' (see emit_vertex_data), we have
186 * to adjust src_offset by the masked off piece:
188 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
189 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
190 * = base + (stride * vtx) + src_offset
196 unsigned start
= vertex_postfix
->offset_start
;
198 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
199 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
200 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
202 /* Adjust by the masked off bits of the offset. Make sure we
203 * read src_offset from so->hw (which is not GPU visible)
204 * rather than target (which is) due to caching effects */
206 unsigned src_offset
= so
->pipe
[i
].src_offset
;
208 /* BOs aligned to 4k so guaranteed aligned to 64 */
209 src_offset
+= (buf
->buffer_offset
& 63);
211 /* Also, somewhat obscurely per-instance data needs to be
212 * offset in response to a delayed start in an indexed draw */
214 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
215 src_offset
-= buf
->stride
* start
;
217 so
->hw
[i
].src_offset
= src_offset
;
221 /* Compute number of UBOs active (more specifically, compute the highest UBO
222 * number addressable -- if there are gaps, include them in the count anyway).
223 * We always include UBO #0 in the count, since we *need* uniforms enabled for
227 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
229 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
230 return 32 - __builtin_clz(mask
);
233 /* The entire frame is in memory -- send it off to the kernel! */
237 struct pipe_context
*pipe
,
238 struct pipe_fence_handle
**fence
,
241 struct panfrost_context
*ctx
= pan_context(pipe
);
242 struct panfrost_device
*dev
= pan_device(pipe
->screen
);
243 uint32_t syncobj
= 0;
246 drmSyncobjCreate(dev
->fd
, 0, &syncobj
);
248 /* Submit all pending jobs */
249 panfrost_flush_all_batches(ctx
, syncobj
);
252 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, syncobj
);
253 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
254 *fence
= (struct pipe_fence_handle
*)f
;
257 if (dev
->debug
& PAN_DBG_TRACE
)
258 pandecode_next_frame();
262 panfrost_texture_barrier(struct pipe_context
*pipe
, unsigned flags
)
264 struct panfrost_context
*ctx
= pan_context(pipe
);
265 panfrost_flush_all_batches(ctx
, 0);
268 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
271 g2m_draw_mode(enum pipe_prim_type mode
)
276 DEFINE_CASE(LINE_LOOP
);
277 DEFINE_CASE(LINE_STRIP
);
278 DEFINE_CASE(TRIANGLES
);
279 DEFINE_CASE(TRIANGLE_STRIP
);
280 DEFINE_CASE(TRIANGLE_FAN
);
282 DEFINE_CASE(QUAD_STRIP
);
283 DEFINE_CASE(POLYGON
);
286 unreachable("Invalid draw mode");
293 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
295 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
297 /* Check if we're scissoring at all */
299 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
302 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
305 /* Count generated primitives (when there is no geom/tess shaders) for
306 * transform feedback */
309 panfrost_statistics_record(
310 struct panfrost_context
*ctx
,
311 const struct pipe_draw_info
*info
)
313 if (!ctx
->active_queries
)
316 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
317 ctx
->prims_generated
+= prims
;
319 if (!ctx
->streamout
.num_targets
)
322 ctx
->tf_prims_generated
+= prims
;
326 panfrost_update_streamout_offsets(struct panfrost_context
*ctx
)
328 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
331 count
= u_stream_outputs_for_vertices(ctx
->active_prim
,
333 ctx
->streamout
.offsets
[i
] += count
;
339 struct pipe_context
*pipe
,
340 const struct pipe_draw_info
*info
)
342 struct panfrost_context
*ctx
= pan_context(pipe
);
344 /* First of all, check the scissor to see if anything is drawn at all.
345 * If it's not, we drop the draw (mostly a conformance issue;
346 * well-behaved apps shouldn't hit this) */
348 if (panfrost_scissor_culls_everything(ctx
))
351 int mode
= info
->mode
;
353 /* Fallback unsupported restart index */
354 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
356 if (info
->primitive_restart
&& info
->index_size
357 && info
->restart_index
!= primitive_index
) {
358 util_draw_vbo_without_prim_restart(pipe
, info
);
362 /* Fallback for unsupported modes */
364 assert(ctx
->rasterizer
!= NULL
);
366 if (!(ctx
->draw_modes
& (1 << mode
))) {
367 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
368 mode
= PIPE_PRIM_TRIANGLE_FAN
;
370 if (info
->count
< 4) {
371 /* Degenerate case? */
375 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
376 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
381 /* Now that we have a guaranteed terminating path, find the job.
382 * Assignment commented out to prevent unused warning */
384 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
386 panfrost_batch_add_fbo_bos(batch
);
387 panfrost_batch_set_requirements(batch
);
389 /* Take into account a negative bias */
390 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
391 ctx
->instance_count
= info
->instance_count
;
392 ctx
->active_prim
= info
->mode
;
394 struct mali_vertex_tiler_prefix vertex_prefix
, tiler_prefix
;
395 struct mali_vertex_tiler_postfix vertex_postfix
, tiler_postfix
;
396 union midgard_primitive_size primitive_size
;
397 unsigned vertex_count
;
399 panfrost_vt_init(ctx
, PIPE_SHADER_VERTEX
, &vertex_prefix
, &vertex_postfix
);
400 panfrost_vt_init(ctx
, PIPE_SHADER_FRAGMENT
, &tiler_prefix
, &tiler_postfix
);
402 panfrost_vt_set_draw_info(ctx
, info
, g2m_draw_mode(mode
),
403 &vertex_postfix
, &tiler_prefix
,
404 &tiler_postfix
, &vertex_count
,
407 panfrost_statistics_record(ctx
, info
);
409 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
410 * vertex_count, 1) */
412 panfrost_pack_work_groups_fused(&vertex_prefix
, &tiler_prefix
,
413 1, vertex_count
, info
->instance_count
,
416 /* Emit all sort of descriptors. */
417 panfrost_emit_vertex_data(batch
, &vertex_postfix
);
418 panfrost_emit_varying_descriptor(batch
,
421 &vertex_postfix
, &tiler_postfix
,
423 panfrost_emit_shader_meta(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
424 panfrost_emit_shader_meta(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
425 panfrost_emit_vertex_attr_meta(batch
, &vertex_postfix
);
426 panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
427 panfrost_emit_sampler_descriptors(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
428 panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
429 panfrost_emit_texture_descriptors(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
430 panfrost_emit_const_buf(batch
, PIPE_SHADER_VERTEX
, &vertex_postfix
);
431 panfrost_emit_const_buf(batch
, PIPE_SHADER_FRAGMENT
, &tiler_postfix
);
432 panfrost_emit_viewport(batch
, &tiler_postfix
);
434 panfrost_vt_update_primitive_size(ctx
, &tiler_prefix
, &primitive_size
);
436 /* Fire off the draw itself */
437 panfrost_emit_vertex_tiler_jobs(batch
, &vertex_prefix
, &vertex_postfix
,
438 &tiler_prefix
, &tiler_postfix
,
441 /* Adjust the batch stack size based on the new shader stack sizes. */
442 panfrost_batch_adjust_stack_size(batch
);
444 /* Increment transform feedback offsets */
445 panfrost_update_streamout_offsets(ctx
);
451 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
457 panfrost_create_rasterizer_state(
458 struct pipe_context
*pctx
,
459 const struct pipe_rasterizer_state
*cso
)
461 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
469 panfrost_bind_rasterizer_state(
470 struct pipe_context
*pctx
,
473 struct panfrost_context
*ctx
= pan_context(pctx
);
475 ctx
->rasterizer
= hwcso
;
480 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
481 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
483 /* Point sprites are emulated */
485 struct panfrost_shader_state
*variant
= panfrost_get_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
487 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
488 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
492 panfrost_create_vertex_elements_state(
493 struct pipe_context
*pctx
,
494 unsigned num_elements
,
495 const struct pipe_vertex_element
*elements
)
497 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
498 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
500 so
->num_elements
= num_elements
;
501 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
503 for (int i
= 0; i
< num_elements
; ++i
) {
506 enum pipe_format fmt
= elements
[i
].src_format
;
507 const struct util_format_description
*desc
= util_format_description(fmt
);
508 so
->hw
[i
].unknown1
= 0x2;
510 if (dev
->quirks
& HAS_SWIZZLES
)
511 so
->hw
[i
].swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
);
513 so
->hw
[i
].swizzle
= panfrost_bifrost_swizzle(desc
->nr_channels
);
515 enum mali_format hw_format
= panfrost_pipe_format_table
[desc
->format
].hw
;
516 so
->hw
[i
].format
= hw_format
;
520 /* Let's also prepare vertex builtins */
521 so
->hw
[PAN_VERTEX_ID
].format
= MALI_R32UI
;
522 if (dev
->quirks
& HAS_SWIZZLES
)
523 so
->hw
[PAN_VERTEX_ID
].swizzle
= panfrost_get_default_swizzle(1);
525 so
->hw
[PAN_VERTEX_ID
].swizzle
= panfrost_bifrost_swizzle(1);
527 so
->hw
[PAN_INSTANCE_ID
].format
= MALI_R32UI
;
528 if (dev
->quirks
& HAS_SWIZZLES
)
529 so
->hw
[PAN_INSTANCE_ID
].swizzle
= panfrost_get_default_swizzle(1);
531 so
->hw
[PAN_INSTANCE_ID
].swizzle
= panfrost_bifrost_swizzle(1);
537 panfrost_bind_vertex_elements_state(
538 struct pipe_context
*pctx
,
541 struct panfrost_context
*ctx
= pan_context(pctx
);
546 panfrost_create_shader_state(
547 struct pipe_context
*pctx
,
548 const struct pipe_shader_state
*cso
,
549 enum pipe_shader_type stage
)
551 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
552 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
555 /* Token deep copy to prevent memory corruption */
557 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
558 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
560 /* Precompile for shader-db if we need to */
561 if (unlikely((dev
->debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
562 struct panfrost_context
*ctx
= pan_context(pctx
);
564 struct panfrost_shader_state state
;
565 uint64_t outputs_written
;
567 panfrost_shader_compile(ctx
, PIPE_SHADER_IR_NIR
,
569 tgsi_processor_to_shader_stage(stage
),
570 &state
, &outputs_written
);
577 panfrost_delete_shader_state(
578 struct pipe_context
*pctx
,
581 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
583 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
584 /* TODO: leaks TGSI tokens! */
587 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
588 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
589 panfrost_bo_unreference(shader_state
->bo
);
590 shader_state
->bo
= NULL
;
598 panfrost_create_sampler_state(
599 struct pipe_context
*pctx
,
600 const struct pipe_sampler_state
*cso
)
602 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
603 struct panfrost_device
*device
= pan_device(pctx
->screen
);
607 if (device
->quirks
& IS_BIFROST
)
608 panfrost_sampler_desc_init_bifrost(cso
, (struct mali_bifrost_sampler_packed
*) &so
->hw
);
610 panfrost_sampler_desc_init(cso
, &so
->hw
);
616 panfrost_bind_sampler_states(
617 struct pipe_context
*pctx
,
618 enum pipe_shader_type shader
,
619 unsigned start_slot
, unsigned num_sampler
,
622 assert(start_slot
== 0);
624 struct panfrost_context
*ctx
= pan_context(pctx
);
626 /* XXX: Should upload, not just copy? */
627 ctx
->sampler_count
[shader
] = num_sampler
;
628 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
632 panfrost_variant_matches(
633 struct panfrost_context
*ctx
,
634 struct panfrost_shader_state
*variant
,
635 enum pipe_shader_type type
)
637 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
638 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
640 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
642 if (variant
->outputs_read
) {
643 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
646 BITSET_FOREACH_SET(i
, &variant
->outputs_read
, 8) {
647 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
649 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
650 fmt
= fb
->cbufs
[i
]->format
;
652 const struct util_format_description
*desc
=
653 util_format_description(fmt
);
655 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
656 fmt
= PIPE_FORMAT_NONE
;
658 if (variant
->rt_formats
[i
] != fmt
)
663 /* Point sprites TODO on bifrost, always pass */
664 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
665 variant
->point_sprite_mask
)
666 && !(dev
->quirks
& IS_BIFROST
)) {
667 /* Ensure the same varyings are turned to point sprites */
668 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
671 /* Ensure the orientation is correct */
673 rasterizer
->sprite_coord_mode
==
674 PIPE_SPRITE_COORD_UPPER_LEFT
;
676 if (variant
->point_sprite_upper_left
!= upper_left
)
680 /* Otherwise, we're good to go */
685 * Fix an uncompiled shader's stream output info, and produce a bitmask
686 * of which VARYING_SLOT_* are captured for stream output.
688 * Core Gallium stores output->register_index as a "slot" number, where
689 * slots are assigned consecutively to all outputs in info->outputs_written.
690 * This naive packing of outputs doesn't work for us - we too have slots,
691 * but the layout is defined by the VUE map, which we won't have until we
692 * compile a specific shader variant. So, we remap these and simply store
693 * VARYING_SLOT_* in our copy's output->register_index fields.
695 * We then produce a bitmask of outputs which are used for SO.
697 * Implementation from iris.
701 update_so_info(struct pipe_stream_output_info
*so_info
,
702 uint64_t outputs_written
)
704 uint64_t so_outputs
= 0;
705 uint8_t reverse_map
[64] = {0};
708 while (outputs_written
)
709 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
711 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
712 struct pipe_stream_output
*output
= &so_info
->output
[i
];
714 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
715 output
->register_index
= reverse_map
[output
->register_index
];
717 so_outputs
|= 1ull << output
->register_index
;
724 panfrost_bind_shader_state(
725 struct pipe_context
*pctx
,
727 enum pipe_shader_type type
)
729 struct panfrost_context
*ctx
= pan_context(pctx
);
730 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
731 ctx
->shader
[type
] = hwcso
;
735 /* Match the appropriate variant */
738 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
740 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
741 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
748 /* No variant matched, so create a new one */
749 variant
= variants
->variant_count
++;
751 if (variants
->variant_count
> variants
->variant_space
) {
752 unsigned old_space
= variants
->variant_space
;
754 variants
->variant_space
*= 2;
755 if (variants
->variant_space
== 0)
756 variants
->variant_space
= 1;
758 /* Arbitrary limit to stop runaway programs from
759 * creating an unbounded number of shader variants. */
760 assert(variants
->variant_space
< 1024);
762 unsigned msize
= sizeof(struct panfrost_shader_state
);
763 variants
->variants
= realloc(variants
->variants
,
764 variants
->variant_space
* msize
);
766 memset(&variants
->variants
[old_space
], 0,
767 (variants
->variant_space
- old_space
) * msize
);
770 struct panfrost_shader_state
*v
=
771 &variants
->variants
[variant
];
773 if (type
== PIPE_SHADER_FRAGMENT
) {
774 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
775 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
776 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
778 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
779 fmt
= fb
->cbufs
[i
]->format
;
781 const struct util_format_description
*desc
=
782 util_format_description(fmt
);
784 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
785 fmt
= PIPE_FORMAT_NONE
;
787 v
->rt_formats
[i
] = fmt
;
790 /* Point sprites are TODO on Bifrost */
791 if (ctx
->rasterizer
&& !(dev
->quirks
& IS_BIFROST
)) {
792 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
793 v
->point_sprite_upper_left
=
794 ctx
->rasterizer
->base
.sprite_coord_mode
==
795 PIPE_SPRITE_COORD_UPPER_LEFT
;
800 /* Select this variant */
801 variants
->active_variant
= variant
;
803 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
804 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
806 /* We finally have a variant, so compile it */
808 if (!shader_state
->compiled
) {
809 uint64_t outputs_written
= 0;
811 panfrost_shader_compile(ctx
, variants
->base
.type
,
812 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
813 variants
->base
.ir
.nir
:
814 variants
->base
.tokens
,
815 tgsi_processor_to_shader_stage(type
),
819 shader_state
->compiled
= true;
821 /* Fixup the stream out information, since what Gallium returns
822 * normally is mildly insane */
824 shader_state
->stream_output
= variants
->base
.stream_output
;
825 shader_state
->so_mask
=
826 update_so_info(&shader_state
->stream_output
, outputs_written
);
831 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
833 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
837 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
839 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
843 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
845 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
849 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
851 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
855 panfrost_set_vertex_buffers(
856 struct pipe_context
*pctx
,
858 unsigned num_buffers
,
859 const struct pipe_vertex_buffer
*buffers
)
861 struct panfrost_context
*ctx
= pan_context(pctx
);
863 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
867 panfrost_set_constant_buffer(
868 struct pipe_context
*pctx
,
869 enum pipe_shader_type shader
, uint index
,
870 const struct pipe_constant_buffer
*buf
)
872 struct panfrost_context
*ctx
= pan_context(pctx
);
873 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
875 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
877 unsigned mask
= (1 << index
);
879 if (unlikely(!buf
)) {
880 pbuf
->enabled_mask
&= ~mask
;
881 pbuf
->dirty_mask
&= ~mask
;
885 pbuf
->enabled_mask
|= mask
;
886 pbuf
->dirty_mask
|= mask
;
890 panfrost_set_stencil_ref(
891 struct pipe_context
*pctx
,
892 const struct pipe_stencil_ref
*ref
)
894 struct panfrost_context
*ctx
= pan_context(pctx
);
895 ctx
->stencil_ref
= *ref
;
899 panfrost_create_sampler_view_bo(struct panfrost_sampler_view
*so
,
900 struct pipe_context
*pctx
,
901 struct pipe_resource
*texture
)
903 struct panfrost_device
*device
= pan_device(pctx
->screen
);
904 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*)texture
;
905 enum pipe_format format
= so
->base
.format
;
908 /* Format to access the stencil portion of a Z32_S8 texture */
909 if (format
== PIPE_FORMAT_X32_S8X24_UINT
) {
910 assert(prsrc
->separate_stencil
);
911 texture
= &prsrc
->separate_stencil
->base
;
912 prsrc
= (struct panfrost_resource
*)texture
;
913 format
= texture
->format
;
916 const struct util_format_description
*desc
= util_format_description(format
);
918 bool fake_rgtc
= !panfrost_supports_compressed_format(device
, MALI_BC4_UNORM
);
920 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
&& fake_rgtc
) {
922 format
= PIPE_FORMAT_R8G8B8A8_SNORM
;
924 format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
925 desc
= util_format_description(format
);
928 so
->texture_bo
= prsrc
->bo
->gpu
;
929 so
->modifier
= prsrc
->modifier
;
931 unsigned char user_swizzle
[4] = {
938 /* In the hardware, array_size refers specifically to array textures,
939 * whereas in Gallium, it also covers cubemaps */
941 unsigned array_size
= texture
->array_size
;
942 unsigned depth
= texture
->depth0
;
944 if (so
->base
.target
== PIPE_TEXTURE_CUBE
) {
945 /* TODO: Cubemap arrays */
946 assert(array_size
== 6);
950 /* MSAA only supported for 2D textures (and 2D texture arrays via an
951 * extension currently unimplemented */
953 if (so
->base
.target
== PIPE_TEXTURE_2D
) {
955 depth
= texture
->nr_samples
;
957 /* MSAA only supported for 2D textures */
958 assert(texture
->nr_samples
<= 1);
961 enum mali_texture_type type
=
962 panfrost_translate_texture_type(so
->base
.target
);
964 if (device
->quirks
& IS_BIFROST
) {
965 unsigned char composed_swizzle
[4];
966 util_format_compose_swizzles(desc
->swizzle
, user_swizzle
, composed_swizzle
);
968 unsigned size
= panfrost_estimate_texture_payload_size(
969 so
->base
.u
.tex
.first_level
,
970 so
->base
.u
.tex
.last_level
,
971 so
->base
.u
.tex
.first_layer
,
972 so
->base
.u
.tex
.last_layer
,
974 type
, prsrc
->modifier
);
976 so
->bo
= panfrost_bo_create(device
, size
, 0);
978 so
->bifrost_descriptor
= rzalloc(pctx
, struct bifrost_texture_descriptor
);
979 panfrost_new_texture_bifrost(
980 so
->bifrost_descriptor
,
981 texture
->width0
, texture
->height0
,
984 type
, prsrc
->modifier
,
985 so
->base
.u
.tex
.first_level
,
986 so
->base
.u
.tex
.last_level
,
987 so
->base
.u
.tex
.first_layer
,
988 so
->base
.u
.tex
.last_layer
,
990 prsrc
->cubemap_stride
,
991 panfrost_translate_swizzle_4(composed_swizzle
),
996 unsigned size
= panfrost_estimate_texture_payload_size(
997 so
->base
.u
.tex
.first_level
,
998 so
->base
.u
.tex
.last_level
,
999 so
->base
.u
.tex
.first_layer
,
1000 so
->base
.u
.tex
.last_layer
,
1001 texture
->nr_samples
,
1002 type
, prsrc
->modifier
);
1003 size
+= sizeof(struct mali_texture_descriptor
);
1005 so
->bo
= panfrost_bo_create(device
, size
, 0);
1007 panfrost_new_texture(
1009 texture
->width0
, texture
->height0
,
1012 type
, prsrc
->modifier
,
1013 so
->base
.u
.tex
.first_level
,
1014 so
->base
.u
.tex
.last_level
,
1015 so
->base
.u
.tex
.first_layer
,
1016 so
->base
.u
.tex
.last_layer
,
1017 texture
->nr_samples
,
1018 prsrc
->cubemap_stride
,
1019 panfrost_translate_swizzle_4(user_swizzle
),
1025 static struct pipe_sampler_view
*
1026 panfrost_create_sampler_view(
1027 struct pipe_context
*pctx
,
1028 struct pipe_resource
*texture
,
1029 const struct pipe_sampler_view
*template)
1031 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
1033 pipe_reference(NULL
, &texture
->reference
);
1035 so
->base
= *template;
1036 so
->base
.texture
= texture
;
1037 so
->base
.reference
.count
= 1;
1038 so
->base
.context
= pctx
;
1040 panfrost_create_sampler_view_bo(so
, pctx
, texture
);
1042 return (struct pipe_sampler_view
*) so
;
1046 panfrost_set_sampler_views(
1047 struct pipe_context
*pctx
,
1048 enum pipe_shader_type shader
,
1049 unsigned start_slot
, unsigned num_views
,
1050 struct pipe_sampler_view
**views
)
1052 struct panfrost_context
*ctx
= pan_context(pctx
);
1053 unsigned new_nr
= 0;
1056 assert(start_slot
== 0);
1058 for (i
= 0; i
< num_views
; ++i
) {
1061 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1065 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
1066 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1069 ctx
->sampler_view_count
[shader
] = new_nr
;
1073 panfrost_sampler_view_destroy(
1074 struct pipe_context
*pctx
,
1075 struct pipe_sampler_view
*pview
)
1077 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
1079 pipe_resource_reference(&pview
->texture
, NULL
);
1080 panfrost_bo_unreference(view
->bo
);
1081 if (view
->bifrost_descriptor
)
1082 ralloc_free(view
->bifrost_descriptor
);
1087 panfrost_set_shader_buffers(
1088 struct pipe_context
*pctx
,
1089 enum pipe_shader_type shader
,
1090 unsigned start
, unsigned count
,
1091 const struct pipe_shader_buffer
*buffers
,
1092 unsigned writable_bitmask
)
1094 struct panfrost_context
*ctx
= pan_context(pctx
);
1096 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
1097 buffers
, start
, count
);
1101 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1102 const struct pipe_framebuffer_state
*fb
)
1104 struct panfrost_context
*ctx
= pan_context(pctx
);
1106 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
1108 panfrost_invalidate_frame(ctx
);
1110 /* We may need to generate a new variant if the fragment shader is
1111 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1112 struct panfrost_shader_variants
*fs
= ctx
->shader
[PIPE_SHADER_FRAGMENT
];
1114 if (fs
&& fs
->variant_count
&& fs
->variants
[fs
->active_variant
].outputs_read
)
1115 ctx
->base
.bind_fs_state(&ctx
->base
, fs
);
1118 static inline unsigned
1119 pan_pipe_to_stencil_op(enum pipe_stencil_op in
)
1122 case PIPE_STENCIL_OP_KEEP
: return MALI_STENCIL_OP_KEEP
;
1123 case PIPE_STENCIL_OP_ZERO
: return MALI_STENCIL_OP_ZERO
;
1124 case PIPE_STENCIL_OP_REPLACE
: return MALI_STENCIL_OP_REPLACE
;
1125 case PIPE_STENCIL_OP_INCR
: return MALI_STENCIL_OP_INCR_SAT
;
1126 case PIPE_STENCIL_OP_DECR
: return MALI_STENCIL_OP_DECR_SAT
;
1127 case PIPE_STENCIL_OP_INCR_WRAP
: return MALI_STENCIL_OP_INCR_WRAP
;
1128 case PIPE_STENCIL_OP_DECR_WRAP
: return MALI_STENCIL_OP_DECR_WRAP
;
1129 case PIPE_STENCIL_OP_INVERT
: return MALI_STENCIL_OP_INVERT
;
1130 default: unreachable("Invalid stencil op");
1135 pan_pipe_to_stencil(const struct pipe_stencil_state
*in
, void *out
)
1137 pan_pack(out
, STENCIL
, cfg
) {
1138 cfg
.mask
= in
->valuemask
;
1139 cfg
.compare_function
= panfrost_translate_compare_func(in
->func
);
1140 cfg
.stencil_fail
= pan_pipe_to_stencil_op(in
->fail_op
);
1141 cfg
.depth_fail
= pan_pipe_to_stencil_op(in
->zfail_op
);
1142 cfg
.depth_pass
= pan_pipe_to_stencil_op(in
->zpass_op
);
1147 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
1148 const struct pipe_depth_stencil_alpha_state
*zsa
)
1150 struct panfrost_zsa_state
*so
= CALLOC_STRUCT(panfrost_zsa_state
);
1153 pan_pipe_to_stencil(&zsa
->stencil
[0], &so
->stencil_front
);
1154 pan_pipe_to_stencil(&zsa
->stencil
[1], &so
->stencil_back
);
1156 so
->stencil_mask_front
= zsa
->stencil
[0].writemask
;
1158 if (zsa
->stencil
[1].enabled
)
1159 so
->stencil_mask_back
= zsa
->stencil
[1].writemask
;
1161 so
->stencil_mask_back
= so
->stencil_mask_front
;
1163 /* Alpha lowered by frontend */
1164 assert(!zsa
->alpha
.enabled
);
1166 /* TODO: Bounds test should be easy */
1167 assert(!zsa
->depth
.bounds_test
);
1173 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
1176 struct panfrost_context
*ctx
= pan_context(pipe
);
1177 struct panfrost_zsa_state
*zsa
= cso
;
1178 ctx
->depth_stencil
= zsa
;
1182 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
1188 panfrost_set_sample_mask(struct pipe_context
*pipe
,
1189 unsigned sample_mask
)
1191 struct panfrost_context
*ctx
= pan_context(pipe
);
1192 ctx
->sample_mask
= sample_mask
;
1196 panfrost_set_min_samples(struct pipe_context
*pipe
,
1197 unsigned min_samples
)
1199 struct panfrost_context
*ctx
= pan_context(pipe
);
1200 ctx
->min_samples
= min_samples
;
1205 panfrost_set_clip_state(struct pipe_context
*pipe
,
1206 const struct pipe_clip_state
*clip
)
1208 //struct panfrost_context *panfrost = pan_context(pipe);
1212 panfrost_set_viewport_states(struct pipe_context
*pipe
,
1213 unsigned start_slot
,
1214 unsigned num_viewports
,
1215 const struct pipe_viewport_state
*viewports
)
1217 struct panfrost_context
*ctx
= pan_context(pipe
);
1219 assert(start_slot
== 0);
1220 assert(num_viewports
== 1);
1222 ctx
->pipe_viewport
= *viewports
;
1226 panfrost_set_scissor_states(struct pipe_context
*pipe
,
1227 unsigned start_slot
,
1228 unsigned num_scissors
,
1229 const struct pipe_scissor_state
*scissors
)
1231 struct panfrost_context
*ctx
= pan_context(pipe
);
1233 assert(start_slot
== 0);
1234 assert(num_scissors
== 1);
1236 ctx
->scissor
= *scissors
;
1240 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
1241 const struct pipe_poly_stipple
*stipple
)
1243 //struct panfrost_context *panfrost = pan_context(pipe);
1247 panfrost_set_active_query_state(struct pipe_context
*pipe
,
1250 struct panfrost_context
*ctx
= pan_context(pipe
);
1251 ctx
->active_queries
= enable
;
1255 panfrost_destroy(struct pipe_context
*pipe
)
1257 struct panfrost_context
*panfrost
= pan_context(pipe
);
1259 if (panfrost
->blitter
)
1260 util_blitter_destroy(panfrost
->blitter
);
1262 if (panfrost
->blitter_wallpaper
)
1263 util_blitter_destroy(panfrost
->blitter_wallpaper
);
1265 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
1266 u_upload_destroy(pipe
->stream_uploader
);
1271 static struct pipe_query
*
1272 panfrost_create_query(struct pipe_context
*pipe
,
1276 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
1281 return (struct pipe_query
*) q
;
1285 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1287 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1290 panfrost_bo_unreference(query
->bo
);
1298 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1300 struct panfrost_context
*ctx
= pan_context(pipe
);
1301 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1303 switch (query
->type
) {
1304 case PIPE_QUERY_OCCLUSION_COUNTER
:
1305 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1306 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1307 /* Allocate a bo for the query results to be stored */
1309 query
->bo
= panfrost_bo_create(
1310 pan_device(ctx
->base
.screen
),
1311 sizeof(unsigned), 0);
1314 unsigned *result
= (unsigned *)query
->bo
->cpu
;
1315 *result
= 0; /* Default to 0 if nothing at all drawn. */
1316 ctx
->occlusion_query
= query
;
1319 /* Geometry statistics are computed in the driver. XXX: geom/tess
1322 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1323 query
->start
= ctx
->prims_generated
;
1325 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1326 query
->start
= ctx
->tf_prims_generated
;
1330 /* TODO: timestamp queries, etc? */
1338 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1340 struct panfrost_context
*ctx
= pan_context(pipe
);
1341 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1343 switch (query
->type
) {
1344 case PIPE_QUERY_OCCLUSION_COUNTER
:
1345 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1346 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1347 ctx
->occlusion_query
= NULL
;
1349 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1350 query
->end
= ctx
->prims_generated
;
1352 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1353 query
->end
= ctx
->tf_prims_generated
;
1361 panfrost_get_query_result(struct pipe_context
*pipe
,
1362 struct pipe_query
*q
,
1364 union pipe_query_result
*vresult
)
1366 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1367 struct panfrost_context
*ctx
= pan_context(pipe
);
1370 switch (query
->type
) {
1371 case PIPE_QUERY_OCCLUSION_COUNTER
:
1372 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1373 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1374 panfrost_flush_batches_accessing_bo(ctx
, query
->bo
, false);
1375 panfrost_bo_wait(query
->bo
, INT64_MAX
, false);
1377 /* Read back the query results */
1378 unsigned *result
= (unsigned *) query
->bo
->cpu
;
1379 unsigned passed
= *result
;
1381 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1382 vresult
->u64
= passed
;
1384 vresult
->b
= !!passed
;
1389 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1390 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1391 panfrost_flush_all_batches(ctx
, 0);
1392 vresult
->u64
= query
->end
- query
->start
;
1396 /* TODO: more queries */
1403 static struct pipe_stream_output_target
*
1404 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
1405 struct pipe_resource
*prsc
,
1406 unsigned buffer_offset
,
1407 unsigned buffer_size
)
1409 struct pipe_stream_output_target
*target
;
1411 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
1416 pipe_reference_init(&target
->reference
, 1);
1417 pipe_resource_reference(&target
->buffer
, prsc
);
1419 target
->context
= pctx
;
1420 target
->buffer_offset
= buffer_offset
;
1421 target
->buffer_size
= buffer_size
;
1427 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
1428 struct pipe_stream_output_target
*target
)
1430 pipe_resource_reference(&target
->buffer
, NULL
);
1431 ralloc_free(target
);
1435 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
1436 unsigned num_targets
,
1437 struct pipe_stream_output_target
**targets
,
1438 const unsigned *offsets
)
1440 struct panfrost_context
*ctx
= pan_context(pctx
);
1441 struct panfrost_streamout
*so
= &ctx
->streamout
;
1443 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
1445 for (unsigned i
= 0; i
< num_targets
; i
++) {
1446 if (offsets
[i
] != -1)
1447 so
->offsets
[i
] = offsets
[i
];
1449 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
1452 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
1453 pipe_so_target_reference(&so
->targets
[i
], NULL
);
1455 so
->num_targets
= num_targets
;
1458 struct pipe_context
*
1459 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
1461 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
1462 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1463 struct panfrost_device
*dev
= pan_device(screen
);
1465 gallium
->screen
= screen
;
1467 gallium
->destroy
= panfrost_destroy
;
1469 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
1471 gallium
->flush
= panfrost_flush
;
1472 gallium
->clear
= panfrost_clear
;
1473 gallium
->draw_vbo
= panfrost_draw_vbo
;
1474 gallium
->texture_barrier
= panfrost_texture_barrier
;
1476 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
1477 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
1478 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
1480 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
1482 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
1483 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
1484 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
1486 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
1487 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
1488 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
1490 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
1491 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
1492 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
1494 gallium
->create_fs_state
= panfrost_create_fs_state
;
1495 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
1496 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
1498 gallium
->create_vs_state
= panfrost_create_vs_state
;
1499 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
1500 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
1502 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
1503 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
1504 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
1506 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
1507 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
1508 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
1510 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
1511 gallium
->set_min_samples
= panfrost_set_min_samples
;
1513 gallium
->set_clip_state
= panfrost_set_clip_state
;
1514 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
1515 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
1516 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
1517 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
1519 gallium
->create_query
= panfrost_create_query
;
1520 gallium
->destroy_query
= panfrost_destroy_query
;
1521 gallium
->begin_query
= panfrost_begin_query
;
1522 gallium
->end_query
= panfrost_end_query
;
1523 gallium
->get_query_result
= panfrost_get_query_result
;
1525 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
1526 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
1527 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
1529 panfrost_resource_context_init(gallium
);
1530 panfrost_blend_context_init(gallium
);
1531 panfrost_compute_context_init(gallium
);
1533 gallium
->stream_uploader
= u_upload_create_default(gallium
);
1534 gallium
->const_uploader
= gallium
->stream_uploader
;
1535 assert(gallium
->stream_uploader
);
1537 /* All of our GPUs support ES mode. Midgard supports additionally
1538 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1540 ctx
->draw_modes
= (1 << (PIPE_PRIM_QUADS
+ 1)) - 1;
1542 if (!(dev
->quirks
& IS_BIFROST
)) {
1543 ctx
->draw_modes
|= (1 << PIPE_PRIM_QUAD_STRIP
);
1544 ctx
->draw_modes
|= (1 << PIPE_PRIM_POLYGON
);
1547 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
1549 ctx
->blitter
= util_blitter_create(gallium
);
1550 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
1552 assert(ctx
->blitter
);
1553 assert(ctx
->blitter_wallpaper
);
1555 /* Prepare for render! */
1557 panfrost_batch_init(ctx
);
1558 panfrost_invalidate_frame(ctx
);
1560 if (!(dev
->quirks
& IS_BIFROST
)) {
1561 for (unsigned c
= 0; c
< PIPE_MAX_COLOR_BUFS
; ++c
)
1562 ctx
->blit_blend
.rt
[c
].shaders
= _mesa_hash_table_u64_create(ctx
);
1565 /* By default mask everything on */
1566 ctx
->sample_mask
= ~0;