2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
57 #include "util/pan_lower_framebuffer.h"
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
62 struct panfrost_device
*device
= pan_device(batch
->ctx
->base
.screen
);
63 bool hierarchy
= !(device
->quirks
& MIDGARD_NO_HIER_TILING
);
64 struct midgard_tiler_descriptor t
= {0};
65 unsigned height
= batch
->key
.height
;
66 unsigned width
= batch
->key
.width
;
69 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
71 /* Compute the polygon header size and use that to offset the body */
73 unsigned header_size
= panfrost_tiler_header_size(
74 width
, height
, t
.hierarchy_mask
, hierarchy
);
76 t
.polygon_list_size
= panfrost_tiler_full_size(
77 width
, height
, t
.hierarchy_mask
, hierarchy
);
80 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
85 t
.heap_start
= device
->tiler_heap
->gpu
;
86 t
.heap_end
= device
->tiler_heap
->gpu
+ device
->tiler_heap
->size
;
88 struct panfrost_bo
*tiler_dummy
;
90 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
91 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
93 /* The tiler is disabled, so don't allow the tiler heap */
94 t
.heap_start
= tiler_dummy
->gpu
;
95 t
.heap_end
= t
.heap_start
;
97 /* Use a dummy polygon list */
98 t
.polygon_list
= tiler_dummy
->gpu
;
100 /* Disable the tiler */
102 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
104 t
.hierarchy_mask
= MALI_TILER_USER
;
105 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
107 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
108 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
109 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
113 t
.polygon_list_body
=
114 t
.polygon_list
+ header_size
;
121 struct pipe_context
*pipe
,
123 const struct pipe_scissor_state
*scissor_state
,
124 const union pipe_color_union
*color
,
125 double depth
, unsigned stencil
)
127 struct panfrost_context
*ctx
= pan_context(pipe
);
129 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
130 * the existing batch targeting this FBO has draws. We could probably
131 * avoid that by replacing plain clears by quad-draws with a specific
132 * color/depth/stencil value, thus avoiding the generation of extra
135 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
136 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
140 panfrost_writes_point_size(struct panfrost_context
*ctx
)
142 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
143 struct panfrost_shader_state
*vs
= panfrost_get_shader_state(ctx
, PIPE_SHADER_VERTEX
);
145 return vs
->writes_point_size
&& ctx
->active_prim
== PIPE_PRIM_POINTS
;
148 /* The entire frame is in memory -- send it off to the kernel! */
152 struct pipe_context
*pipe
,
153 struct pipe_fence_handle
**fence
,
156 struct panfrost_context
*ctx
= pan_context(pipe
);
157 struct panfrost_device
*dev
= pan_device(pipe
->screen
);
158 uint32_t syncobj
= 0;
161 drmSyncobjCreate(dev
->fd
, 0, &syncobj
);
163 /* Submit all pending jobs */
164 panfrost_flush_all_batches(ctx
, syncobj
);
167 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, syncobj
);
168 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
169 *fence
= (struct pipe_fence_handle
*)f
;
172 if (dev
->debug
& PAN_DBG_TRACE
)
173 pandecode_next_frame();
177 panfrost_texture_barrier(struct pipe_context
*pipe
, unsigned flags
)
179 struct panfrost_context
*ctx
= pan_context(pipe
);
180 panfrost_flush_all_batches(ctx
, 0);
183 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
186 pan_draw_mode(enum pipe_prim_type mode
)
191 DEFINE_CASE(LINE_LOOP
);
192 DEFINE_CASE(LINE_STRIP
);
193 DEFINE_CASE(TRIANGLES
);
194 DEFINE_CASE(TRIANGLE_STRIP
);
195 DEFINE_CASE(TRIANGLE_FAN
);
197 DEFINE_CASE(QUAD_STRIP
);
198 DEFINE_CASE(POLYGON
);
201 unreachable("Invalid draw mode");
208 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
210 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
212 /* Check if we're scissoring at all */
214 if (!ctx
->rasterizer
->base
.scissor
)
217 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
220 /* Count generated primitives (when there is no geom/tess shaders) for
221 * transform feedback */
224 panfrost_statistics_record(
225 struct panfrost_context
*ctx
,
226 const struct pipe_draw_info
*info
)
228 if (!ctx
->active_queries
)
231 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
232 ctx
->prims_generated
+= prims
;
234 if (!ctx
->streamout
.num_targets
)
237 ctx
->tf_prims_generated
+= prims
;
241 panfrost_update_streamout_offsets(struct panfrost_context
*ctx
)
243 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
246 count
= u_stream_outputs_for_vertices(ctx
->active_prim
,
248 ctx
->streamout
.offsets
[i
] += count
;
253 pan_emit_draw_descs(struct panfrost_batch
*batch
,
254 struct MALI_DRAW
*d
, enum pipe_shader_type st
)
256 d
->offset_start
= batch
->ctx
->offset_start
;
257 d
->instances
= batch
->ctx
->instance_count
> 1 ?
258 batch
->ctx
->padded_count
: 1;
260 d
->uniform_buffers
= panfrost_emit_const_buf(batch
, st
, &d
->push_uniforms
);
261 d
->textures
= panfrost_emit_texture_descriptors(batch
, st
);
262 d
->samplers
= panfrost_emit_sampler_descriptors(batch
, st
);
265 static enum mali_index_type
266 panfrost_translate_index_size(unsigned size
)
269 case 1: return MALI_INDEX_TYPE_UINT8
;
270 case 2: return MALI_INDEX_TYPE_UINT16
;
271 case 4: return MALI_INDEX_TYPE_UINT32
;
272 default: unreachable("Invalid index size");
278 struct pipe_context
*pipe
,
279 const struct pipe_draw_info
*info
)
281 struct panfrost_context
*ctx
= pan_context(pipe
);
282 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
284 /* First of all, check the scissor to see if anything is drawn at all.
285 * If it's not, we drop the draw (mostly a conformance issue;
286 * well-behaved apps shouldn't hit this) */
288 if (panfrost_scissor_culls_everything(ctx
))
291 int mode
= info
->mode
;
293 /* Fallback unsupported restart index */
294 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
296 if (info
->primitive_restart
&& info
->index_size
297 && info
->restart_index
!= primitive_index
) {
298 util_draw_vbo_without_prim_restart(pipe
, info
);
302 /* Fallback for unsupported modes */
304 assert(ctx
->rasterizer
!= NULL
);
306 if (!(ctx
->draw_modes
& (1 << mode
))) {
307 if (info
->count
< 4) {
308 /* Degenerate case? */
312 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
313 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
317 /* Now that we have a guaranteed terminating path, find the job. */
319 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
320 panfrost_batch_set_requirements(batch
);
322 /* Take into account a negative bias */
323 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
324 ctx
->instance_count
= info
->instance_count
;
325 ctx
->active_prim
= info
->mode
;
327 struct mali_vertex_tiler_prefix vertex_prefix
= { 0 }, tiler_prefix
= { 0 };
328 struct mali_draw_packed vertex_postfix
, tiler_postfix
;
329 struct mali_primitive_packed primitive
;
330 union midgard_primitive_size primitive_size
;
331 unsigned vertex_count
= ctx
->vertex_count
;
333 mali_ptr shared_mem
= (device
->quirks
& IS_BIFROST
) ?
334 panfrost_vt_emit_shared_memory(batch
) :
335 panfrost_batch_reserve_framebuffer(batch
);
337 struct pipe_rasterizer_state
*rast
= &ctx
->rasterizer
->base
;
338 unsigned min_index
= 0, max_index
= 0;
340 pan_pack(&primitive
, PRIMITIVE
, cfg
) {
341 cfg
.draw_mode
= pan_draw_mode(mode
);
342 cfg
.point_size_array
= panfrost_writes_point_size(ctx
);
343 cfg
.first_provoking_vertex
= rast
->flatshade_first
;
344 cfg
.primitive_restart
= info
->primitive_restart
;
347 if (info
->index_size
) {
348 cfg
.index_type
= panfrost_translate_index_size(info
->index_size
);
349 cfg
.indices
= panfrost_get_index_buffer_bounded(ctx
, info
,
350 &min_index
, &max_index
);
352 /* Use the corresponding values */
353 vertex_count
= max_index
- min_index
+ 1;
354 ctx
->offset_start
= min_index
+ info
->index_bias
;
356 cfg
.base_vertex_offset
= -min_index
;
357 cfg
.index_count
= info
->count
;
359 ctx
->offset_start
= info
->start
;
360 cfg
.index_count
= ctx
->vertex_count
;
364 vertex_prefix
.primitive
.opaque
[0] = (5) << 26; /* XXX */
365 memcpy(&tiler_prefix
.primitive
, &primitive
, sizeof(primitive
));
367 /* Encode the padded vertex count */
369 if (info
->instance_count
> 1)
370 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
372 ctx
->padded_count
= vertex_count
;
374 panfrost_statistics_record(ctx
, info
);
376 panfrost_pack_work_groups_fused(&vertex_prefix
, &tiler_prefix
,
377 1, vertex_count
, info
->instance_count
,
380 /* Emit all sort of descriptors. */
381 mali_ptr varyings
= 0, vs_vary
= 0, fs_vary
= 0, pos
= 0, psiz
= 0;
383 panfrost_emit_varying_descriptor(batch
,
386 &vs_vary
, &fs_vary
, &varyings
,
389 pan_pack(&vertex_postfix
, DRAW
, cfg
) {
390 cfg
.unknown_1
= (device
->quirks
& IS_BIFROST
) ? 0x2 : 0x6;
391 cfg
.state
= panfrost_emit_compute_shader_meta(batch
, PIPE_SHADER_VERTEX
);
392 cfg
.attributes
= panfrost_emit_vertex_data(batch
, &cfg
.attribute_buffers
);
393 cfg
.varyings
= vs_vary
;
394 cfg
.varying_buffers
= varyings
;
395 cfg
.shared
= shared_mem
;
396 pan_emit_draw_descs(batch
, &cfg
, PIPE_SHADER_VERTEX
);
399 pan_pack(&tiler_postfix
, DRAW
, cfg
) {
400 cfg
.unknown_1
= (device
->quirks
& IS_BIFROST
) ? 0x3 : 0x7;
401 cfg
.front_face_ccw
= rast
->front_ccw
;
402 cfg
.cull_front_face
= rast
->cull_face
& PIPE_FACE_FRONT
;
403 cfg
.cull_back_face
= rast
->cull_face
& PIPE_FACE_BACK
;
405 cfg
.state
= panfrost_emit_frag_shader_meta(batch
);
406 cfg
.viewport
= panfrost_emit_viewport(batch
);
407 cfg
.varyings
= fs_vary
;
408 cfg
.varying_buffers
= varyings
;
409 cfg
.shared
= shared_mem
;
411 pan_emit_draw_descs(batch
, &cfg
, PIPE_SHADER_FRAGMENT
);
413 if (ctx
->occlusion_query
) {
414 cfg
.occlusion_query
= MALI_OCCLUSION_MODE_PREDICATE
;
415 cfg
.occlusion
= ctx
->occlusion_query
->bo
->gpu
;
416 panfrost_batch_add_bo(ctx
->batch
, ctx
->occlusion_query
->bo
,
417 PAN_BO_ACCESS_SHARED
|
419 PAN_BO_ACCESS_FRAGMENT
);
423 primitive_size
.pointer
= psiz
;
424 panfrost_vt_update_primitive_size(ctx
, info
->mode
== PIPE_PRIM_POINTS
, &primitive_size
);
426 /* Fire off the draw itself */
427 panfrost_emit_vertex_tiler_jobs(batch
, &vertex_prefix
, &vertex_postfix
,
428 &tiler_prefix
, &tiler_postfix
,
431 /* Adjust the batch stack size based on the new shader stack sizes. */
432 panfrost_batch_adjust_stack_size(batch
);
434 /* Increment transform feedback offsets */
435 panfrost_update_streamout_offsets(ctx
);
441 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
447 panfrost_create_rasterizer_state(
448 struct pipe_context
*pctx
,
449 const struct pipe_rasterizer_state
*cso
)
451 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
455 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
456 assert(cso
->offset_clamp
== 0.0);
462 panfrost_bind_rasterizer_state(
463 struct pipe_context
*pctx
,
466 struct panfrost_context
*ctx
= pan_context(pctx
);
467 ctx
->rasterizer
= hwcso
;
471 panfrost_create_vertex_elements_state(
472 struct pipe_context
*pctx
,
473 unsigned num_elements
,
474 const struct pipe_vertex_element
*elements
)
476 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
477 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
479 so
->num_elements
= num_elements
;
480 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
482 for (int i
= 0; i
< num_elements
; ++i
) {
483 enum pipe_format fmt
= elements
[i
].src_format
;
484 const struct util_format_description
*desc
= util_format_description(fmt
);
485 unsigned swizzle
= 0;
486 if (dev
->quirks
& HAS_SWIZZLES
)
487 swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
);
489 swizzle
= panfrost_bifrost_swizzle(desc
->nr_channels
);
491 enum mali_format hw_format
= panfrost_pipe_format_table
[desc
->format
].hw
;
492 so
->formats
[i
] = (hw_format
<< 12) | swizzle
;
496 /* Let's also prepare vertex builtins */
497 if (dev
->quirks
& HAS_SWIZZLES
)
498 so
->formats
[PAN_VERTEX_ID
] = (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
500 so
->formats
[PAN_VERTEX_ID
] = (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
502 if (dev
->quirks
& HAS_SWIZZLES
)
503 so
->formats
[PAN_INSTANCE_ID
] = (MALI_R32UI
<< 12) | panfrost_get_default_swizzle(1);
505 so
->formats
[PAN_INSTANCE_ID
] = (MALI_R32UI
<< 12) | panfrost_bifrost_swizzle(1);
511 panfrost_bind_vertex_elements_state(
512 struct pipe_context
*pctx
,
515 struct panfrost_context
*ctx
= pan_context(pctx
);
520 panfrost_create_shader_state(
521 struct pipe_context
*pctx
,
522 const struct pipe_shader_state
*cso
,
523 enum pipe_shader_type stage
)
525 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
526 struct panfrost_device
*dev
= pan_device(pctx
->screen
);
529 /* Token deep copy to prevent memory corruption */
531 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
532 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
534 /* Precompile for shader-db if we need to */
535 if (unlikely((dev
->debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
536 struct panfrost_context
*ctx
= pan_context(pctx
);
538 struct panfrost_shader_state state
= { 0 };
539 uint64_t outputs_written
;
541 panfrost_shader_compile(ctx
, PIPE_SHADER_IR_NIR
,
543 tgsi_processor_to_shader_stage(stage
),
544 &state
, &outputs_written
);
551 panfrost_delete_shader_state(
552 struct pipe_context
*pctx
,
555 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
557 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
558 /* TODO: leaks TGSI tokens! */
561 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
562 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
563 panfrost_bo_unreference(shader_state
->bo
);
565 if (shader_state
->upload
.rsrc
)
566 pipe_resource_reference(&shader_state
->upload
.rsrc
, NULL
);
568 shader_state
->bo
= NULL
;
577 panfrost_create_sampler_state(
578 struct pipe_context
*pctx
,
579 const struct pipe_sampler_state
*cso
)
581 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
582 struct panfrost_device
*device
= pan_device(pctx
->screen
);
586 if (device
->quirks
& IS_BIFROST
)
587 panfrost_sampler_desc_init_bifrost(cso
, (struct mali_bifrost_sampler_packed
*) &so
->hw
);
589 panfrost_sampler_desc_init(cso
, &so
->hw
);
595 panfrost_bind_sampler_states(
596 struct pipe_context
*pctx
,
597 enum pipe_shader_type shader
,
598 unsigned start_slot
, unsigned num_sampler
,
601 assert(start_slot
== 0);
603 struct panfrost_context
*ctx
= pan_context(pctx
);
605 /* XXX: Should upload, not just copy? */
606 ctx
->sampler_count
[shader
] = num_sampler
;
607 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
611 panfrost_variant_matches(
612 struct panfrost_context
*ctx
,
613 struct panfrost_shader_state
*variant
,
614 enum pipe_shader_type type
)
616 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
618 if (variant
->outputs_read
) {
619 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
622 BITSET_FOREACH_SET(i
, &variant
->outputs_read
, 8) {
623 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
625 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
626 fmt
= fb
->cbufs
[i
]->format
;
628 const struct util_format_description
*desc
=
629 util_format_description(fmt
);
631 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
632 fmt
= PIPE_FORMAT_NONE
;
634 if (variant
->rt_formats
[i
] != fmt
)
639 /* Otherwise, we're good to go */
644 * Fix an uncompiled shader's stream output info, and produce a bitmask
645 * of which VARYING_SLOT_* are captured for stream output.
647 * Core Gallium stores output->register_index as a "slot" number, where
648 * slots are assigned consecutively to all outputs in info->outputs_written.
649 * This naive packing of outputs doesn't work for us - we too have slots,
650 * but the layout is defined by the VUE map, which we won't have until we
651 * compile a specific shader variant. So, we remap these and simply store
652 * VARYING_SLOT_* in our copy's output->register_index fields.
654 * We then produce a bitmask of outputs which are used for SO.
656 * Implementation from iris.
660 update_so_info(struct pipe_stream_output_info
*so_info
,
661 uint64_t outputs_written
)
663 uint64_t so_outputs
= 0;
664 uint8_t reverse_map
[64] = {0};
667 while (outputs_written
)
668 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
670 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
671 struct pipe_stream_output
*output
= &so_info
->output
[i
];
673 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
674 output
->register_index
= reverse_map
[output
->register_index
];
676 so_outputs
|= 1ull << output
->register_index
;
683 panfrost_bind_shader_state(
684 struct pipe_context
*pctx
,
686 enum pipe_shader_type type
)
688 struct panfrost_context
*ctx
= pan_context(pctx
);
689 struct panfrost_device
*dev
= pan_device(ctx
->base
.screen
);
690 ctx
->shader
[type
] = hwcso
;
694 /* Match the appropriate variant */
697 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
699 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
700 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
707 /* No variant matched, so create a new one */
708 variant
= variants
->variant_count
++;
710 if (variants
->variant_count
> variants
->variant_space
) {
711 unsigned old_space
= variants
->variant_space
;
713 variants
->variant_space
*= 2;
714 if (variants
->variant_space
== 0)
715 variants
->variant_space
= 1;
717 /* Arbitrary limit to stop runaway programs from
718 * creating an unbounded number of shader variants. */
719 assert(variants
->variant_space
< 1024);
721 unsigned msize
= sizeof(struct panfrost_shader_state
);
722 variants
->variants
= realloc(variants
->variants
,
723 variants
->variant_space
* msize
);
725 memset(&variants
->variants
[old_space
], 0,
726 (variants
->variant_space
- old_space
) * msize
);
729 struct panfrost_shader_state
*v
=
730 &variants
->variants
[variant
];
732 if (type
== PIPE_SHADER_FRAGMENT
) {
733 struct pipe_framebuffer_state
*fb
= &ctx
->pipe_framebuffer
;
734 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
735 enum pipe_format fmt
= PIPE_FORMAT_R8G8B8A8_UNORM
;
737 if ((fb
->nr_cbufs
> i
) && fb
->cbufs
[i
])
738 fmt
= fb
->cbufs
[i
]->format
;
740 const struct util_format_description
*desc
=
741 util_format_description(fmt
);
743 if (pan_format_class_load(desc
, dev
->quirks
) == PAN_FORMAT_NATIVE
)
744 fmt
= PIPE_FORMAT_NONE
;
746 v
->rt_formats
[i
] = fmt
;
751 /* Select this variant */
752 variants
->active_variant
= variant
;
754 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
755 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
757 /* We finally have a variant, so compile it */
759 if (!shader_state
->compiled
) {
760 uint64_t outputs_written
= 0;
762 panfrost_shader_compile(ctx
, variants
->base
.type
,
763 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
764 variants
->base
.ir
.nir
:
765 variants
->base
.tokens
,
766 tgsi_processor_to_shader_stage(type
),
770 shader_state
->compiled
= true;
772 /* Fixup the stream out information, since what Gallium returns
773 * normally is mildly insane */
775 shader_state
->stream_output
= variants
->base
.stream_output
;
776 shader_state
->so_mask
=
777 update_so_info(&shader_state
->stream_output
, outputs_written
);
782 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
784 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
788 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
790 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
794 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
796 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
800 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
802 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
806 panfrost_set_vertex_buffers(
807 struct pipe_context
*pctx
,
809 unsigned num_buffers
,
810 const struct pipe_vertex_buffer
*buffers
)
812 struct panfrost_context
*ctx
= pan_context(pctx
);
814 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
818 panfrost_set_constant_buffer(
819 struct pipe_context
*pctx
,
820 enum pipe_shader_type shader
, uint index
,
821 const struct pipe_constant_buffer
*buf
)
823 struct panfrost_context
*ctx
= pan_context(pctx
);
824 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
826 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
828 unsigned mask
= (1 << index
);
830 if (unlikely(!buf
)) {
831 pbuf
->enabled_mask
&= ~mask
;
832 pbuf
->dirty_mask
&= ~mask
;
836 pbuf
->enabled_mask
|= mask
;
837 pbuf
->dirty_mask
|= mask
;
841 panfrost_set_stencil_ref(
842 struct pipe_context
*pctx
,
843 const struct pipe_stencil_ref
*ref
)
845 struct panfrost_context
*ctx
= pan_context(pctx
);
846 ctx
->stencil_ref
= *ref
;
850 panfrost_create_sampler_view_bo(struct panfrost_sampler_view
*so
,
851 struct pipe_context
*pctx
,
852 struct pipe_resource
*texture
)
854 struct panfrost_device
*device
= pan_device(pctx
->screen
);
855 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*)texture
;
856 enum pipe_format format
= so
->base
.format
;
859 /* Format to access the stencil portion of a Z32_S8 texture */
860 if (format
== PIPE_FORMAT_X32_S8X24_UINT
) {
861 assert(prsrc
->separate_stencil
);
862 texture
= &prsrc
->separate_stencil
->base
;
863 prsrc
= (struct panfrost_resource
*)texture
;
864 format
= texture
->format
;
867 const struct util_format_description
*desc
= util_format_description(format
);
869 bool fake_rgtc
= !panfrost_supports_compressed_format(device
, MALI_BC4_UNORM
);
871 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
&& fake_rgtc
) {
873 format
= PIPE_FORMAT_R8G8B8A8_SNORM
;
875 format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
876 desc
= util_format_description(format
);
879 so
->texture_bo
= prsrc
->bo
->gpu
;
880 so
->modifier
= prsrc
->modifier
;
882 unsigned char user_swizzle
[4] = {
889 /* In the hardware, array_size refers specifically to array textures,
890 * whereas in Gallium, it also covers cubemaps */
892 unsigned array_size
= texture
->array_size
;
893 unsigned depth
= texture
->depth0
;
895 if (so
->base
.target
== PIPE_TEXTURE_CUBE
) {
896 /* TODO: Cubemap arrays */
897 assert(array_size
== 6);
901 /* MSAA only supported for 2D textures (and 2D texture arrays via an
902 * extension currently unimplemented */
904 if (so
->base
.target
== PIPE_TEXTURE_2D
) {
906 depth
= texture
->nr_samples
;
908 /* MSAA only supported for 2D textures */
909 assert(texture
->nr_samples
<= 1);
912 enum mali_texture_dimension type
=
913 panfrost_translate_texture_dimension(so
->base
.target
);
915 if (device
->quirks
& IS_BIFROST
) {
916 unsigned char composed_swizzle
[4];
917 util_format_compose_swizzles(desc
->swizzle
, user_swizzle
, composed_swizzle
);
919 unsigned size
= panfrost_estimate_texture_payload_size(
920 so
->base
.u
.tex
.first_level
,
921 so
->base
.u
.tex
.last_level
,
922 so
->base
.u
.tex
.first_layer
,
923 so
->base
.u
.tex
.last_layer
,
925 type
, prsrc
->modifier
);
927 so
->bo
= panfrost_bo_create(device
, size
, 0);
929 panfrost_new_texture_bifrost(
930 &so
->bifrost_descriptor
,
931 texture
->width0
, texture
->height0
,
934 type
, prsrc
->modifier
,
935 so
->base
.u
.tex
.first_level
,
936 so
->base
.u
.tex
.last_level
,
937 so
->base
.u
.tex
.first_layer
,
938 so
->base
.u
.tex
.last_layer
,
940 prsrc
->cubemap_stride
,
941 panfrost_translate_swizzle_4(composed_swizzle
),
946 unsigned size
= panfrost_estimate_texture_payload_size(
947 so
->base
.u
.tex
.first_level
,
948 so
->base
.u
.tex
.last_level
,
949 so
->base
.u
.tex
.first_layer
,
950 so
->base
.u
.tex
.last_layer
,
952 type
, prsrc
->modifier
);
953 size
+= MALI_MIDGARD_TEXTURE_LENGTH
;
955 so
->bo
= panfrost_bo_create(device
, size
, 0);
957 panfrost_new_texture(
959 texture
->width0
, texture
->height0
,
962 type
, prsrc
->modifier
,
963 so
->base
.u
.tex
.first_level
,
964 so
->base
.u
.tex
.last_level
,
965 so
->base
.u
.tex
.first_layer
,
966 so
->base
.u
.tex
.last_layer
,
968 prsrc
->cubemap_stride
,
969 panfrost_translate_swizzle_4(user_swizzle
),
975 static struct pipe_sampler_view
*
976 panfrost_create_sampler_view(
977 struct pipe_context
*pctx
,
978 struct pipe_resource
*texture
,
979 const struct pipe_sampler_view
*template)
981 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
983 pipe_reference(NULL
, &texture
->reference
);
985 so
->base
= *template;
986 so
->base
.texture
= texture
;
987 so
->base
.reference
.count
= 1;
988 so
->base
.context
= pctx
;
990 panfrost_create_sampler_view_bo(so
, pctx
, texture
);
992 return (struct pipe_sampler_view
*) so
;
996 panfrost_set_sampler_views(
997 struct pipe_context
*pctx
,
998 enum pipe_shader_type shader
,
999 unsigned start_slot
, unsigned num_views
,
1000 struct pipe_sampler_view
**views
)
1002 struct panfrost_context
*ctx
= pan_context(pctx
);
1003 unsigned new_nr
= 0;
1006 assert(start_slot
== 0);
1008 for (i
= 0; i
< num_views
; ++i
) {
1011 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1015 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
1016 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
1019 ctx
->sampler_view_count
[shader
] = new_nr
;
1023 panfrost_sampler_view_destroy(
1024 struct pipe_context
*pctx
,
1025 struct pipe_sampler_view
*pview
)
1027 struct panfrost_sampler_view
*view
= (struct panfrost_sampler_view
*) pview
;
1029 pipe_resource_reference(&pview
->texture
, NULL
);
1030 panfrost_bo_unreference(view
->bo
);
1035 panfrost_set_shader_buffers(
1036 struct pipe_context
*pctx
,
1037 enum pipe_shader_type shader
,
1038 unsigned start
, unsigned count
,
1039 const struct pipe_shader_buffer
*buffers
,
1040 unsigned writable_bitmask
)
1042 struct panfrost_context
*ctx
= pan_context(pctx
);
1044 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
1045 buffers
, start
, count
);
1049 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1050 const struct pipe_framebuffer_state
*fb
)
1052 struct panfrost_context
*ctx
= pan_context(pctx
);
1054 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
1057 /* We may need to generate a new variant if the fragment shader is
1058 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1059 struct panfrost_shader_variants
*fs
= ctx
->shader
[PIPE_SHADER_FRAGMENT
];
1061 if (fs
&& fs
->variant_count
&& fs
->variants
[fs
->active_variant
].outputs_read
)
1062 ctx
->base
.bind_fs_state(&ctx
->base
, fs
);
1065 static inline unsigned
1066 pan_pipe_to_stencil_op(enum pipe_stencil_op in
)
1069 case PIPE_STENCIL_OP_KEEP
: return MALI_STENCIL_OP_KEEP
;
1070 case PIPE_STENCIL_OP_ZERO
: return MALI_STENCIL_OP_ZERO
;
1071 case PIPE_STENCIL_OP_REPLACE
: return MALI_STENCIL_OP_REPLACE
;
1072 case PIPE_STENCIL_OP_INCR
: return MALI_STENCIL_OP_INCR_SAT
;
1073 case PIPE_STENCIL_OP_DECR
: return MALI_STENCIL_OP_DECR_SAT
;
1074 case PIPE_STENCIL_OP_INCR_WRAP
: return MALI_STENCIL_OP_INCR_WRAP
;
1075 case PIPE_STENCIL_OP_DECR_WRAP
: return MALI_STENCIL_OP_DECR_WRAP
;
1076 case PIPE_STENCIL_OP_INVERT
: return MALI_STENCIL_OP_INVERT
;
1077 default: unreachable("Invalid stencil op");
1082 pan_pipe_to_stencil(const struct pipe_stencil_state
*in
, void *out
)
1084 pan_pack(out
, STENCIL
, cfg
) {
1085 cfg
.mask
= in
->valuemask
;
1086 cfg
.compare_function
= panfrost_translate_compare_func(in
->func
);
1087 cfg
.stencil_fail
= pan_pipe_to_stencil_op(in
->fail_op
);
1088 cfg
.depth_fail
= pan_pipe_to_stencil_op(in
->zfail_op
);
1089 cfg
.depth_pass
= pan_pipe_to_stencil_op(in
->zpass_op
);
1094 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
1095 const struct pipe_depth_stencil_alpha_state
*zsa
)
1097 struct panfrost_zsa_state
*so
= CALLOC_STRUCT(panfrost_zsa_state
);
1100 pan_pipe_to_stencil(&zsa
->stencil
[0], &so
->stencil_front
);
1101 so
->stencil_mask_front
= zsa
->stencil
[0].writemask
;
1103 if (zsa
->stencil
[1].enabled
) {
1104 pan_pipe_to_stencil(&zsa
->stencil
[1], &so
->stencil_back
);
1105 so
->stencil_mask_back
= zsa
->stencil
[1].writemask
;
1107 so
->stencil_back
= so
->stencil_front
;
1108 so
->stencil_mask_back
= so
->stencil_mask_front
;
1111 /* Alpha lowered by frontend */
1112 assert(!zsa
->alpha
.enabled
);
1114 /* TODO: Bounds test should be easy */
1115 assert(!zsa
->depth
.bounds_test
);
1121 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
1124 struct panfrost_context
*ctx
= pan_context(pipe
);
1125 ctx
->depth_stencil
= cso
;
1129 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
1135 panfrost_set_sample_mask(struct pipe_context
*pipe
,
1136 unsigned sample_mask
)
1138 struct panfrost_context
*ctx
= pan_context(pipe
);
1139 ctx
->sample_mask
= sample_mask
;
1143 panfrost_set_min_samples(struct pipe_context
*pipe
,
1144 unsigned min_samples
)
1146 struct panfrost_context
*ctx
= pan_context(pipe
);
1147 ctx
->min_samples
= min_samples
;
1152 panfrost_set_clip_state(struct pipe_context
*pipe
,
1153 const struct pipe_clip_state
*clip
)
1155 //struct panfrost_context *panfrost = pan_context(pipe);
1159 panfrost_set_viewport_states(struct pipe_context
*pipe
,
1160 unsigned start_slot
,
1161 unsigned num_viewports
,
1162 const struct pipe_viewport_state
*viewports
)
1164 struct panfrost_context
*ctx
= pan_context(pipe
);
1166 assert(start_slot
== 0);
1167 assert(num_viewports
== 1);
1169 ctx
->pipe_viewport
= *viewports
;
1173 panfrost_set_scissor_states(struct pipe_context
*pipe
,
1174 unsigned start_slot
,
1175 unsigned num_scissors
,
1176 const struct pipe_scissor_state
*scissors
)
1178 struct panfrost_context
*ctx
= pan_context(pipe
);
1180 assert(start_slot
== 0);
1181 assert(num_scissors
== 1);
1183 ctx
->scissor
= *scissors
;
1187 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
1188 const struct pipe_poly_stipple
*stipple
)
1190 //struct panfrost_context *panfrost = pan_context(pipe);
1194 panfrost_set_active_query_state(struct pipe_context
*pipe
,
1197 struct panfrost_context
*ctx
= pan_context(pipe
);
1198 ctx
->active_queries
= enable
;
1202 panfrost_destroy(struct pipe_context
*pipe
)
1204 struct panfrost_context
*panfrost
= pan_context(pipe
);
1206 if (panfrost
->blitter
)
1207 util_blitter_destroy(panfrost
->blitter
);
1209 if (panfrost
->blitter_wallpaper
)
1210 util_blitter_destroy(panfrost
->blitter_wallpaper
);
1212 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
1213 u_upload_destroy(pipe
->stream_uploader
);
1214 u_upload_destroy(panfrost
->state_uploader
);
1219 static struct pipe_query
*
1220 panfrost_create_query(struct pipe_context
*pipe
,
1224 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
1229 return (struct pipe_query
*) q
;
1233 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1235 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1238 panfrost_bo_unreference(query
->bo
);
1246 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1248 struct panfrost_context
*ctx
= pan_context(pipe
);
1249 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1251 switch (query
->type
) {
1252 case PIPE_QUERY_OCCLUSION_COUNTER
:
1253 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1254 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1255 /* Allocate a bo for the query results to be stored */
1257 query
->bo
= panfrost_bo_create(
1258 pan_device(ctx
->base
.screen
),
1259 sizeof(unsigned), 0);
1262 unsigned *result
= (unsigned *)query
->bo
->cpu
;
1263 *result
= 0; /* Default to 0 if nothing at all drawn. */
1264 ctx
->occlusion_query
= query
;
1267 /* Geometry statistics are computed in the driver. XXX: geom/tess
1270 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1271 query
->start
= ctx
->prims_generated
;
1273 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1274 query
->start
= ctx
->tf_prims_generated
;
1278 /* TODO: timestamp queries, etc? */
1286 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
1288 struct panfrost_context
*ctx
= pan_context(pipe
);
1289 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1291 switch (query
->type
) {
1292 case PIPE_QUERY_OCCLUSION_COUNTER
:
1293 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1294 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1295 ctx
->occlusion_query
= NULL
;
1297 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1298 query
->end
= ctx
->prims_generated
;
1300 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1301 query
->end
= ctx
->tf_prims_generated
;
1309 panfrost_get_query_result(struct pipe_context
*pipe
,
1310 struct pipe_query
*q
,
1312 union pipe_query_result
*vresult
)
1314 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
1315 struct panfrost_context
*ctx
= pan_context(pipe
);
1318 switch (query
->type
) {
1319 case PIPE_QUERY_OCCLUSION_COUNTER
:
1320 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1321 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
1322 panfrost_flush_batches_accessing_bo(ctx
, query
->bo
, false);
1323 panfrost_bo_wait(query
->bo
, INT64_MAX
, false);
1325 /* Read back the query results */
1326 unsigned *result
= (unsigned *) query
->bo
->cpu
;
1327 unsigned passed
= *result
;
1329 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
1330 vresult
->u64
= passed
;
1332 vresult
->b
= !!passed
;
1337 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1338 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1339 panfrost_flush_all_batches(ctx
, 0);
1340 vresult
->u64
= query
->end
- query
->start
;
1344 /* TODO: more queries */
1351 static struct pipe_stream_output_target
*
1352 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
1353 struct pipe_resource
*prsc
,
1354 unsigned buffer_offset
,
1355 unsigned buffer_size
)
1357 struct pipe_stream_output_target
*target
;
1359 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
1364 pipe_reference_init(&target
->reference
, 1);
1365 pipe_resource_reference(&target
->buffer
, prsc
);
1367 target
->context
= pctx
;
1368 target
->buffer_offset
= buffer_offset
;
1369 target
->buffer_size
= buffer_size
;
1375 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
1376 struct pipe_stream_output_target
*target
)
1378 pipe_resource_reference(&target
->buffer
, NULL
);
1379 ralloc_free(target
);
1383 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
1384 unsigned num_targets
,
1385 struct pipe_stream_output_target
**targets
,
1386 const unsigned *offsets
)
1388 struct panfrost_context
*ctx
= pan_context(pctx
);
1389 struct panfrost_streamout
*so
= &ctx
->streamout
;
1391 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
1393 for (unsigned i
= 0; i
< num_targets
; i
++) {
1394 if (offsets
[i
] != -1)
1395 so
->offsets
[i
] = offsets
[i
];
1397 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
1400 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
1401 pipe_so_target_reference(&so
->targets
[i
], NULL
);
1403 so
->num_targets
= num_targets
;
1406 struct pipe_context
*
1407 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
1409 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
1410 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1411 struct panfrost_device
*dev
= pan_device(screen
);
1413 gallium
->screen
= screen
;
1415 gallium
->destroy
= panfrost_destroy
;
1417 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
1419 gallium
->flush
= panfrost_flush
;
1420 gallium
->clear
= panfrost_clear
;
1421 gallium
->draw_vbo
= panfrost_draw_vbo
;
1422 gallium
->texture_barrier
= panfrost_texture_barrier
;
1424 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
1425 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
1426 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
1428 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
1430 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
1431 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
1432 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
1434 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
1435 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
1436 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
1438 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
1439 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
1440 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
1442 gallium
->create_fs_state
= panfrost_create_fs_state
;
1443 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
1444 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
1446 gallium
->create_vs_state
= panfrost_create_vs_state
;
1447 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
1448 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
1450 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
1451 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
1452 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
1454 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
1455 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
1456 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
1458 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
1459 gallium
->set_min_samples
= panfrost_set_min_samples
;
1461 gallium
->set_clip_state
= panfrost_set_clip_state
;
1462 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
1463 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
1464 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
1465 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
1467 gallium
->create_query
= panfrost_create_query
;
1468 gallium
->destroy_query
= panfrost_destroy_query
;
1469 gallium
->begin_query
= panfrost_begin_query
;
1470 gallium
->end_query
= panfrost_end_query
;
1471 gallium
->get_query_result
= panfrost_get_query_result
;
1473 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
1474 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
1475 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
1477 panfrost_resource_context_init(gallium
);
1478 panfrost_blend_context_init(gallium
);
1479 panfrost_compute_context_init(gallium
);
1481 gallium
->stream_uploader
= u_upload_create_default(gallium
);
1482 gallium
->const_uploader
= gallium
->stream_uploader
;
1484 ctx
->state_uploader
= u_upload_create(gallium
, 4096,
1485 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_DYNAMIC
, 0);
1487 /* All of our GPUs support ES mode. Midgard supports additionally
1488 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1490 ctx
->draw_modes
= (1 << (PIPE_PRIM_QUADS
+ 1)) - 1;
1492 if (!(dev
->quirks
& IS_BIFROST
)) {
1493 ctx
->draw_modes
|= (1 << PIPE_PRIM_QUAD_STRIP
);
1494 ctx
->draw_modes
|= (1 << PIPE_PRIM_POLYGON
);
1497 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
1499 ctx
->blitter
= util_blitter_create(gallium
);
1500 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
1502 assert(ctx
->blitter
);
1503 assert(ctx
->blitter_wallpaper
);
1505 /* Prepare for render! */
1507 panfrost_batch_init(ctx
);
1509 if (!(dev
->quirks
& IS_BIFROST
)) {
1510 for (unsigned c
= 0; c
< PIPE_MAX_COLOR_BUFS
; ++c
)
1511 ctx
->blit_blend
.rt
[c
].shaders
= _mesa_hash_table_u64_create(ctx
);
1514 /* By default mask everything on */
1515 ctx
->sample_mask
= ~0;
1516 ctx
->active_queries
= true;