2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_format.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
55 #include "pandecode/decode.h"
57 struct midgard_tiler_descriptor
58 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
60 struct panfrost_screen
*screen
= pan_screen(batch
->ctx
->base
.screen
);
61 bool hierarchy
= !(screen
->quirks
& MIDGARD_NO_HIER_TILING
);
62 struct midgard_tiler_descriptor t
= {0};
63 unsigned height
= batch
->key
.height
;
64 unsigned width
= batch
->key
.width
;
67 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
69 /* Compute the polygon header size and use that to offset the body */
71 unsigned header_size
= panfrost_tiler_header_size(
72 width
, height
, t
.hierarchy_mask
, hierarchy
);
74 t
.polygon_list_size
= panfrost_tiler_full_size(
75 width
, height
, t
.hierarchy_mask
, hierarchy
);
80 struct panfrost_bo
*tiler_heap
;
82 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
83 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
88 /* Allow the entire tiler heap */
89 t
.heap_start
= tiler_heap
->gpu
;
90 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
92 struct panfrost_bo
*tiler_dummy
;
94 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
95 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
97 /* The tiler is disabled, so don't allow the tiler heap */
98 t
.heap_start
= tiler_dummy
->gpu
;
99 t
.heap_end
= t
.heap_start
;
101 /* Use a dummy polygon list */
102 t
.polygon_list
= tiler_dummy
->gpu
;
104 /* Disable the tiler */
106 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
108 t
.hierarchy_mask
= MALI_TILER_USER
;
109 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
111 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
112 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
113 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
117 t
.polygon_list_body
=
118 t
.polygon_list
+ header_size
;
125 struct pipe_context
*pipe
,
127 const union pipe_color_union
*color
,
128 double depth
, unsigned stencil
)
130 struct panfrost_context
*ctx
= pan_context(pipe
);
132 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
133 * the existing batch targeting this FBO has draws. We could probably
134 * avoid that by replacing plain clears by quad-draws with a specific
135 * color/depth/stencil value, thus avoiding the generation of extra
138 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
140 panfrost_batch_add_fbo_bos(batch
);
141 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
145 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
147 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
148 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
150 /* If we haven't, reserve space for the framebuffer */
152 if (!batch
->framebuffer
.gpu
) {
153 unsigned size
= (screen
->quirks
& MIDGARD_SFBD
) ?
154 sizeof(struct mali_single_framebuffer
) :
155 sizeof(struct bifrost_framebuffer
);
157 batch
->framebuffer
= panfrost_allocate_transient(batch
, size
);
159 /* Tag the pointer */
160 if (!(screen
->quirks
& MIDGARD_SFBD
))
161 batch
->framebuffer
.gpu
|= MALI_MFBD
;
164 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
165 ctx
->payloads
[i
].postfix
.framebuffer
= batch
->framebuffer
.gpu
;
168 /* Reset per-frame context, called on context initialisation as well as after
169 * flushing a frame */
172 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
174 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
175 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
178 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
181 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
183 /* TODO: When does this need to be handled? */
184 ctx
->active_queries
= true;
187 /* In practice, every field of these payloads should be configurable
188 * arbitrarily, which means these functions are basically catch-all's for
189 * as-of-yet unwavering unknowns */
192 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
194 /* 0x2 bit clear on 32-bit T6XX */
196 struct midgard_payload_vertex_tiler payload
= {
197 .gl_enables
= 0x4 | 0x2,
200 /* Vertex and compute are closely coupled, so share a payload */
202 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
203 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
207 translate_tex_wrap(enum pipe_tex_wrap w
)
210 case PIPE_TEX_WRAP_REPEAT
:
211 return MALI_WRAP_REPEAT
;
213 case PIPE_TEX_WRAP_CLAMP
:
214 return MALI_WRAP_CLAMP
;
216 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
217 return MALI_WRAP_CLAMP_TO_EDGE
;
219 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
220 return MALI_WRAP_CLAMP_TO_BORDER
;
222 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
223 return MALI_WRAP_MIRRORED_REPEAT
;
225 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
226 return MALI_WRAP_MIRRORED_CLAMP
;
228 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
229 return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE
;
231 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
232 return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER
;
235 unreachable("Invalid wrap");
240 panfrost_translate_compare_func(enum pipe_compare_func in
)
243 case PIPE_FUNC_NEVER
:
244 return MALI_FUNC_NEVER
;
247 return MALI_FUNC_LESS
;
249 case PIPE_FUNC_EQUAL
:
250 return MALI_FUNC_EQUAL
;
252 case PIPE_FUNC_LEQUAL
:
253 return MALI_FUNC_LEQUAL
;
255 case PIPE_FUNC_GREATER
:
256 return MALI_FUNC_GREATER
;
258 case PIPE_FUNC_NOTEQUAL
:
259 return MALI_FUNC_NOTEQUAL
;
261 case PIPE_FUNC_GEQUAL
:
262 return MALI_FUNC_GEQUAL
;
264 case PIPE_FUNC_ALWAYS
:
265 return MALI_FUNC_ALWAYS
;
268 unreachable("Invalid func");
273 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
276 case PIPE_STENCIL_OP_KEEP
:
277 return MALI_STENCIL_KEEP
;
279 case PIPE_STENCIL_OP_ZERO
:
280 return MALI_STENCIL_ZERO
;
282 case PIPE_STENCIL_OP_REPLACE
:
283 return MALI_STENCIL_REPLACE
;
285 case PIPE_STENCIL_OP_INCR
:
286 return MALI_STENCIL_INCR
;
288 case PIPE_STENCIL_OP_DECR
:
289 return MALI_STENCIL_DECR
;
291 case PIPE_STENCIL_OP_INCR_WRAP
:
292 return MALI_STENCIL_INCR_WRAP
;
294 case PIPE_STENCIL_OP_DECR_WRAP
:
295 return MALI_STENCIL_DECR_WRAP
;
297 case PIPE_STENCIL_OP_INVERT
:
298 return MALI_STENCIL_INVERT
;
301 unreachable("Invalid stencil op");
306 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
308 out
->ref
= 0; /* Gallium gets it from elsewhere */
310 out
->mask
= in
->valuemask
;
311 out
->func
= panfrost_translate_compare_func(in
->func
);
312 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
313 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
314 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
318 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
320 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
321 struct mali_shader_meta shader
= {
322 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
324 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
325 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
328 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this is
329 * required (independent of 32-bit/64-bit descriptors), or why it's not
330 * used on later GPU revisions. Otherwise, all shader jobs fault on
331 * these earlier chips (perhaps this is a chicken bit of some kind).
332 * More investigation is needed. */
334 if (screen
->quirks
& MIDGARD_SFBD
)
335 shader
.unknown2_4
|= 0x10;
337 struct pipe_stencil_state default_stencil
= {
339 .func
= PIPE_FUNC_ALWAYS
,
340 .fail_op
= MALI_STENCIL_KEEP
,
341 .zfail_op
= MALI_STENCIL_KEEP
,
342 .zpass_op
= MALI_STENCIL_KEEP
,
347 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
348 shader
.stencil_mask_front
= default_stencil
.writemask
;
350 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
351 shader
.stencil_mask_back
= default_stencil
.writemask
;
353 if (default_stencil
.enabled
)
354 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
356 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
359 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
360 * graphics command stream. It should be called once per draw, accordding to
361 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
362 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
365 struct panfrost_transfer
366 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
368 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
369 struct mali_job_descriptor_header job
= {
370 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
371 .job_descriptor_size
= 1,
374 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
376 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sizeof(job
) + sizeof(*payload
));
377 memcpy(transfer
.cpu
, &job
, sizeof(job
));
378 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
383 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
385 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
386 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
388 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
392 panfrost_writes_point_size(struct panfrost_context
*ctx
)
394 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
395 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
397 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
400 /* Stage the attribute descriptors so we can adjust src_offset
401 * to let BOs align nicely */
404 panfrost_stage_attributes(struct panfrost_context
*ctx
)
406 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
407 struct panfrost_vertex_state
*so
= ctx
->vertex
;
409 size_t sz
= sizeof(struct mali_attr_meta
) * PAN_MAX_ATTRIBUTE
;
410 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
411 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
413 /* Copy as-is for the first pass */
414 memcpy(target
, so
->hw
, sz
);
416 /* Fixup offsets for the second pass. Recall that the hardware
417 * calculates attribute addresses as:
419 * addr = base + (stride * vtx) + src_offset;
421 * However, on Mali, base must be aligned to 64-bytes, so we
424 * base' = base & ~63 = base - (base & 63)
426 * To compensate when using base' (see emit_vertex_data), we have
427 * to adjust src_offset by the masked off piece:
429 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
430 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
431 * = base + (stride * vtx) + src_offset
437 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
439 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
440 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
441 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
442 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
444 /* Adjust by the masked off bits of the offset */
445 target
[i
].src_offset
+= (addr
& 63);
447 /* Also, somewhat obscurely per-instance data needs to be
448 * offset in response to a delayed start in an indexed draw */
450 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
451 target
[i
].src_offset
-= buf
->stride
* start
;
454 /* Let's also include vertex builtins */
456 target
[PAN_VERTEX_ID
].format
= MALI_R32UI
;
457 target
[PAN_VERTEX_ID
].swizzle
= panfrost_get_default_swizzle(1);
459 target
[PAN_INSTANCE_ID
].format
= MALI_R32UI
;
460 target
[PAN_INSTANCE_ID
].swizzle
= panfrost_get_default_swizzle(1);
462 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
466 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
468 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
469 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
471 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
474 if (ctx
->sampler_count
[t
]) {
475 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
477 struct panfrost_transfer transfer
=
478 panfrost_allocate_transient(batch
, transfer_size
);
480 struct mali_sampler_descriptor
*desc
=
481 (struct mali_sampler_descriptor
*) transfer
.cpu
;
483 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
484 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
486 upload
= transfer
.gpu
;
489 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
493 static enum mali_texture_layout
494 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
496 switch (rsrc
->layout
) {
498 return MALI_TEXTURE_AFBC
;
500 return MALI_TEXTURE_TILED
;
502 return MALI_TEXTURE_LINEAR
;
504 unreachable("Invalid texture layout");
510 struct panfrost_context
*ctx
,
511 enum pipe_shader_type st
,
512 struct panfrost_sampler_view
*view
)
517 struct pipe_sampler_view
*pview
= &view
->base
;
518 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
519 mali_ptr descriptor_gpu
;
522 /* Do we interleave an explicit stride with every element? */
524 bool has_manual_stride
= view
->manual_stride
;
526 /* For easy access */
528 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
529 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
530 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
531 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
532 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
533 unsigned first_face
= 0;
534 unsigned last_face
= 0;
535 unsigned face_mult
= 1;
537 /* Cubemaps have 6 faces as layers in between each actual layer.
538 * There's a bit of an impedence mismatch between Gallium and the
539 * hardware, let's fixup for it */
541 if (pview
->target
== PIPE_TEXTURE_CUBE
|| pview
->target
== PIPE_TEXTURE_CUBE_ARRAY
) {
542 /* TODO: logic wrong in the asserted out cases ... can they happen? */
544 first_face
= first_layer
% 6;
545 last_face
= last_layer
% 6;
549 assert((first_layer
== last_layer
) || (first_face
== 0 && last_face
== 5));
553 /* Lower-bit is set when sampling from colour AFBC */
554 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
555 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
556 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
558 /* Add the BO to the job so it's retained until the job is done. */
559 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
560 panfrost_batch_add_bo(batch
, rsrc
->bo
,
561 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
562 panfrost_bo_access_for_stage(st
));
564 /* Add the usage flags in, since they can change across the CSO
565 * lifetime due to layout switches */
567 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
568 view
->hw
.format
.manual_stride
= has_manual_stride
;
570 /* Inject the addresses in, interleaving array indices, mip levels,
571 * cube faces, and strides in that order */
574 unsigned levels
= 1 + last_level
- first_level
;
575 unsigned layers
= 1 + last_layer
- first_layer
;
576 unsigned faces
= 1 + last_face
- first_face
;
577 unsigned num_elements
= levels
* layers
* faces
;
578 if (has_manual_stride
)
581 descriptor
= malloc(sizeof(struct mali_texture_descriptor
) +
582 sizeof(mali_ptr
) * num_elements
);
583 memcpy(descriptor
, &view
->hw
, sizeof(struct mali_texture_descriptor
));
585 mali_ptr
*pointers_and_strides
= descriptor
+
586 sizeof(struct mali_texture_descriptor
);
588 for (unsigned w
= first_layer
; w
<= last_layer
; ++w
) {
589 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
590 for (unsigned f
= first_face
; f
<= last_face
; ++f
) {
591 pointers_and_strides
[idx
++] =
592 panfrost_get_texture_address(rsrc
, l
, w
*face_mult
+ f
)
593 + afbc_bit
+ view
->astc_stretch
;
595 if (has_manual_stride
) {
596 pointers_and_strides
[idx
++] =
597 rsrc
->slices
[l
].stride
;
603 descriptor_gpu
= panfrost_upload_transient(batch
, descriptor
,
604 sizeof(struct mali_texture_descriptor
) +
605 num_elements
* sizeof(*pointers_and_strides
));
608 return descriptor_gpu
;
612 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
614 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
616 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
617 mali_ptr trampoline
= 0;
619 if (ctx
->sampler_view_count
[t
]) {
620 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
622 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
624 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
626 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
629 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
633 struct sysval_uniform
{
642 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
643 struct sysval_uniform
*uniform
)
645 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
647 uniform
->f
[0] = vp
->scale
[0];
648 uniform
->f
[1] = vp
->scale
[1];
649 uniform
->f
[2] = vp
->scale
[2];
652 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
653 struct sysval_uniform
*uniform
)
655 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
657 uniform
->f
[0] = vp
->translate
[0];
658 uniform
->f
[1] = vp
->translate
[1];
659 uniform
->f
[2] = vp
->translate
[2];
662 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
663 enum pipe_shader_type st
,
664 unsigned int sysvalid
,
665 struct sysval_uniform
*uniform
)
667 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
668 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
669 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
670 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
673 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
676 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
677 tex
->u
.tex
.first_level
);
680 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
681 tex
->u
.tex
.first_level
);
684 uniform
->i
[dim
] = tex
->texture
->array_size
;
687 static void panfrost_upload_ssbo_sysval(
688 struct panfrost_context
*ctx
,
689 enum pipe_shader_type st
,
691 struct sysval_uniform
*uniform
)
693 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
694 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
696 /* Compute address */
697 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
698 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
700 panfrost_batch_add_bo(batch
, bo
,
701 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
702 panfrost_bo_access_for_stage(st
));
704 /* Upload address and size as sysval */
705 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
706 uniform
->u
[2] = sb
.buffer_size
;
710 panfrost_upload_sampler_sysval(
711 struct panfrost_context
*ctx
,
712 enum pipe_shader_type st
,
713 unsigned sampler_index
,
714 struct sysval_uniform
*uniform
)
716 struct pipe_sampler_state
*sampl
=
717 &ctx
->samplers
[st
][sampler_index
]->base
;
719 uniform
->f
[0] = sampl
->min_lod
;
720 uniform
->f
[1] = sampl
->max_lod
;
721 uniform
->f
[2] = sampl
->lod_bias
;
723 /* Even without any errata, Midgard represents "no mipmapping" as
724 * fixing the LOD with the clamps; keep behaviour consistent. c.f.
725 * panfrost_create_sampler_state which also explains our choice of
726 * epsilon value (again to keep behaviour consistent) */
728 if (sampl
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
729 uniform
->f
[1] = uniform
->f
[0] + (1.0/256.0);
732 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
733 struct sysval_uniform
*uniform
)
735 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
736 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
737 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
740 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
741 struct panfrost_shader_state
*ss
,
742 enum pipe_shader_type st
)
744 struct sysval_uniform
*uniforms
= (void *)buf
;
746 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
747 int sysval
= ss
->sysval
[i
];
749 switch (PAN_SYSVAL_TYPE(sysval
)) {
750 case PAN_SYSVAL_VIEWPORT_SCALE
:
751 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
753 case PAN_SYSVAL_VIEWPORT_OFFSET
:
754 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
756 case PAN_SYSVAL_TEXTURE_SIZE
:
757 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
760 case PAN_SYSVAL_SSBO
:
761 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
764 case PAN_SYSVAL_NUM_WORK_GROUPS
:
765 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
767 case PAN_SYSVAL_SAMPLER
:
768 panfrost_upload_sampler_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
778 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
780 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
781 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
784 return rsrc
->bo
->cpu
;
785 else if (cb
->user_buffer
)
786 return cb
->user_buffer
;
788 unreachable("No constant buffer");
792 panfrost_map_constant_buffer_gpu(
793 struct panfrost_context
*ctx
,
794 enum pipe_shader_type st
,
795 struct panfrost_constant_buffer
*buf
,
798 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
799 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
800 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
803 panfrost_batch_add_bo(batch
, rsrc
->bo
,
804 PAN_BO_ACCESS_SHARED
|
806 panfrost_bo_access_for_stage(st
));
808 /* Alignment gauranteed by PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */
809 return rsrc
->bo
->gpu
+ cb
->buffer_offset
;
810 } else if (cb
->user_buffer
) {
811 return panfrost_upload_transient(batch
, cb
->user_buffer
+ cb
->buffer_offset
, cb
->buffer_size
);
813 unreachable("No constant buffer");
817 /* Compute number of UBOs active (more specifically, compute the highest UBO
818 * number addressable -- if there are gaps, include them in the count anyway).
819 * We always include UBO #0 in the count, since we *need* uniforms enabled for
823 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
825 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
826 return 32 - __builtin_clz(mask
);
829 /* Fixes up a shader state with current state */
832 panfrost_patch_shader_state(struct panfrost_context
*ctx
,
833 enum pipe_shader_type stage
)
835 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
838 ctx
->payloads
[stage
].postfix
.shader
= 0;
842 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
844 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
845 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
847 ss
->tripipe
->midgard1
.flags
= 0x220;
849 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
850 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
852 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
854 /* Add the shader BO to the batch. */
855 panfrost_batch_add_bo(batch
, ss
->bo
,
856 PAN_BO_ACCESS_PRIVATE
|
858 panfrost_bo_access_for_stage(stage
));
860 ctx
->payloads
[stage
].postfix
.shader
= panfrost_upload_transient(batch
,
862 sizeof(struct mali_shader_meta
));
865 /* Go through dirty flags and actualise them in the cmdstream. */
868 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
870 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
871 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
873 panfrost_batch_add_fbo_bos(batch
);
874 panfrost_attach_vt_framebuffer(ctx
);
876 if (with_vertex_data
) {
877 panfrost_emit_vertex_data(batch
);
879 /* Varyings emitted for -all- geometry */
880 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
881 panfrost_emit_varying_descriptor(ctx
, total_count
);
884 bool msaa
= ctx
->rasterizer
->base
.multisample
;
886 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
887 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
889 /* TODO: Sample size */
890 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
891 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
894 panfrost_batch_set_requirements(batch
);
896 if (ctx
->occlusion_query
) {
897 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
;
898 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
901 panfrost_patch_shader_state(ctx
, PIPE_SHADER_VERTEX
);
902 panfrost_patch_shader_state(ctx
, PIPE_SHADER_COMPUTE
);
904 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
905 /* Check if we need to link the gl_PointSize varying */
906 if (!panfrost_writes_point_size(ctx
)) {
907 /* If the size is constant, write it out. Otherwise,
908 * don't touch primitive_size (since we would clobber
909 * the pointer there) */
911 bool points
= ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
913 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= points
?
914 ctx
->rasterizer
->base
.point_size
:
915 ctx
->rasterizer
->base
.line_width
;
919 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
920 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
921 ctx
->dirty
|= PAN_DIRTY_FS
;
923 if (ctx
->dirty
& PAN_DIRTY_FS
) {
924 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
925 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
927 panfrost_patch_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
929 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
932 COPY(attribute_count
);
936 COPY(midgard1
.uniform_count
);
937 COPY(midgard1
.uniform_buffer_count
);
938 COPY(midgard1
.work_count
);
939 COPY(midgard1
.flags
);
940 COPY(midgard1
.unknown2
);
944 /* Get blending setup */
945 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
947 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
948 unsigned shader_offset
= 0;
949 struct panfrost_bo
*shader_bo
= NULL
;
951 for (unsigned c
= 0; c
< rt_count
; ++c
) {
952 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
, &shader_bo
, &shader_offset
);
955 /* If there is a blend shader, work registers are shared. XXX: opt */
957 for (unsigned c
= 0; c
< rt_count
; ++c
) {
958 if (blend
[c
].is_shader
)
959 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
962 /* Depending on whether it's legal to in the given shader, we
963 * try to enable early-z testing (or forward-pixel kill?) */
965 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags
, MALI_EARLY_Z
, !variant
->can_discard
);
967 /* Any time texturing is used, derivatives are implicitly
968 * calculated, so we need to enable helper invocations */
970 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags
, MALI_HELPER_INVOCATIONS
, variant
->helper_invocations
);
972 /* Assign the stencil refs late */
974 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
975 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
976 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
978 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
979 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
981 /* CAN_DISCARD should be set if the fragment shader possibly
982 * contains a 'discard' instruction. It is likely this is
983 * related to optimizations related to forward-pixel kill, as
984 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
985 * thing?" by Peter Harris
988 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, variant
->can_discard
);
989 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags
, 0x400, variant
->can_discard
);
991 /* Even on MFBD, the shader descriptor gets blend shaders. It's
992 * *also* copied to the blend_meta appended (by convention),
993 * but this is the field actually read by the hardware. (Or
994 * maybe both are read...?). Specify the last RTi with a blend
997 ctx
->fragment_shader_core
.blend
.shader
= 0;
999 for (signed rt
= (rt_count
- 1); rt
>= 0; --rt
) {
1000 if (blend
[rt
].is_shader
) {
1001 ctx
->fragment_shader_core
.blend
.shader
=
1002 blend
[rt
].shader
.gpu
| blend
[rt
].shader
.first_tag
;
1007 if (screen
->quirks
& MIDGARD_SFBD
) {
1008 /* When only a single render target platform is used, the blend
1009 * information is inside the shader meta itself. We
1010 * additionally need to signal CAN_DISCARD for nontrivial blend
1011 * modes (so we're able to read back the destination buffer) */
1013 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_BLEND_SHADER
, blend
[0].is_shader
);
1015 if (!blend
[0].is_shader
) {
1016 ctx
->fragment_shader_core
.blend
.equation
=
1017 *blend
[0].equation
.equation
;
1018 ctx
->fragment_shader_core
.blend
.constant
=
1019 blend
[0].equation
.constant
;
1022 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, !blend
[0].no_blending
);
1025 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1026 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1027 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1029 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.shader
= transfer
.gpu
;
1031 if (!(screen
->quirks
& MIDGARD_SFBD
)) {
1032 /* Additional blend descriptor tacked on for jobs using MFBD */
1034 struct midgard_blend_rt rts
[4];
1036 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1037 rts
[i
].flags
= 0x200;
1040 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1041 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1042 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1044 SET_BIT(rts
[i
].flags
, MALI_BLEND_MRT_SHADER
, blend
[i
].is_shader
);
1045 SET_BIT(rts
[i
].flags
, MALI_BLEND_LOAD_TIB
, !blend
[i
].no_blending
);
1046 SET_BIT(rts
[i
].flags
, MALI_BLEND_SRGB
, is_srgb
);
1047 SET_BIT(rts
[i
].flags
, MALI_BLEND_NO_DITHER
, !ctx
->blend
->base
.dither
);
1049 if (blend
[i
].is_shader
) {
1050 rts
[i
].blend
.shader
= blend
[i
].shader
.gpu
| blend
[i
].shader
.first_tag
;
1052 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1053 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1057 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1061 /* We stage to transient, so always dirty.. */
1063 panfrost_stage_attributes(ctx
);
1065 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1066 panfrost_upload_sampler_descriptors(ctx
);
1068 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1069 panfrost_upload_texture_descriptors(ctx
);
1071 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1073 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1074 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1079 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1081 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1083 /* Uniforms are implicitly UBO #0 */
1084 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1086 /* Allocate room for the sysval and the uniforms */
1087 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1088 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1089 size_t size
= sys_size
+ uniform_size
;
1090 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1092 /* Upload sysvals requested by the shader */
1093 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1095 /* Upload uniforms */
1097 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1098 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1102 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1104 struct mali_vertex_tiler_postfix
*postfix
=
1105 &ctx
->payloads
[i
].postfix
;
1107 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1110 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1111 assert(ubo_count
>= 1);
1113 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1114 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1116 /* Upload uniforms as a UBO */
1117 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1118 ubos
[0].ptr
= transfer
.gpu
>> 2;
1120 /* The rest are honest-to-goodness UBOs */
1122 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1123 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1125 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1126 bool empty
= usz
== 0;
1128 if (!enabled
|| empty
) {
1129 /* Stub out disabled UBOs to catch accesses */
1132 ubos
[ubo
].ptr
= 0xDEAD0000;
1136 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, i
, buf
, ubo
);
1138 unsigned bytes_per_field
= 16;
1139 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1140 unsigned fields
= aligned
/ bytes_per_field
;
1142 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1143 ubos
[ubo
].ptr
= gpu
>> 2;
1146 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1147 postfix
->uniforms
= transfer
.gpu
;
1148 postfix
->uniform_buffers
= ubufs
;
1150 buf
->dirty_mask
= 0;
1153 /* TODO: Upload the viewport somewhere more appropriate */
1155 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1156 * (somewhat) asymmetric ints. */
1157 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1159 struct mali_viewport view
= {
1160 /* By default, do no viewport clipping, i.e. clip to (-inf,
1161 * inf) in each direction. Clipping to the viewport in theory
1162 * should work, but in practice causes issues when we're not
1163 * explicitly trying to scissor */
1165 .clip_minx
= -INFINITY
,
1166 .clip_miny
= -INFINITY
,
1167 .clip_maxx
= INFINITY
,
1168 .clip_maxy
= INFINITY
,
1171 /* Always scissor to the viewport by default. */
1172 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1173 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1175 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1176 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1178 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1179 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1181 /* Apply the scissor test */
1183 unsigned minx
, miny
, maxx
, maxy
;
1185 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1186 minx
= MAX2(ss
->minx
, vp_minx
);
1187 miny
= MAX2(ss
->miny
, vp_miny
);
1188 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1189 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1197 /* Hardware needs the min/max to be strictly ordered, so flip if we
1198 * need to. The viewport transformation in the vertex shader will
1199 * handle the negatives if we don't */
1202 unsigned temp
= miny
;
1208 unsigned temp
= minx
;
1219 /* Clamp to the framebuffer size as a last check */
1221 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1222 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1224 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1225 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1227 /* Update the job, unless we're doing wallpapering (whose lack of
1228 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1229 * just... be faster :) */
1231 if (!ctx
->wallpaper_batch
)
1232 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1236 view
.viewport0
[0] = minx
;
1237 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1239 view
.viewport0
[1] = miny
;
1240 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1242 view
.clip_minz
= minz
;
1243 view
.clip_maxz
= maxz
;
1245 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1246 panfrost_upload_transient(batch
,
1248 sizeof(struct mali_viewport
));
1253 /* Corresponds to exactly one draw, but does not submit anything */
1256 panfrost_queue_draw(struct panfrost_context
*ctx
)
1258 /* Handle dirty flags now */
1259 panfrost_emit_for_draw(ctx
, true);
1261 /* If rasterizer discard is enable, only submit the vertex */
1263 bool rasterizer_discard
= ctx
->rasterizer
1264 && ctx
->rasterizer
->base
.rasterizer_discard
;
1266 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1267 struct panfrost_transfer tiler
;
1269 if (!rasterizer_discard
)
1270 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1272 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1274 if (rasterizer_discard
)
1275 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1276 else if (ctx
->wallpaper_batch
&& batch
->first_tiler
.gpu
)
1277 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1279 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1281 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1282 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1287 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1288 batch
->stack_size
= MAX2(batch
->stack_size
, ss
->stack_size
);
1292 /* The entire frame is in memory -- send it off to the kernel! */
1296 struct pipe_context
*pipe
,
1297 struct pipe_fence_handle
**fence
,
1300 struct panfrost_context
*ctx
= pan_context(pipe
);
1301 struct util_dynarray fences
;
1303 /* We must collect the fences before the flush is done, otherwise we'll
1304 * lose track of them.
1307 util_dynarray_init(&fences
, NULL
);
1308 hash_table_foreach(ctx
->batches
, hentry
) {
1309 struct panfrost_batch
*batch
= hentry
->data
;
1311 panfrost_batch_fence_reference(batch
->out_sync
);
1312 util_dynarray_append(&fences
,
1313 struct panfrost_batch_fence
*,
1318 /* Submit all pending jobs */
1319 panfrost_flush_all_batches(ctx
, false);
1322 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
1323 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1324 *fence
= (struct pipe_fence_handle
*)f
;
1326 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
1327 panfrost_batch_fence_unreference(*fence
);
1329 util_dynarray_fini(&fences
);
1332 if (pan_debug
& PAN_DBG_TRACE
)
1333 pandecode_next_frame();
1336 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1339 g2m_draw_mode(enum pipe_prim_type mode
)
1342 DEFINE_CASE(POINTS
);
1344 DEFINE_CASE(LINE_LOOP
);
1345 DEFINE_CASE(LINE_STRIP
);
1346 DEFINE_CASE(TRIANGLES
);
1347 DEFINE_CASE(TRIANGLE_STRIP
);
1348 DEFINE_CASE(TRIANGLE_FAN
);
1350 DEFINE_CASE(QUAD_STRIP
);
1351 DEFINE_CASE(POLYGON
);
1354 unreachable("Invalid draw mode");
1361 panfrost_translate_index_size(unsigned size
)
1365 return MALI_DRAW_INDEXED_UINT8
;
1368 return MALI_DRAW_INDEXED_UINT16
;
1371 return MALI_DRAW_INDEXED_UINT32
;
1374 unreachable("Invalid index size");
1378 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1379 * good for the duration of the draw (transient), could last longer */
1382 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1384 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1386 off_t offset
= info
->start
* info
->index_size
;
1387 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1389 if (!info
->has_user_indices
) {
1390 /* Only resources can be directly mapped */
1391 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1392 PAN_BO_ACCESS_SHARED
|
1393 PAN_BO_ACCESS_READ
|
1394 PAN_BO_ACCESS_VERTEX_TILER
);
1395 return rsrc
->bo
->gpu
+ offset
;
1397 /* Otherwise, we need to upload to transient memory */
1398 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1399 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1404 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1406 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1408 /* Check if we're scissoring at all */
1410 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1413 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1416 /* Count generated primitives (when there is no geom/tess shaders) for
1417 * transform feedback */
1420 panfrost_statistics_record(
1421 struct panfrost_context
*ctx
,
1422 const struct pipe_draw_info
*info
)
1424 if (!ctx
->active_queries
)
1427 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1428 ctx
->prims_generated
+= prims
;
1430 if (!ctx
->streamout
.num_targets
)
1433 ctx
->tf_prims_generated
+= prims
;
1438 struct pipe_context
*pipe
,
1439 const struct pipe_draw_info
*info
)
1441 struct panfrost_context
*ctx
= pan_context(pipe
);
1443 /* First of all, check the scissor to see if anything is drawn at all.
1444 * If it's not, we drop the draw (mostly a conformance issue;
1445 * well-behaved apps shouldn't hit this) */
1447 if (panfrost_scissor_culls_everything(ctx
))
1450 int mode
= info
->mode
;
1452 /* Fallback unsupported restart index */
1453 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1455 if (info
->primitive_restart
&& info
->index_size
1456 && info
->restart_index
!= primitive_index
) {
1457 util_draw_vbo_without_prim_restart(pipe
, info
);
1461 /* Fallback for unsupported modes */
1463 assert(ctx
->rasterizer
!= NULL
);
1465 if (!(ctx
->draw_modes
& (1 << mode
))) {
1466 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1467 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1469 if (info
->count
< 4) {
1470 /* Degenerate case? */
1474 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1475 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1480 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1481 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1483 /* Now that we have a guaranteed terminating path, find the job.
1484 * Assignment commented out to prevent unused warning */
1486 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1488 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1490 /* Take into account a negative bias */
1491 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1492 ctx
->instance_count
= info
->instance_count
;
1493 ctx
->active_prim
= info
->mode
;
1495 /* For non-indexed draws, they're the same */
1496 unsigned vertex_count
= ctx
->vertex_count
;
1498 unsigned draw_flags
= 0;
1500 /* The draw flags interpret how primitive size is interpreted */
1502 if (panfrost_writes_point_size(ctx
))
1503 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1505 if (info
->primitive_restart
)
1506 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1508 /* These doesn't make much sense */
1510 draw_flags
|= 0x3000;
1512 if (ctx
->rasterizer
&& ctx
->rasterizer
->base
.flatshade_first
)
1513 draw_flags
|= MALI_DRAW_FLATSHADE_FIRST
;
1515 panfrost_statistics_record(ctx
, info
);
1517 if (info
->index_size
) {
1518 /* Calculate the min/max index used so we can figure out how
1519 * many times to invoke the vertex shader */
1521 /* Fetch / calculate index bounds */
1522 unsigned min_index
= 0, max_index
= 0;
1524 if (info
->max_index
== ~0u) {
1525 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1527 min_index
= info
->min_index
;
1528 max_index
= info
->max_index
;
1531 /* Use the corresponding values */
1532 vertex_count
= max_index
- min_index
+ 1;
1533 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1534 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1536 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1537 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1539 //assert(!info->restart_index); /* TODO: Research */
1541 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1542 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1544 /* Index count == vertex count, if no indexing is applied, as
1545 * if it is internally indexed in the expected order */
1547 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1548 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1550 /* Reverse index state */
1551 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1554 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1555 * vertex_count, 1) */
1557 panfrost_pack_work_groups_fused(
1558 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1559 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1560 1, vertex_count
, info
->instance_count
,
1563 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1565 /* Encode the padded vertex count */
1567 if (info
->instance_count
> 1) {
1568 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
1570 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
1571 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
1573 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= shift
;
1574 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= shift
;
1576 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= k
;
1577 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= k
;
1579 ctx
->padded_count
= vertex_count
;
1581 /* Reset instancing state */
1582 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1583 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1584 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1585 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1588 /* Fire off the draw itself */
1589 panfrost_queue_draw(ctx
);
1591 /* Increment transform feedback offsets */
1593 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1594 unsigned output_count
= u_stream_outputs_for_vertices(
1595 ctx
->active_prim
, ctx
->vertex_count
);
1597 ctx
->streamout
.offsets
[i
] += output_count
;
1604 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1610 panfrost_create_rasterizer_state(
1611 struct pipe_context
*pctx
,
1612 const struct pipe_rasterizer_state
*cso
)
1614 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1618 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1619 so
->tiler_gl_enables
= 0x7;
1622 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1624 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1625 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1627 if (cso
->cull_face
& PIPE_FACE_BACK
)
1628 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1634 panfrost_bind_rasterizer_state(
1635 struct pipe_context
*pctx
,
1638 struct panfrost_context
*ctx
= pan_context(pctx
);
1640 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1644 ctx
->rasterizer
= hwcso
;
1645 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1647 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
* 2.0f
;
1648 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1650 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1651 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1653 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1655 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1656 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1658 /* Point sprites are emulated */
1660 struct panfrost_shader_state
*variant
=
1661 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1663 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1664 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1668 panfrost_create_vertex_elements_state(
1669 struct pipe_context
*pctx
,
1670 unsigned num_elements
,
1671 const struct pipe_vertex_element
*elements
)
1673 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1675 so
->num_elements
= num_elements
;
1676 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1678 for (int i
= 0; i
< num_elements
; ++i
) {
1679 so
->hw
[i
].index
= i
;
1681 enum pipe_format fmt
= elements
[i
].src_format
;
1682 const struct util_format_description
*desc
= util_format_description(fmt
);
1683 so
->hw
[i
].unknown1
= 0x2;
1684 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1686 so
->hw
[i
].format
= panfrost_find_format(desc
);
1688 /* The field itself should probably be shifted over */
1689 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1696 panfrost_bind_vertex_elements_state(
1697 struct pipe_context
*pctx
,
1700 struct panfrost_context
*ctx
= pan_context(pctx
);
1702 ctx
->vertex
= hwcso
;
1703 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1707 panfrost_create_shader_state(
1708 struct pipe_context
*pctx
,
1709 const struct pipe_shader_state
*cso
,
1710 enum pipe_shader_type stage
)
1712 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1715 /* Token deep copy to prevent memory corruption */
1717 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1718 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1720 /* Precompile for shader-db if we need to */
1721 if (unlikely((pan_debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
1722 struct panfrost_context
*ctx
= pan_context(pctx
);
1724 struct mali_shader_meta meta
;
1725 struct panfrost_shader_state state
;
1726 uint64_t outputs_written
;
1728 panfrost_shader_compile(ctx
, &meta
,
1731 tgsi_processor_to_shader_stage(stage
), &state
,
1739 panfrost_delete_shader_state(
1740 struct pipe_context
*pctx
,
1743 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1745 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1746 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1749 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1750 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1751 panfrost_bo_unreference(shader_state
->bo
);
1752 shader_state
->bo
= NULL
;
1754 free(cso
->variants
);
1760 panfrost_create_sampler_state(
1761 struct pipe_context
*pctx
,
1762 const struct pipe_sampler_state
*cso
)
1764 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1767 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1769 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1770 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1771 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1773 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1774 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1775 unsigned mip_filter
= mip_linear
?
1776 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1777 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1779 struct mali_sampler_descriptor sampler_descriptor
= {
1780 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1781 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1782 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1783 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1784 .compare_func
= panfrost_flip_compare_func(
1785 panfrost_translate_compare_func(
1786 cso
->compare_func
)),
1788 cso
->border_color
.f
[0],
1789 cso
->border_color
.f
[1],
1790 cso
->border_color
.f
[2],
1791 cso
->border_color
.f
[3]
1793 .min_lod
= FIXED_16(cso
->min_lod
, false), /* clamp at 0 */
1794 .max_lod
= FIXED_16(cso
->max_lod
, false),
1795 .lod_bias
= FIXED_16(cso
->lod_bias
, true), /* can be negative */
1796 .seamless_cube_map
= cso
->seamless_cube_map
,
1799 /* If necessary, we disable mipmapping in the sampler descriptor by
1800 * clamping the LOD as tight as possible (from 0 to epsilon,
1801 * essentially -- remember these are fixed point numbers, so
1804 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1805 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1807 /* Enforce that there is something in the middle by adding epsilon*/
1809 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1810 sampler_descriptor
.max_lod
++;
1813 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1815 so
->hw
= sampler_descriptor
;
1821 panfrost_bind_sampler_states(
1822 struct pipe_context
*pctx
,
1823 enum pipe_shader_type shader
,
1824 unsigned start_slot
, unsigned num_sampler
,
1827 assert(start_slot
== 0);
1829 struct panfrost_context
*ctx
= pan_context(pctx
);
1831 /* XXX: Should upload, not just copy? */
1832 ctx
->sampler_count
[shader
] = num_sampler
;
1833 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1835 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1839 panfrost_variant_matches(
1840 struct panfrost_context
*ctx
,
1841 struct panfrost_shader_state
*variant
,
1842 enum pipe_shader_type type
)
1844 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1845 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1847 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1849 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1850 /* Make sure enable state is at least the same */
1851 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1855 /* Check that the contents of the test are the same */
1856 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1857 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1859 if (!(same_func
&& same_ref
)) {
1864 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1865 variant
->point_sprite_mask
)) {
1866 /* Ensure the same varyings are turned to point sprites */
1867 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1870 /* Ensure the orientation is correct */
1872 rasterizer
->sprite_coord_mode
==
1873 PIPE_SPRITE_COORD_UPPER_LEFT
;
1875 if (variant
->point_sprite_upper_left
!= upper_left
)
1879 /* Otherwise, we're good to go */
1884 * Fix an uncompiled shader's stream output info, and produce a bitmask
1885 * of which VARYING_SLOT_* are captured for stream output.
1887 * Core Gallium stores output->register_index as a "slot" number, where
1888 * slots are assigned consecutively to all outputs in info->outputs_written.
1889 * This naive packing of outputs doesn't work for us - we too have slots,
1890 * but the layout is defined by the VUE map, which we won't have until we
1891 * compile a specific shader variant. So, we remap these and simply store
1892 * VARYING_SLOT_* in our copy's output->register_index fields.
1894 * We then produce a bitmask of outputs which are used for SO.
1896 * Implementation from iris.
1900 update_so_info(struct pipe_stream_output_info
*so_info
,
1901 uint64_t outputs_written
)
1903 uint64_t so_outputs
= 0;
1904 uint8_t reverse_map
[64] = {0};
1907 while (outputs_written
)
1908 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1910 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1911 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1913 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1914 output
->register_index
= reverse_map
[output
->register_index
];
1916 so_outputs
|= 1ull << output
->register_index
;
1923 panfrost_bind_shader_state(
1924 struct pipe_context
*pctx
,
1926 enum pipe_shader_type type
)
1928 struct panfrost_context
*ctx
= pan_context(pctx
);
1930 ctx
->shader
[type
] = hwcso
;
1932 if (type
== PIPE_SHADER_FRAGMENT
)
1933 ctx
->dirty
|= PAN_DIRTY_FS
;
1935 ctx
->dirty
|= PAN_DIRTY_VS
;
1939 /* Match the appropriate variant */
1941 signed variant
= -1;
1942 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1944 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1945 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1951 if (variant
== -1) {
1952 /* No variant matched, so create a new one */
1953 variant
= variants
->variant_count
++;
1955 if (variants
->variant_count
> variants
->variant_space
) {
1956 unsigned old_space
= variants
->variant_space
;
1958 variants
->variant_space
*= 2;
1959 if (variants
->variant_space
== 0)
1960 variants
->variant_space
= 1;
1962 /* Arbitrary limit to stop runaway programs from
1963 * creating an unbounded number of shader variants. */
1964 assert(variants
->variant_space
< 1024);
1966 unsigned msize
= sizeof(struct panfrost_shader_state
);
1967 variants
->variants
= realloc(variants
->variants
,
1968 variants
->variant_space
* msize
);
1970 memset(&variants
->variants
[old_space
], 0,
1971 (variants
->variant_space
- old_space
) * msize
);
1974 struct panfrost_shader_state
*v
=
1975 &variants
->variants
[variant
];
1977 if (type
== PIPE_SHADER_FRAGMENT
) {
1978 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1980 if (ctx
->rasterizer
) {
1981 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1982 v
->point_sprite_upper_left
=
1983 ctx
->rasterizer
->base
.sprite_coord_mode
==
1984 PIPE_SPRITE_COORD_UPPER_LEFT
;
1988 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1992 /* Select this variant */
1993 variants
->active_variant
= variant
;
1995 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1996 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1998 /* We finally have a variant, so compile it */
2000 if (!shader_state
->compiled
) {
2001 uint64_t outputs_written
= 0;
2003 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
2004 variants
->base
.type
,
2005 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
2006 variants
->base
.ir
.nir
:
2007 variants
->base
.tokens
,
2008 tgsi_processor_to_shader_stage(type
), shader_state
,
2011 shader_state
->compiled
= true;
2013 /* Fixup the stream out information, since what Gallium returns
2014 * normally is mildly insane */
2016 shader_state
->stream_output
= variants
->base
.stream_output
;
2017 shader_state
->so_mask
=
2018 update_so_info(&shader_state
->stream_output
, outputs_written
);
2023 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
2025 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2029 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
2031 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2035 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2037 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2041 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2043 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2047 panfrost_set_vertex_buffers(
2048 struct pipe_context
*pctx
,
2049 unsigned start_slot
,
2050 unsigned num_buffers
,
2051 const struct pipe_vertex_buffer
*buffers
)
2053 struct panfrost_context
*ctx
= pan_context(pctx
);
2055 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2059 panfrost_set_constant_buffer(
2060 struct pipe_context
*pctx
,
2061 enum pipe_shader_type shader
, uint index
,
2062 const struct pipe_constant_buffer
*buf
)
2064 struct panfrost_context
*ctx
= pan_context(pctx
);
2065 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2067 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2069 unsigned mask
= (1 << index
);
2071 if (unlikely(!buf
)) {
2072 pbuf
->enabled_mask
&= ~mask
;
2073 pbuf
->dirty_mask
&= ~mask
;
2077 pbuf
->enabled_mask
|= mask
;
2078 pbuf
->dirty_mask
|= mask
;
2082 panfrost_set_stencil_ref(
2083 struct pipe_context
*pctx
,
2084 const struct pipe_stencil_ref
*ref
)
2086 struct panfrost_context
*ctx
= pan_context(pctx
);
2087 ctx
->stencil_ref
= *ref
;
2089 /* Shader core dirty */
2090 ctx
->dirty
|= PAN_DIRTY_FS
;
2093 static enum mali_texture_type
2094 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2098 case PIPE_TEXTURE_1D
:
2099 case PIPE_TEXTURE_1D_ARRAY
:
2102 case PIPE_TEXTURE_2D
:
2103 case PIPE_TEXTURE_2D_ARRAY
:
2104 case PIPE_TEXTURE_RECT
:
2107 case PIPE_TEXTURE_3D
:
2110 case PIPE_TEXTURE_CUBE
:
2111 case PIPE_TEXTURE_CUBE_ARRAY
:
2112 return MALI_TEX_CUBE
;
2115 unreachable("Unknown target");
2120 panfrost_compute_astc_stretch(
2121 const struct util_format_description
*desc
)
2123 unsigned width
= desc
->block
.width
;
2124 unsigned height
= desc
->block
.height
;
2125 assert(width
>= 4 && width
<= 12);
2126 assert(height
>= 4 && height
<= 12);
2131 return ((height
- 4) * 8) + (width
- 4);
2134 static struct pipe_sampler_view
*
2135 panfrost_create_sampler_view(
2136 struct pipe_context
*pctx
,
2137 struct pipe_resource
*texture
,
2138 const struct pipe_sampler_view
*template)
2140 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2141 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2143 pipe_reference(NULL
, &texture
->reference
);
2145 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2148 so
->base
= *template;
2149 so
->base
.texture
= texture
;
2150 so
->base
.reference
.count
= 1;
2151 so
->base
.context
= pctx
;
2153 /* sampler_views correspond to texture descriptors, minus the texture
2154 * (data) itself. So, we serialise the descriptor here and cache it for
2157 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2159 unsigned char user_swizzle
[4] = {
2160 template->swizzle_r
,
2161 template->swizzle_g
,
2162 template->swizzle_b
,
2166 enum mali_format format
= panfrost_find_format(desc
);
2168 if (format
== MALI_ASTC_HDR_SUPP
|| format
== MALI_ASTC_SRGB_SUPP
)
2169 so
->astc_stretch
= panfrost_compute_astc_stretch(desc
);
2171 /* Check if we need to set a custom stride by computing the "expected"
2172 * stride and comparing it to what the BO actually wants. Only applies
2173 * to linear textures, since tiled/compressed textures have strict
2174 * alignment requirements for their strides as it is */
2176 unsigned first_level
= template->u
.tex
.first_level
;
2177 unsigned last_level
= template->u
.tex
.last_level
;
2179 if (prsrc
->layout
== PAN_LINEAR
) {
2180 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2181 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2182 unsigned width
= u_minify(texture
->width0
, l
);
2183 unsigned comp_stride
= width
* bytes_per_pixel
;
2185 if (comp_stride
!= actual_stride
) {
2186 so
->manual_stride
= true;
2192 /* In the hardware, array_size refers specifically to array textures,
2193 * whereas in Gallium, it also covers cubemaps */
2195 unsigned array_size
= texture
->array_size
;
2197 if (template->target
== PIPE_TEXTURE_CUBE
) {
2198 /* TODO: Cubemap arrays */
2199 assert(array_size
== 6);
2203 struct mali_texture_descriptor texture_descriptor
= {
2204 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2205 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2206 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2207 .array_size
= MALI_POSITIVE(array_size
),
2210 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2212 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2213 .type
= panfrost_translate_texture_type(template->target
),
2217 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2220 texture_descriptor
.levels
= last_level
- first_level
;
2222 so
->hw
= texture_descriptor
;
2224 return (struct pipe_sampler_view
*) so
;
2228 panfrost_set_sampler_views(
2229 struct pipe_context
*pctx
,
2230 enum pipe_shader_type shader
,
2231 unsigned start_slot
, unsigned num_views
,
2232 struct pipe_sampler_view
**views
)
2234 struct panfrost_context
*ctx
= pan_context(pctx
);
2235 unsigned new_nr
= 0;
2238 assert(start_slot
== 0);
2240 for (i
= 0; i
< num_views
; ++i
) {
2243 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2247 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
2248 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2251 ctx
->sampler_view_count
[shader
] = new_nr
;
2253 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2257 panfrost_sampler_view_destroy(
2258 struct pipe_context
*pctx
,
2259 struct pipe_sampler_view
*view
)
2261 pipe_resource_reference(&view
->texture
, NULL
);
2266 panfrost_set_shader_buffers(
2267 struct pipe_context
*pctx
,
2268 enum pipe_shader_type shader
,
2269 unsigned start
, unsigned count
,
2270 const struct pipe_shader_buffer
*buffers
,
2271 unsigned writable_bitmask
)
2273 struct panfrost_context
*ctx
= pan_context(pctx
);
2275 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2276 buffers
, start
, count
);
2279 /* Hints that a framebuffer should use AFBC where possible */
2283 struct panfrost_screen
*screen
,
2284 const struct pipe_framebuffer_state
*fb
)
2286 /* AFBC implemenation incomplete; hide it */
2287 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2289 /* Hint AFBC to the resources bound to each color buffer */
2291 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2292 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2293 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2294 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2297 /* Also hint it to the depth buffer */
2300 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2301 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2306 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2307 const struct pipe_framebuffer_state
*fb
)
2309 struct panfrost_context
*ctx
= pan_context(pctx
);
2311 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
2312 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2314 panfrost_invalidate_frame(ctx
);
2318 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2319 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2321 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2325 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2328 struct panfrost_context
*ctx
= pan_context(pipe
);
2329 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2330 ctx
->depth_stencil
= depth_stencil
;
2335 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2336 * emulated in the fragment shader */
2338 if (depth_stencil
->alpha
.enabled
) {
2339 /* We need to trigger a new shader (maybe) */
2340 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2344 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2346 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2347 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2349 /* If back-stencil is not enabled, use the front values */
2350 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2351 unsigned back_index
= back_enab
? 1 : 0;
2353 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2354 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2356 /* Depth state (TODO: Refactor) */
2357 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_WRITEMASK
,
2358 depth_stencil
->depth
.writemask
);
2360 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2362 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2363 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2365 /* Bounds test not implemented */
2366 assert(!depth_stencil
->depth
.bounds_test
);
2368 ctx
->dirty
|= PAN_DIRTY_FS
;
2372 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2378 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2379 unsigned sample_mask
)
2384 panfrost_set_clip_state(struct pipe_context
*pipe
,
2385 const struct pipe_clip_state
*clip
)
2387 //struct panfrost_context *panfrost = pan_context(pipe);
2391 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2392 unsigned start_slot
,
2393 unsigned num_viewports
,
2394 const struct pipe_viewport_state
*viewports
)
2396 struct panfrost_context
*ctx
= pan_context(pipe
);
2398 assert(start_slot
== 0);
2399 assert(num_viewports
== 1);
2401 ctx
->pipe_viewport
= *viewports
;
2405 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2406 unsigned start_slot
,
2407 unsigned num_scissors
,
2408 const struct pipe_scissor_state
*scissors
)
2410 struct panfrost_context
*ctx
= pan_context(pipe
);
2412 assert(start_slot
== 0);
2413 assert(num_scissors
== 1);
2415 ctx
->scissor
= *scissors
;
2419 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2420 const struct pipe_poly_stipple
*stipple
)
2422 //struct panfrost_context *panfrost = pan_context(pipe);
2426 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2429 struct panfrost_context
*ctx
= pan_context(pipe
);
2430 ctx
->active_queries
= enable
;
2434 panfrost_destroy(struct pipe_context
*pipe
)
2436 struct panfrost_context
*panfrost
= pan_context(pipe
);
2438 if (panfrost
->blitter
)
2439 util_blitter_destroy(panfrost
->blitter
);
2441 if (panfrost
->blitter_wallpaper
)
2442 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2444 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
2445 u_upload_destroy(pipe
->stream_uploader
);
2450 static struct pipe_query
*
2451 panfrost_create_query(struct pipe_context
*pipe
,
2455 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2460 return (struct pipe_query
*) q
;
2464 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2466 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2469 panfrost_bo_unreference(query
->bo
);
2477 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2479 struct panfrost_context
*ctx
= pan_context(pipe
);
2480 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2482 switch (query
->type
) {
2483 case PIPE_QUERY_OCCLUSION_COUNTER
:
2484 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2485 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2486 /* Allocate a bo for the query results to be stored */
2488 query
->bo
= panfrost_bo_create(
2489 pan_screen(ctx
->base
.screen
),
2490 sizeof(unsigned), 0);
2493 unsigned *result
= (unsigned *)query
->bo
->cpu
;
2494 *result
= 0; /* Default to 0 if nothing at all drawn. */
2495 ctx
->occlusion_query
= query
;
2498 /* Geometry statistics are computed in the driver. XXX: geom/tess
2501 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2502 query
->start
= ctx
->prims_generated
;
2504 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2505 query
->start
= ctx
->tf_prims_generated
;
2509 fprintf(stderr
, "Skipping query %u\n", query
->type
);
2517 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2519 struct panfrost_context
*ctx
= pan_context(pipe
);
2520 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2522 switch (query
->type
) {
2523 case PIPE_QUERY_OCCLUSION_COUNTER
:
2524 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2525 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2526 ctx
->occlusion_query
= NULL
;
2528 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2529 query
->end
= ctx
->prims_generated
;
2531 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2532 query
->end
= ctx
->tf_prims_generated
;
2540 panfrost_get_query_result(struct pipe_context
*pipe
,
2541 struct pipe_query
*q
,
2543 union pipe_query_result
*vresult
)
2545 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2546 struct panfrost_context
*ctx
= pan_context(pipe
);
2549 switch (query
->type
) {
2550 case PIPE_QUERY_OCCLUSION_COUNTER
:
2551 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2552 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2554 panfrost_flush_all_batches(ctx
, true);
2556 /* Read back the query results */
2557 unsigned *result
= (unsigned *) query
->bo
->cpu
;
2558 unsigned passed
= *result
;
2560 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2561 vresult
->u64
= passed
;
2563 vresult
->b
= !!passed
;
2568 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2569 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2570 panfrost_flush_all_batches(ctx
, true);
2571 vresult
->u64
= query
->end
- query
->start
;
2575 DBG("Skipped query get %u\n", query
->type
);
2582 static struct pipe_stream_output_target
*
2583 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2584 struct pipe_resource
*prsc
,
2585 unsigned buffer_offset
,
2586 unsigned buffer_size
)
2588 struct pipe_stream_output_target
*target
;
2590 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2595 pipe_reference_init(&target
->reference
, 1);
2596 pipe_resource_reference(&target
->buffer
, prsc
);
2598 target
->context
= pctx
;
2599 target
->buffer_offset
= buffer_offset
;
2600 target
->buffer_size
= buffer_size
;
2606 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2607 struct pipe_stream_output_target
*target
)
2609 pipe_resource_reference(&target
->buffer
, NULL
);
2610 ralloc_free(target
);
2614 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2615 unsigned num_targets
,
2616 struct pipe_stream_output_target
**targets
,
2617 const unsigned *offsets
)
2619 struct panfrost_context
*ctx
= pan_context(pctx
);
2620 struct panfrost_streamout
*so
= &ctx
->streamout
;
2622 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2624 for (unsigned i
= 0; i
< num_targets
; i
++) {
2625 if (offsets
[i
] != -1)
2626 so
->offsets
[i
] = offsets
[i
];
2628 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2631 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2632 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2634 so
->num_targets
= num_targets
;
2637 struct pipe_context
*
2638 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2640 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2641 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2643 gallium
->screen
= screen
;
2645 gallium
->destroy
= panfrost_destroy
;
2647 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2649 gallium
->flush
= panfrost_flush
;
2650 gallium
->clear
= panfrost_clear
;
2651 gallium
->draw_vbo
= panfrost_draw_vbo
;
2653 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2654 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2655 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2657 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2659 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2660 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2661 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2663 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2664 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2665 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2667 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2668 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2669 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2671 gallium
->create_fs_state
= panfrost_create_fs_state
;
2672 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2673 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2675 gallium
->create_vs_state
= panfrost_create_vs_state
;
2676 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2677 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2679 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2680 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2681 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2683 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2684 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2685 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2687 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2689 gallium
->set_clip_state
= panfrost_set_clip_state
;
2690 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2691 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2692 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2693 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2695 gallium
->create_query
= panfrost_create_query
;
2696 gallium
->destroy_query
= panfrost_destroy_query
;
2697 gallium
->begin_query
= panfrost_begin_query
;
2698 gallium
->end_query
= panfrost_end_query
;
2699 gallium
->get_query_result
= panfrost_get_query_result
;
2701 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2702 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2703 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2705 panfrost_resource_context_init(gallium
);
2706 panfrost_blend_context_init(gallium
);
2707 panfrost_compute_context_init(gallium
);
2710 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2711 gallium
->const_uploader
= gallium
->stream_uploader
;
2712 assert(gallium
->stream_uploader
);
2714 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2715 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2717 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2719 ctx
->blitter
= util_blitter_create(gallium
);
2720 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2722 assert(ctx
->blitter
);
2723 assert(ctx
->blitter_wallpaper
);
2725 /* Prepare for render! */
2727 panfrost_batch_init(ctx
);
2728 panfrost_emit_vertex_payload(ctx
);
2729 panfrost_invalidate_frame(ctx
);
2730 panfrost_default_shader_backend(ctx
);