6acaf3d3859abe9ab3fb44917f3f8fda975054cf
[mesa.git] / src / gallium / drivers / panfrost / pan_mfbd.c
1 /*
2 * Copyright 2018-2019 Alyssa Rosenzweig
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 */
24
25 #include "pan_bo.h"
26 #include "pan_context.h"
27 #include "pan_cmdstream.h"
28 #include "pan_util.h"
29 #include "panfrost-quirks.h"
30
31 static struct mali_rt_format
32 panfrost_mfbd_format(struct pipe_surface *surf)
33 {
34 /* Explode details on the format */
35
36 const struct util_format_description *desc =
37 util_format_description(surf->format);
38
39 /* The swizzle for rendering is inverted from texturing */
40
41 unsigned char swizzle[4];
42 panfrost_invert_swizzle(desc->swizzle, swizzle);
43
44 /* Fill in accordingly, defaulting to 8-bit UNORM */
45
46 struct mali_rt_format fmt = {
47 .unk1 = 0x4000000,
48 .unk2 = 0x1,
49 .nr_channels = MALI_POSITIVE(desc->nr_channels),
50 .unk3 = 0x4,
51 .flags = 0x8,
52 .swizzle = panfrost_translate_swizzle_4(swizzle),
53 .no_preload = true
54 };
55
56 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
57 fmt.flags |= MALI_MFBD_FORMAT_SRGB;
58
59 /* sRGB handled as a dedicated flag */
60 enum pipe_format linearized = util_format_linear(surf->format);
61
62 /* If RGB, we're good to go */
63 if (util_format_is_unorm8(desc))
64 return fmt;
65
66 /* Set flags for alternative formats */
67
68 switch (linearized) {
69 case PIPE_FORMAT_B5G6R5_UNORM:
70 fmt.unk1 = 0x14000000;
71 fmt.nr_channels = MALI_POSITIVE(2);
72 fmt.unk3 |= 0x1;
73 break;
74
75 case PIPE_FORMAT_A4B4G4R4_UNORM:
76 case PIPE_FORMAT_B4G4R4A4_UNORM:
77 case PIPE_FORMAT_R4G4B4A4_UNORM:
78 fmt.unk1 = 0x10000000;
79 fmt.unk3 = 0x5;
80 fmt.nr_channels = MALI_POSITIVE(1);
81 break;
82
83 case PIPE_FORMAT_R10G10B10A2_UNORM:
84 case PIPE_FORMAT_B10G10R10A2_UNORM:
85 case PIPE_FORMAT_R10G10B10X2_UNORM:
86 case PIPE_FORMAT_B10G10R10X2_UNORM:
87 fmt.unk1 = 0x08000000;
88 fmt.unk3 = 0x6;
89 fmt.nr_channels = MALI_POSITIVE(1);
90 break;
91
92 case PIPE_FORMAT_B5G5R5A1_UNORM:
93 case PIPE_FORMAT_R5G5B5A1_UNORM:
94 case PIPE_FORMAT_B5G5R5X1_UNORM:
95 fmt.unk1 = 0x18000000;
96 fmt.unk3 = 0x7;
97 fmt.nr_channels = MALI_POSITIVE(2);
98 break;
99
100 /* Generic 8-bit */
101 case PIPE_FORMAT_R8_UINT:
102 case PIPE_FORMAT_R8_SINT:
103 fmt.unk1 = 0x80000000;
104 fmt.unk3 = 0x0;
105 fmt.nr_channels = MALI_POSITIVE(1);
106 break;
107
108 /* Generic 32-bit */
109 case PIPE_FORMAT_R11G11B10_FLOAT:
110 case PIPE_FORMAT_R8G8B8A8_UINT:
111 case PIPE_FORMAT_R8G8B8A8_SINT:
112 case PIPE_FORMAT_R16G16_FLOAT:
113 case PIPE_FORMAT_R16G16_UINT:
114 case PIPE_FORMAT_R16G16_SINT:
115 case PIPE_FORMAT_R32_FLOAT:
116 case PIPE_FORMAT_R32_UINT:
117 case PIPE_FORMAT_R32_SINT:
118 case PIPE_FORMAT_R10G10B10A2_UINT:
119 fmt.unk1 = 0x88000000;
120 fmt.unk3 = 0x0;
121 fmt.nr_channels = MALI_POSITIVE(4);
122 break;
123
124 /* Generic 16-bit */
125 case PIPE_FORMAT_R8G8_UINT:
126 case PIPE_FORMAT_R8G8_SINT:
127 case PIPE_FORMAT_R16_FLOAT:
128 case PIPE_FORMAT_R16_UINT:
129 case PIPE_FORMAT_R16_SINT:
130 fmt.unk1 = 0x84000000;
131 fmt.unk3 = 0x0;
132 fmt.nr_channels = MALI_POSITIVE(2);
133 break;
134
135 /* Generic 64-bit */
136 case PIPE_FORMAT_R32G32_FLOAT:
137 case PIPE_FORMAT_R32G32_SINT:
138 case PIPE_FORMAT_R32G32_UINT:
139 case PIPE_FORMAT_R16G16B16A16_FLOAT:
140 case PIPE_FORMAT_R16G16B16A16_SINT:
141 case PIPE_FORMAT_R16G16B16A16_UINT:
142 fmt.unk1 = 0x8c000000;
143 fmt.unk3 = 0x1;
144 fmt.nr_channels = MALI_POSITIVE(2);
145 break;
146
147 /* Generic 128-bit */
148 case PIPE_FORMAT_R32G32B32A32_FLOAT:
149 case PIPE_FORMAT_R32G32B32A32_SINT:
150 case PIPE_FORMAT_R32G32B32A32_UINT:
151 fmt.unk1 = 0x90000000;
152 fmt.unk3 = 0x1;
153 fmt.nr_channels = MALI_POSITIVE(4);
154 break;
155
156 default:
157 unreachable("Invalid format rendering");
158 }
159
160 return fmt;
161 }
162
163
164 static void
165 panfrost_mfbd_clear(
166 struct panfrost_batch *batch,
167 struct mali_framebuffer *fb,
168 struct mali_framebuffer_extra *fbx,
169 struct mali_render_target *rts,
170 unsigned rt_count)
171 {
172 struct panfrost_context *ctx = batch->ctx;
173 struct pipe_context *gallium = (struct pipe_context *) ctx;
174 struct panfrost_device *dev = pan_device(gallium->screen);
175
176 for (unsigned i = 0; i < rt_count; ++i) {
177 if (!(batch->clear & (PIPE_CLEAR_COLOR0 << i)))
178 continue;
179
180 rts[i].clear_color_1 = batch->clear_color[i][0];
181 rts[i].clear_color_2 = batch->clear_color[i][1];
182 rts[i].clear_color_3 = batch->clear_color[i][2];
183 rts[i].clear_color_4 = batch->clear_color[i][3];
184 }
185
186 if (batch->clear & PIPE_CLEAR_DEPTH) {
187 fb->clear_depth = batch->clear_depth;
188 }
189
190 if (batch->clear & PIPE_CLEAR_STENCIL) {
191 fb->clear_stencil = batch->clear_stencil;
192 }
193
194 if (dev->quirks & IS_BIFROST) {
195 fbx->clear_color_1 = batch->clear_color[0][0];
196 fbx->clear_color_2 = 0xc0000000 | (fbx->clear_color_1 & 0xffff); /* WTF? */
197 }
198 }
199
200 static void
201 panfrost_mfbd_set_cbuf(
202 struct mali_render_target *rt,
203 struct pipe_surface *surf)
204 {
205 struct panfrost_resource *rsrc = pan_resource(surf->texture);
206 struct panfrost_device *dev = pan_device(surf->context->screen);
207 bool is_bifrost = dev->quirks & IS_BIFROST;
208
209 unsigned level = surf->u.tex.level;
210 unsigned first_layer = surf->u.tex.first_layer;
211 assert(surf->u.tex.last_layer == first_layer);
212 int stride = rsrc->slices[level].stride;
213
214 /* Only set layer_stride for MSAA rendering */
215
216 unsigned nr_samples = surf->nr_samples;
217
218 if (!nr_samples)
219 nr_samples = surf->texture->nr_samples;
220
221 unsigned layer_stride = (nr_samples > 1) ? rsrc->slices[level].size0 : 0;
222
223 mali_ptr base = panfrost_get_texture_address(rsrc, level, first_layer, 0);
224
225 rt->format = panfrost_mfbd_format(surf);
226
227 /* Now, we set the layout specific pieces */
228
229 if (rsrc->layout == MALI_TEXTURE_LINEAR) {
230 if (is_bifrost) {
231 rt->format.unk4 = 0x1;
232 } else {
233 rt->format.block = MALI_BLOCK_LINEAR;
234 }
235
236 rt->framebuffer = base;
237 rt->framebuffer_stride = stride / 16;
238 rt->layer_stride = layer_stride;
239 } else if (rsrc->layout == MALI_TEXTURE_TILED) {
240 if (is_bifrost) {
241 rt->format.unk3 |= 0x8;
242 } else {
243 rt->format.block = MALI_BLOCK_TILED;
244 }
245
246 rt->framebuffer = base;
247 rt->framebuffer_stride = stride;
248 rt->layer_stride = layer_stride;
249 } else if (rsrc->layout == MALI_TEXTURE_AFBC) {
250 rt->format.block = MALI_BLOCK_AFBC;
251
252 unsigned header_size = rsrc->slices[level].header_size;
253
254 rt->framebuffer = base + header_size;
255 rt->layer_stride = layer_stride;
256 rt->afbc.metadata = base;
257 rt->afbc.stride = 0;
258 rt->afbc.flags = MALI_AFBC_FLAGS;
259
260 unsigned components = util_format_get_nr_components(surf->format);
261
262 /* The "lossless colorspace transform" is lossy for R and RG formats */
263 if (components >= 3)
264 rt->afbc.flags |= MALI_AFBC_YTR;
265
266 /* TODO: The blob sets this to something nonzero, but it's not
267 * clear what/how to calculate/if it matters */
268 rt->framebuffer_stride = 0;
269 } else {
270 fprintf(stderr, "Invalid render layout (cbuf)");
271 assert(0);
272 }
273 }
274
275 static void
276 panfrost_mfbd_set_zsbuf(
277 struct mali_framebuffer *fb,
278 struct mali_framebuffer_extra *fbx,
279 struct pipe_surface *surf)
280 {
281 struct panfrost_device *dev = pan_device(surf->context->screen);
282 bool is_bifrost = dev->quirks & IS_BIFROST;
283 struct panfrost_resource *rsrc = pan_resource(surf->texture);
284
285 unsigned level = surf->u.tex.level;
286 unsigned first_layer = surf->u.tex.first_layer;
287 assert(surf->u.tex.last_layer == first_layer);
288
289 mali_ptr base = panfrost_get_texture_address(rsrc, level, first_layer, 0);
290
291 if (rsrc->layout == MALI_TEXTURE_AFBC) {
292 /* The only Z/S format we can compress is Z24S8 or variants
293 * thereof (handled by the gallium frontend) */
294 assert(panfrost_is_z24s8_variant(surf->format));
295
296 unsigned header_size = rsrc->slices[level].header_size;
297
298 fb->mfbd_flags |= MALI_MFBD_EXTRA;
299
300 fbx->flags_hi |= MALI_EXTRA_PRESENT;
301 fbx->flags_lo |= MALI_EXTRA_ZS | 0x1; /* unknown */
302 fbx->zs_block = MALI_BLOCK_AFBC;
303
304 fbx->ds_afbc.depth_stencil = base + header_size;
305 fbx->ds_afbc.depth_stencil_afbc_metadata = base;
306 fbx->ds_afbc.depth_stencil_afbc_stride = 0;
307
308 fbx->ds_afbc.flags = MALI_AFBC_FLAGS;
309 fbx->ds_afbc.padding = 0x1000;
310 } else if (rsrc->layout == MALI_TEXTURE_LINEAR || rsrc->layout == MALI_TEXTURE_TILED) {
311 /* TODO: Z32F(S8) support, which is always linear */
312
313 int stride = rsrc->slices[level].stride;
314
315 fb->mfbd_flags |= MALI_MFBD_EXTRA;
316 fbx->flags_hi |= MALI_EXTRA_PRESENT;
317 fbx->flags_lo |= MALI_EXTRA_ZS;
318
319 fbx->ds_linear.depth = base;
320
321 if (rsrc->layout == MALI_TEXTURE_LINEAR) {
322 fbx->zs_block = MALI_BLOCK_LINEAR;
323 fbx->ds_linear.depth_stride = stride / 16;
324 } else {
325 if (is_bifrost) {
326 fbx->zs_block = MALI_BLOCK_UNKNOWN;
327 fbx->flags_hi |= 0x4400;
328 fbx->flags_lo |= 0x1;
329 } else {
330 fbx->zs_block = MALI_BLOCK_TILED;
331 }
332
333 fbx->ds_linear.depth_stride = stride;
334 }
335
336 if (panfrost_is_z24s8_variant(surf->format)) {
337 fbx->flags_lo |= 0x1;
338 } else if (surf->format == PIPE_FORMAT_Z32_FLOAT) {
339 fbx->flags_lo |= 0xA;
340 fb->mfbd_flags ^= 0x100;
341 fb->mfbd_flags |= 0x200;
342 } else if (surf->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
343 fbx->flags_hi |= 0x400;
344 fbx->flags_lo |= 0xA;
345 fb->mfbd_flags ^= 0x100;
346 fb->mfbd_flags |= 0x201;
347
348 struct panfrost_resource *stencil = rsrc->separate_stencil;
349 struct panfrost_slice stencil_slice = stencil->slices[level];
350
351 fbx->ds_linear.stencil = panfrost_get_texture_address(stencil, level, first_layer, 0);
352 fbx->ds_linear.stencil_stride = stencil_slice.stride;
353 }
354
355 } else {
356 assert(0);
357 }
358 }
359
360 /* Helper for sequential uploads used for MFBD */
361
362 #define UPLOAD(dest, offset, src, max) { \
363 size_t sz = sizeof(*src); \
364 memcpy(dest.cpu + offset, src, sz); \
365 assert((offset + sz) <= max); \
366 offset += sz; \
367 }
368
369 static mali_ptr
370 panfrost_mfbd_upload(struct panfrost_batch *batch,
371 struct mali_framebuffer *fb,
372 struct mali_framebuffer_extra *fbx,
373 struct mali_render_target *rts,
374 unsigned rt_count)
375 {
376 off_t offset = 0;
377
378 /* There may be extra data stuck in the middle */
379 bool has_extra = fb->mfbd_flags & MALI_MFBD_EXTRA;
380
381 /* Compute total size for transfer */
382
383 size_t total_sz =
384 sizeof(struct mali_framebuffer) +
385 (has_extra ? sizeof(struct mali_framebuffer_extra) : 0) +
386 sizeof(struct mali_render_target) * 4;
387
388 struct panfrost_transfer m_f_trans =
389 panfrost_allocate_transient(batch, total_sz);
390
391 /* Do the transfer */
392
393 UPLOAD(m_f_trans, offset, fb, total_sz);
394
395 if (has_extra)
396 UPLOAD(m_f_trans, offset, fbx, total_sz);
397
398 for (unsigned c = 0; c < 4; ++c) {
399 UPLOAD(m_f_trans, offset, &rts[c], total_sz);
400 }
401
402 /* Return pointer suitable for the fragment section */
403 unsigned tag =
404 MALI_MFBD |
405 (has_extra ? MALI_MFBD_TAG_EXTRA : 0) |
406 (MALI_POSITIVE(rt_count) << 2);
407
408 return m_f_trans.gpu | tag;
409 }
410
411 #undef UPLOAD
412
413 /* Determines whether a framebuffer uses too much tilebuffer space (requiring
414 * us to scale up the tile at a performance penalty). This is conservative but
415 * afaict you get 128-bits per pixel normally */
416
417 static bool
418 pan_is_large_tib(struct panfrost_batch *batch)
419 {
420 unsigned size = 0;
421
422 for (int cb = 0; cb < batch->key.nr_cbufs; ++cb) {
423 struct pipe_surface *surf = batch->key.cbufs[cb];
424 assert(surf);
425 unsigned bpp = util_format_get_blocksize(surf->format);
426 size += ALIGN_POT(bpp, 4);
427 }
428
429 return (size > 16);
430 }
431
432 static struct mali_framebuffer
433 panfrost_emit_mfbd(struct panfrost_batch *batch, unsigned vertex_count)
434 {
435 struct panfrost_context *ctx = batch->ctx;
436 struct pipe_context *gallium = (struct pipe_context *) ctx;
437 struct panfrost_device *dev = pan_device(gallium->screen);
438
439 unsigned width = batch->key.width;
440 unsigned height = batch->key.height;
441
442 struct mali_framebuffer mfbd = {
443 .width1 = MALI_POSITIVE(width),
444 .height1 = MALI_POSITIVE(height),
445 .width2 = MALI_POSITIVE(width),
446 .height2 = MALI_POSITIVE(height),
447
448 /* Seems to configure tib size */
449 .unk1 = pan_is_large_tib(batch) ? 0xc80 : 0x1080,
450
451 .rt_count_1 = MALI_POSITIVE(batch->key.nr_cbufs),
452 .rt_count_2 = 4,
453 };
454
455 if (dev->quirks & IS_BIFROST) {
456 mfbd.msaa.sample_locations = panfrost_emit_sample_locations(batch);
457 mfbd.tiler_meta = panfrost_batch_get_tiler_meta(batch, vertex_count);
458 } else {
459 unsigned shift = panfrost_get_stack_shift(batch->stack_size);
460 struct panfrost_bo *bo = panfrost_batch_get_scratchpad(batch,
461 shift,
462 dev->thread_tls_alloc,
463 dev->core_count);
464 mfbd.shared_memory.stack_shift = shift;
465 mfbd.shared_memory.scratchpad = bo->gpu;
466 mfbd.shared_memory.shared_workgroup_count = ~0;
467
468 mfbd.tiler = panfrost_emit_midg_tiler(batch, vertex_count);
469 }
470
471 return mfbd;
472 }
473
474 void
475 panfrost_attach_mfbd(struct panfrost_batch *batch, unsigned vertex_count)
476 {
477 struct mali_framebuffer mfbd =
478 panfrost_emit_mfbd(batch, vertex_count);
479
480 memcpy(batch->framebuffer.cpu, &mfbd, sizeof(mfbd));
481 }
482
483 /* Creates an MFBD for the FRAGMENT section of the bound framebuffer */
484
485 mali_ptr
486 panfrost_mfbd_fragment(struct panfrost_batch *batch, bool has_draws)
487 {
488 struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
489 bool is_bifrost = dev->quirks & IS_BIFROST;
490
491 struct mali_framebuffer fb = panfrost_emit_mfbd(batch, has_draws);
492 struct mali_framebuffer_extra fbx = {0};
493 struct mali_render_target rts[4] = {0};
494
495 /* We always upload at least one dummy GL_NONE render target */
496
497 unsigned rt_descriptors = MAX2(batch->key.nr_cbufs, 1);
498
499 fb.rt_count_1 = MALI_POSITIVE(rt_descriptors);
500 fb.rt_count_2 = rt_descriptors;
501 fb.mfbd_flags = 0x100;
502
503 /* TODO: MRT clear */
504 panfrost_mfbd_clear(batch, &fb, &fbx, rts, fb.rt_count_2);
505
506
507 /* Upload either the render target or a dummy GL_NONE target */
508
509 for (int cb = 0; cb < rt_descriptors; ++cb) {
510 struct pipe_surface *surf = batch->key.cbufs[cb];
511
512 if (surf) {
513 panfrost_mfbd_set_cbuf(&rts[cb], surf);
514
515 /* What is this? Looks like some extension of the bpp
516 * field. Maybe it establishes how much internal
517 * tilebuffer space is reserved? */
518
519 unsigned bpp = util_format_get_blocksize(surf->format);
520 fb.rt_count_2 = MAX2(fb.rt_count_2, ALIGN_POT(bpp, 4) / 4);
521 } else {
522 struct mali_rt_format null_rt = {
523 .unk1 = 0x4000000,
524 .no_preload = true
525 };
526
527 if (is_bifrost) {
528 null_rt.flags = 0x8;
529 null_rt.unk3 = 0x8;
530 }
531
532 rts[cb].format = null_rt;
533 rts[cb].framebuffer = 0;
534 rts[cb].framebuffer_stride = 0;
535 }
536
537 /* TODO: Break out the field */
538 rts[cb].format.unk1 |= (cb * 0x400);
539 }
540
541 if (batch->key.zsbuf) {
542 panfrost_mfbd_set_zsbuf(&fb, &fbx, batch->key.zsbuf);
543 }
544
545 /* When scanning out, the depth buffer is immediately invalidated, so
546 * we don't need to waste bandwidth writing it out. This can improve
547 * performance substantially (Z24X8_UNORM 1080p @ 60fps is 475 MB/s of
548 * memory bandwidth!).
549 *
550 * The exception is ReadPixels, but this is not supported on GLES so we
551 * can safely ignore it. */
552
553 if (panfrost_batch_is_scanout(batch))
554 batch->requirements &= ~PAN_REQ_DEPTH_WRITE;
555
556 /* Actualize the requirements */
557
558 if (batch->requirements & PAN_REQ_MSAA) {
559 rts[0].format.flags |= MALI_MFBD_FORMAT_MSAA;
560
561 /* XXX */
562 fb.unk1 |= (1 << 4) | (1 << 1);
563 fb.rt_count_2 = 4;
564 }
565
566 if (batch->requirements & PAN_REQ_DEPTH_WRITE)
567 fb.mfbd_flags |= MALI_MFBD_DEPTH_WRITE;
568
569 /* Checksumming only works with a single render target */
570
571 if (batch->key.nr_cbufs == 1) {
572 struct pipe_surface *surf = batch->key.cbufs[0];
573 struct panfrost_resource *rsrc = pan_resource(surf->texture);
574
575 if (rsrc->checksummed) {
576 unsigned level = surf->u.tex.level;
577 struct panfrost_slice *slice = &rsrc->slices[level];
578
579 fb.mfbd_flags |= MALI_MFBD_EXTRA;
580 fbx.flags_hi |= MALI_EXTRA_PRESENT;
581 fbx.checksum_stride = slice->checksum_stride;
582 if (slice->checksum_bo)
583 fbx.checksum = slice->checksum_bo->gpu;
584 else
585 fbx.checksum = rsrc->bo->gpu + slice->checksum_offset;
586 }
587 }
588
589 return panfrost_mfbd_upload(batch, &fb, &fbx, rts, rt_descriptors);
590 }