src/gallium/drivers/panfrost/pan_resource.h

   1 /*
   2  * © Copyright2018-2019 Alyssa Rosenzweig
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24
  25
  26 #ifndef PAN_RESOURCE_H
  27 #define PAN_RESOURCE_H
  28
  29 #include <panfrost-job.h>
  30 #include "pan_screen.h"
  31 #include "pan_allocate.h"
  32 #include "drm-uapi/drm.h"
  33
  34 /* Describes the memory layout of a BO */
  35
  36 enum panfrost_memory_layout {
  37         PAN_LINEAR,
  38         PAN_TILED,
  39         PAN_AFBC
  40 };
  41
  42 struct panfrost_bo {
  43         /* Address to the BO in question */
  44
  45         uint8_t *cpu[MAX_MIP_LEVELS];
  46
  47         /* Not necessarily a GPU mapping of cpu! In case of texture tiling, gpu
  48          * points to the GPU-side, tiled texture, while cpu points to the
  49          * CPU-side, untiled texture from mesa */
  50
  51         mali_ptr gpu[MAX_MIP_LEVELS];
  52
  53         /* Memory entry corresponding to gpu above */
  54         struct panfrost_memory_entry *entry[MAX_MIP_LEVELS];
  55
  56         /* Set if this bo was imported rather than allocated */
  57         bool imported;
  58
  59         /* Number of bytes of allocation */
  60         size_t size[MAX_MIP_LEVELS];
  61
  62         /* Internal layout (tiled?) */
  63         enum panfrost_memory_layout layout;
  64
  65         /* Is something other than level 0 ever written? */
  66         bool is_mipmap;
  67
  68         /* If AFBC is enabled for this resource, we lug around an AFBC
  69          * metadata buffer as well. The actual AFBC resource is also in
  70          * afbc_slab (only defined for AFBC) at position afbc_main_offset
  71          */
  72
  73         struct panfrost_memory afbc_slab;
  74         int afbc_metadata_size;
  75
  76         /* If transaciton elimination is enabled, we have a dedicated
  77          * buffer for that as well. */
  78
  79         bool has_checksum;
  80         struct panfrost_memory checksum_slab;
  81         int checksum_stride;
  82
  83         int gem_handle;
  84 };
  85
  86 struct panfrost_resource {
  87         struct pipe_resource base;
  88
  89         struct panfrost_bo *bo;
  90         struct renderonly_scanout *scanout;
  91
  92         struct panfrost_resource *separate_stencil;
  93 };
  94
  95 static inline struct panfrost_resource *
  96 pan_resource(struct pipe_resource *p)
  97 {
  98    return (struct panfrost_resource *)p;
  99 }
 100
 101 void panfrost_resource_screen_init(struct panfrost_screen *screen);
 102
 103 void panfrost_resource_context_init(struct pipe_context *pctx);
 104
 105 #endif /* PAN_RESOURCE_H */