2 * Copyright (C) 2008 VMware, Inc.
3 * Copyright (C) 2014 Broadcom
4 * Copyright (C) 2018 Alyssa Rosenzweig
5 * Copyright (C) 2019 Collabora, Ltd.
6 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 #include "util/u_debug.h"
30 #include "util/u_memory.h"
31 #include "util/format/u_format.h"
32 #include "util/format/u_format_s3tc.h"
33 #include "util/u_video.h"
34 #include "util/u_screen.h"
35 #include "util/os_time.h"
36 #include "util/u_process.h"
37 #include "pipe/p_defines.h"
38 #include "pipe/p_screen.h"
39 #include "draw/draw_context.h"
43 #include "drm-uapi/drm_fourcc.h"
44 #include "drm-uapi/panfrost_drm.h"
47 #include "pan_screen.h"
48 #include "pan_resource.h"
49 #include "pan_public.h"
51 #include "pandecode/decode.h"
53 #include "pan_context.h"
54 #include "midgard/midgard_compile.h"
55 #include "bifrost/bifrost_compile.h"
56 #include "panfrost-quirks.h"
58 static const struct debug_named_value debug_options
[] = {
59 {"msgs", PAN_DBG_MSGS
, "Print debug messages"},
60 {"trace", PAN_DBG_TRACE
, "Trace the command stream"},
61 {"deqp", PAN_DBG_DEQP
, "Hacks for dEQP"},
62 {"afbc", PAN_DBG_AFBC
, "Enable non-conformant AFBC impl"},
63 {"sync", PAN_DBG_SYNC
, "Wait for each job's completion and check for any GPU fault"},
64 {"precompile", PAN_DBG_PRECOMPILE
, "Precompile shaders for shader-db"},
65 {"gles3", PAN_DBG_GLES3
, "Enable experimental GLES3 implementation"},
66 {"fp16", PAN_DBG_FP16
, "Enable buggy experimental (don't use!) fp16"},
67 {"bifrost", PAN_DBG_BIFROST
, "Enable experimental Mali G31 and G52 support"},
68 {"gl3", PAN_DBG_GL3
, "Enable experimental GL 3.x implementation, up to 3.3"},
72 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug
, "PAN_MESA_DEBUG", debug_options
, 0)
77 panfrost_get_name(struct pipe_screen
*screen
)
79 return panfrost_model_name(pan_device(screen
)->gpu_id
);
83 panfrost_get_vendor(struct pipe_screen
*screen
)
89 panfrost_get_device_vendor(struct pipe_screen
*screen
)
95 panfrost_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
97 /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
98 bool is_deqp
= pan_debug
& PAN_DBG_DEQP
;
99 struct panfrost_device
*dev
= pan_device(screen
);
101 /* Our GL 3.x implementation is WIP */
102 bool is_gl3
= pan_debug
& PAN_DBG_GL3
;
105 /* Same with GLES 3 */
106 bool is_gles3
= pan_debug
& PAN_DBG_GLES3
;
110 case PIPE_CAP_NPOT_TEXTURES
:
111 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
112 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
113 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
114 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
115 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
116 case PIPE_CAP_POINT_SPRITE
:
117 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
118 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
121 case PIPE_CAP_MAX_RENDER_TARGETS
:
122 return is_gles3
? 4 : 1;
124 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
125 return is_gl3
? 1 : 0;
127 /* Throttling frames breaks pipelining */
128 case PIPE_CAP_THROTTLE
:
131 case PIPE_CAP_OCCLUSION_QUERY
:
133 case PIPE_CAP_QUERY_TIME_ELAPSED
:
134 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
135 case PIPE_CAP_QUERY_SO_OVERFLOW
:
138 case PIPE_CAP_TEXTURE_SWIZZLE
:
141 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
142 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
145 case PIPE_CAP_TGSI_INSTANCEID
:
146 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
147 case PIPE_CAP_PRIMITIVE_RESTART
:
148 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX
:
151 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
152 return is_gles3
? 4 : 0;
153 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
154 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
155 return is_gles3
? 64 : 0;
156 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
159 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
162 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
163 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
164 return is_gl3
? 330 : (is_gles3
? 140 : 120);
165 case PIPE_CAP_ESSL_FEATURE_LEVEL
:
166 return is_gles3
? 300 : 120;
168 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
171 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
174 /* For faking GLES 3.1 for dEQP-GLES31 */
175 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS
:
176 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS
:
177 case PIPE_CAP_IMAGE_LOAD_FORMATTED
:
178 case PIPE_CAP_CUBE_MAP_ARRAY
:
181 /* For faking compute shaders */
182 case PIPE_CAP_COMPUTE
:
185 case PIPE_CAP_QUERY_TIMESTAMP
:
186 case PIPE_CAP_CONDITIONAL_RENDER
:
189 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
191 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
192 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
195 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
196 case PIPE_CAP_INDEP_BLEND_ENABLE
:
197 case PIPE_CAP_INDEP_BLEND_FUNC
:
200 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
201 /* Hardware is natively upper left */
204 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
205 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
206 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
207 case PIPE_CAP_GENERATE_MIPMAP
:
210 /* We would prefer varyings on Midgard, but proper sysvals on Bifrost */
211 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
212 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
213 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL
:
214 return dev
->quirks
& IS_BIFROST
;
216 /* I really don't want to set this CAP but let's not swim against the
218 case PIPE_CAP_TGSI_TEXCOORD
:
221 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
222 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
225 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET
:
228 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
231 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
234 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
237 case PIPE_CAP_ENDIANNESS
:
238 return PIPE_ENDIAN_NATIVE
;
240 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
243 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
246 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
249 case PIPE_CAP_VENDOR_ID
:
250 case PIPE_CAP_DEVICE_ID
:
253 case PIPE_CAP_ACCELERATED
:
255 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
256 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
257 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
258 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
261 case PIPE_CAP_VIDEO_MEMORY
: {
262 uint64_t system_memory
;
264 if (!os_get_total_physical_memory(&system_memory
))
267 return (int)(system_memory
>> 20);
270 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
273 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
276 case PIPE_CAP_MAX_VARYINGS
:
279 case PIPE_CAP_ALPHA_TEST
:
280 case PIPE_CAP_FLATSHADE
:
281 case PIPE_CAP_TWO_SIDED_COLOR
:
282 case PIPE_CAP_CLIP_PLANES
:
285 case PIPE_CAP_PACKED_STREAM_OUTPUT
:
288 case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED
:
289 case PIPE_CAP_PSIZ_CLAMPED
:
293 return u_pipe_screen_get_param_defaults(screen
, param
);
298 panfrost_get_shader_param(struct pipe_screen
*screen
,
299 enum pipe_shader_type shader
,
300 enum pipe_shader_cap param
)
302 bool is_deqp
= pan_debug
& PAN_DBG_DEQP
;
303 bool is_fp16
= pan_debug
& PAN_DBG_FP16
;
304 struct panfrost_device
*dev
= pan_device(screen
);
306 if (shader
!= PIPE_SHADER_VERTEX
&&
307 shader
!= PIPE_SHADER_FRAGMENT
&&
308 !(shader
== PIPE_SHADER_COMPUTE
&& is_deqp
))
311 /* this is probably not totally correct.. but it's a start: */
313 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
314 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
315 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
316 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
319 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
322 case PIPE_SHADER_CAP_MAX_INPUTS
:
325 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
326 return shader
== PIPE_SHADER_FRAGMENT
? 4 : 16;
328 case PIPE_SHADER_CAP_MAX_TEMPS
:
329 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
331 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
332 return 16 * 1024 * sizeof(float);
334 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
335 return PAN_MAX_CONST_BUFFERS
;
337 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
340 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
342 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
345 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
348 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
351 case PIPE_SHADER_CAP_SUBROUTINES
:
354 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
357 case PIPE_SHADER_CAP_INTEGERS
:
360 case PIPE_SHADER_CAP_FP16
:
361 return !(dev
->quirks
& MIDGARD_BROKEN_FP16
) || is_fp16
;
363 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
364 case PIPE_SHADER_CAP_INT16
:
365 case PIPE_SHADER_CAP_GLSL_16BIT_TEMPS
:
366 case PIPE_SHADER_CAP_INT64_ATOMICS
:
367 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
368 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
369 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
370 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
371 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
374 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
375 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
376 return 16; /* XXX: How many? */
378 case PIPE_SHADER_CAP_PREFERRED_IR
:
379 return PIPE_SHADER_IR_NIR
;
381 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
382 return (1 << PIPE_SHADER_IR_NIR
) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED
);
384 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
387 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
388 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
389 return is_deqp
? 8 : 0;
390 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
391 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
394 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
395 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
399 DBG("unknown shader param %d\n", param
);
407 panfrost_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
410 case PIPE_CAPF_MAX_LINE_WIDTH
:
413 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
414 return 255.0; /* arbitrary */
416 case PIPE_CAPF_MAX_POINT_WIDTH
:
419 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
422 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
425 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
426 return 16.0; /* arbitrary */
428 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
429 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
430 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
434 debug_printf("Unexpected PIPE_CAPF %d query\n", param
);
440 * Query format support for creating a texture, drawing surface, etc.
441 * \param format the format to test
442 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
445 panfrost_is_format_supported( struct pipe_screen
*screen
,
446 enum pipe_format format
,
447 enum pipe_texture_target target
,
448 unsigned sample_count
,
449 unsigned storage_sample_count
,
452 const struct util_format_description
*format_desc
;
454 assert(target
== PIPE_BUFFER
||
455 target
== PIPE_TEXTURE_1D
||
456 target
== PIPE_TEXTURE_1D_ARRAY
||
457 target
== PIPE_TEXTURE_2D
||
458 target
== PIPE_TEXTURE_2D_ARRAY
||
459 target
== PIPE_TEXTURE_RECT
||
460 target
== PIPE_TEXTURE_3D
||
461 target
== PIPE_TEXTURE_CUBE
||
462 target
== PIPE_TEXTURE_CUBE_ARRAY
);
464 format_desc
= util_format_description(format
);
469 /* MSAA 4x supported, but no more. Technically some revisions of the
470 * hardware can go up to 16x but we don't support higher modes yet.
471 * MSAA 2x is notably not supported and gets rounded up to MSAA 4x. */
473 if (!(sample_count
== 0 || sample_count
== 1 || sample_count
== 4))
476 if (MAX2(sample_count
, 1) != MAX2(storage_sample_count
, 1))
479 /* Don't confuse poorly written apps (workaround dEQP bug) that expect
480 * more alpha than they ask for */
482 bool scanout
= bind
& (PIPE_BIND_SCANOUT
| PIPE_BIND_SHARED
| PIPE_BIND_DISPLAY_TARGET
);
483 bool renderable
= bind
& PIPE_BIND_RENDER_TARGET
;
485 if (scanout
&& renderable
&& !util_format_is_rgba8_variant(format_desc
))
488 if (pan_debug
& (PAN_DBG_GL3
| PAN_DBG_DEQP
)) {
489 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
)
493 /* Check we support the format with the given bind */
495 unsigned relevant_bind
= bind
&
496 ( PIPE_BIND_DEPTH_STENCIL
| PIPE_BIND_RENDER_TARGET
497 | PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_SAMPLER_VIEW
);
499 struct panfrost_format fmt
= panfrost_pipe_format_table
[format
];
500 return fmt
.hw
&& ((relevant_bind
& ~fmt
.bind
) == 0);
504 panfrost_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
505 enum pipe_compute_cap param
, void *ret
)
507 const char * const ir
= "panfrost";
509 if (!(pan_debug
& PAN_DBG_DEQP
))
512 #define RET(x) do { \
514 memcpy(ret, x, sizeof(x)); \
519 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
520 RET((uint32_t []){ 64 });
522 case PIPE_COMPUTE_CAP_IR_TARGET
:
524 sprintf(ret
, "%s", ir
);
525 return strlen(ir
) * sizeof(char);
527 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
528 RET((uint64_t []) { 3 });
530 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
531 RET(((uint64_t []) { 65535, 65535, 65535 }));
533 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
534 RET(((uint64_t []) { 1024, 1024, 64 }));
536 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
537 RET((uint64_t []) { 1024 });
539 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
540 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
542 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
543 RET((uint64_t []) { 32768 });
545 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
546 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
547 RET((uint64_t []) { 4096 });
549 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
550 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
552 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
553 RET((uint32_t []) { 800 /* MHz -- TODO */ });
555 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
556 RET((uint32_t []) { 9999 }); // TODO
558 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
559 RET((uint32_t []) { 1 }); // TODO
561 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
562 RET((uint32_t []) { 32 }); // TODO
564 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
565 RET((uint64_t []) { 1024 }); // TODO
572 panfrost_destroy_screen(struct pipe_screen
*pscreen
)
574 panfrost_close_device(pan_device(pscreen
));
575 ralloc_free(pscreen
);
579 panfrost_get_timestamp(struct pipe_screen
*_screen
)
581 return os_time_get_nano();
585 panfrost_fence_reference(struct pipe_screen
*pscreen
,
586 struct pipe_fence_handle
**ptr
,
587 struct pipe_fence_handle
*fence
)
589 struct panfrost_fence
**p
= (struct panfrost_fence
**)ptr
;
590 struct panfrost_fence
*f
= (struct panfrost_fence
*)fence
;
591 struct panfrost_fence
*old
= *p
;
593 if (pipe_reference(&(*p
)->reference
, &f
->reference
)) {
594 util_dynarray_foreach(&old
->syncfds
, int, fd
)
596 util_dynarray_fini(&old
->syncfds
);
603 panfrost_fence_finish(struct pipe_screen
*pscreen
,
604 struct pipe_context
*ctx
,
605 struct pipe_fence_handle
*fence
,
608 struct panfrost_device
*dev
= pan_device(pscreen
);
609 struct panfrost_fence
*f
= (struct panfrost_fence
*)fence
;
610 struct util_dynarray syncobjs
;
613 /* All fences were already signaled */
614 if (!util_dynarray_num_elements(&f
->syncfds
, int))
617 util_dynarray_init(&syncobjs
, NULL
);
618 util_dynarray_foreach(&f
->syncfds
, int, fd
) {
621 ret
= drmSyncobjCreate(dev
->fd
, 0, &syncobj
);
624 ret
= drmSyncobjImportSyncFile(dev
->fd
, syncobj
, *fd
);
626 util_dynarray_append(&syncobjs
, uint32_t, syncobj
);
629 uint64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
630 if (abs_timeout
== OS_TIMEOUT_INFINITE
)
631 abs_timeout
= INT64_MAX
;
633 ret
= drmSyncobjWait(dev
->fd
, util_dynarray_begin(&syncobjs
),
634 util_dynarray_num_elements(&syncobjs
, uint32_t),
635 abs_timeout
, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL
,
638 util_dynarray_foreach(&syncobjs
, uint32_t, syncobj
)
639 drmSyncobjDestroy(dev
->fd
, *syncobj
);
644 struct panfrost_fence
*
645 panfrost_fence_create(struct panfrost_context
*ctx
,
646 struct util_dynarray
*fences
)
648 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
649 struct panfrost_fence
*f
= calloc(1, sizeof(*f
));
653 util_dynarray_init(&f
->syncfds
, NULL
);
655 /* Export fences from all pending batches. */
656 util_dynarray_foreach(fences
, struct panfrost_batch_fence
*, fence
) {
659 /* The fence is already signaled, no need to export it. */
660 if ((*fence
)->signaled
)
663 drmSyncobjExportSyncFile(device
->fd
, (*fence
)->syncobj
, &fd
);
665 fprintf(stderr
, "export failed: %m\n");
668 util_dynarray_append(&f
->syncfds
, int, fd
);
671 pipe_reference_init(&f
->reference
, 1);
677 panfrost_screen_get_compiler_options(struct pipe_screen
*pscreen
,
678 enum pipe_shader_ir ir
,
679 enum pipe_shader_type shader
)
681 if (pan_device(pscreen
)->quirks
& IS_BIFROST
)
682 return &bifrost_nir_options
;
684 return &midgard_nir_options
;
688 panfrost_create_screen(int fd
, struct renderonly
*ro
)
690 pan_debug
= debug_get_option_pan_debug();
692 /* Blacklist apps known to be buggy under Panfrost */
693 const char *proc
= util_get_process_name();
694 const char *blacklist
[] = {
699 for (unsigned i
= 0; i
< ARRAY_SIZE(blacklist
); ++i
) {
700 if ((strcmp(blacklist
[i
], proc
) == 0))
704 /* Create the screen */
705 struct panfrost_screen
*screen
= rzalloc(NULL
, struct panfrost_screen
);
710 struct panfrost_device
*dev
= pan_device(&screen
->base
);
711 panfrost_open_device(screen
, fd
, dev
);
714 dev
->ro
= renderonly_dup(ro
);
716 DBG("Failed to dup renderonly object\n");
722 /* Check if we're loading against a supported GPU model. */
724 switch (dev
->gpu_id
) {
725 case 0x720: /* T720 */
726 case 0x750: /* T760 */
727 case 0x820: /* T820 */
728 case 0x860: /* T860 */
730 case 0x7093: /* G31 */
731 case 0x7212: /* G52 */
732 if (pan_debug
& PAN_DBG_BIFROST
)
737 /* Fail to load against untested models */
738 debug_printf("panfrost: Unsupported model %X", dev
->gpu_id
);
739 panfrost_destroy_screen(&(screen
->base
));
743 if (pan_debug
& (PAN_DBG_TRACE
| PAN_DBG_SYNC
))
744 pandecode_initialize(!(pan_debug
& PAN_DBG_TRACE
));
746 screen
->base
.destroy
= panfrost_destroy_screen
;
748 screen
->base
.get_name
= panfrost_get_name
;
749 screen
->base
.get_vendor
= panfrost_get_vendor
;
750 screen
->base
.get_device_vendor
= panfrost_get_device_vendor
;
751 screen
->base
.get_param
= panfrost_get_param
;
752 screen
->base
.get_shader_param
= panfrost_get_shader_param
;
753 screen
->base
.get_compute_param
= panfrost_get_compute_param
;
754 screen
->base
.get_paramf
= panfrost_get_paramf
;
755 screen
->base
.get_timestamp
= panfrost_get_timestamp
;
756 screen
->base
.is_format_supported
= panfrost_is_format_supported
;
757 screen
->base
.context_create
= panfrost_create_context
;
758 screen
->base
.get_compiler_options
= panfrost_screen_get_compiler_options
;
759 screen
->base
.fence_reference
= panfrost_fence_reference
;
760 screen
->base
.fence_finish
= panfrost_fence_finish
;
761 screen
->base
.set_damage_region
= panfrost_resource_set_damage_region
;
763 panfrost_resource_screen_init(&screen
->base
);
765 return &screen
->base
;