src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  24  * SOFTWARE.
  25  *
  26  */
  27
  28 #include "util/u_debug.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_format.h"
  31 #include "util/u_format_s3tc.h"
  32 #include "util/u_video.h"
  33 #include "util/u_screen.h"
  34 #include "util/os_time.h"
  35 #include "pipe/p_defines.h"
  36 #include "pipe/p_screen.h"
  37 #include "draw/draw_context.h"
  38 #include <xf86drm.h>
  39
  40 #include <fcntl.h>
  41
  42 #include "drm-uapi/drm_fourcc.h"
  43
  44 #include "pan_screen.h"
  45 #include "pan_resource.h"
  46 #include "pan_public.h"
  47 #include "pan_util.h"
  48 #include "pandecode/decode.h"
  49
  50 #include "pan_context.h"
  51 #include "midgard/midgard_compile.h"
  52
  53 static const struct debug_named_value debug_options[] = {
  54         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  55         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  56         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  57                 /* ^^ If Rob can do it, so can I */
  58         DEBUG_NAMED_VALUE_END
  59 };
  60
  61 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug, "PAN_MESA_DEBUG", debug_options, 0)
  62
  63 int pan_debug = 0;
  64
  65 static const char *
  66 panfrost_get_name(struct pipe_screen *screen)
  67 {
  68         return "panfrost";
  69 }
  70
  71 static const char *
  72 panfrost_get_vendor(struct pipe_screen *screen)
  73 {
  74         return "panfrost";
  75 }
  76
  77 static const char *
  78 panfrost_get_device_vendor(struct pipe_screen *screen)
  79 {
  80         return "Arm";
  81 }
  82
  83 static int
  84 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  85 {
  86         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  87         bool is_deqp = pan_debug & PAN_DBG_DEQP;
  88
  89         switch (param) {
  90         case PIPE_CAP_NPOT_TEXTURES:
  91         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  92         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  93         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  94         case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  95         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  96         case PIPE_CAP_POINT_SPRITE:
  97                 return 1;
  98
  99         case PIPE_CAP_MAX_RENDER_TARGETS:
 100                 return 1;
 101
 102         case PIPE_CAP_OCCLUSION_QUERY:
 103                 return 1;
 104         case PIPE_CAP_QUERY_TIME_ELAPSED:
 105         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 106         case PIPE_CAP_QUERY_TIMESTAMP:
 107         case PIPE_CAP_QUERY_SO_OVERFLOW:
 108                 return 0;
 109
 110         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 111         case PIPE_CAP_TEXTURE_SWIZZLE:
 112                 return 1;
 113
 114         case PIPE_CAP_TGSI_INSTANCEID:
 115         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 116                 return is_deqp ? 1 : 0;
 117
 118         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 119                 return is_deqp ? 4 : 0;
 120         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 121         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 122                 return is_deqp ? 64 : 0;
 123
 124         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 125                 return is_deqp ? 256 : 0; /* for GL3 */
 126
 127         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 128         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 129                 return is_deqp ? 140 : 120;
 130         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 131                 return is_deqp ? 300 : 120;
 132
 133         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 134                 return is_deqp ? 16 : 0;
 135
 136         case PIPE_CAP_CUBE_MAP_ARRAY:
 137                 return is_deqp;
 138
 139         /* TODO: Where does this req come from in practice? */
 140         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 141                 return 1;
 142
 143         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 144                 return 4096;
 145         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 146         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 147                 return 13;
 148
 149         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 150         case PIPE_CAP_INDEP_BLEND_ENABLE:
 151         case PIPE_CAP_INDEP_BLEND_FUNC:
 152                 return 1;
 153
 154         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 155                 /* Hardware is natively upper left */
 156                 return 0;
 157
 158         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 159         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 160         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 161         case PIPE_CAP_GENERATE_MIPMAP:
 162                 return 1;
 163
 164         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 165         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 166                 return 1;
 167
 168         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 169                 return 0xffff;
 170
 171         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 172                 return 1;
 173
 174         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 175                 return 65536;
 176
 177         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 178                 return 0;
 179
 180         case PIPE_CAP_ENDIANNESS:
 181                 return PIPE_ENDIAN_NATIVE;
 182
 183         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 184                 return 1;
 185
 186         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 187                 return -8;
 188
 189         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 190                 return 7;
 191
 192         case PIPE_CAP_VENDOR_ID:
 193         case PIPE_CAP_DEVICE_ID:
 194                 return 0xFFFFFFFF;
 195
 196         case PIPE_CAP_ACCELERATED:
 197         case PIPE_CAP_UMA:
 198         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 199         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 200         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 201         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 202                 return 1;
 203
 204         case PIPE_CAP_VIDEO_MEMORY: {
 205                 uint64_t system_memory;
 206
 207                 if (!os_get_total_physical_memory(&system_memory))
 208                         return 0;
 209
 210                 return (int)(system_memory >> 20);
 211         }
 212
 213         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 214                 return 4;
 215
 216         case PIPE_CAP_MAX_VARYINGS:
 217                 return 16;
 218
 219         default:
 220                 return u_pipe_screen_get_param_defaults(screen, param);
 221         }
 222 }
 223
 224 static int
 225 panfrost_get_shader_param(struct pipe_screen *screen,
 226                           enum pipe_shader_type shader,
 227                           enum pipe_shader_cap param)
 228 {
 229         if (shader != PIPE_SHADER_VERTEX &&
 230                         shader != PIPE_SHADER_FRAGMENT) {
 231                 return 0;
 232         }
 233
 234         /* this is probably not totally correct.. but it's a start: */
 235         switch (param) {
 236         case PIPE_SHADER_CAP_SCALAR_ISA:
 237                 return 0;
 238
 239         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 240                 return 0;
 241         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 242         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 243         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 244                 return 16384;
 245
 246         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 247                 return 1024;
 248
 249         case PIPE_SHADER_CAP_MAX_INPUTS:
 250                 return 16;
 251
 252         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 253                 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
 254
 255         case PIPE_SHADER_CAP_MAX_TEMPS:
 256                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 257
 258         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 259                 return 16 * 1024 * sizeof(float);
 260
 261         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 262                 return 16;
 263
 264         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 265                 return 0;
 266
 267         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 268                 return 1;
 269         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 270                 return 0;
 271
 272         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 273                 return 0;
 274
 275         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 276                 return 1;
 277
 278         case PIPE_SHADER_CAP_SUBROUTINES:
 279                 return 0;
 280
 281         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 282                 return 0;
 283
 284         case PIPE_SHADER_CAP_INTEGERS:
 285                 return 1;
 286
 287         case PIPE_SHADER_CAP_INT64_ATOMICS:
 288         case PIPE_SHADER_CAP_FP16:
 289         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 290         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 291         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 292         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 293         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 294                 return 0;
 295
 296         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 297         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 298                 return 16; /* XXX: How many? */
 299
 300         case PIPE_SHADER_CAP_PREFERRED_IR:
 301                 return PIPE_SHADER_IR_NIR;
 302
 303         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 304                 return 0;
 305
 306         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 307                 return 32;
 308
 309         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 310         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 311         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 312         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 313         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 314         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 315                 return 0;
 316
 317         default:
 318                 fprintf(stderr, "unknown shader param %d\n", param);
 319                 return 0;
 320         }
 321
 322         return 0;
 323 }
 324
 325 static float
 326 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 327 {
 328         switch (param) {
 329         case PIPE_CAPF_MAX_LINE_WIDTH:
 330
 331         /* fall-through */
 332         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 333                 return 255.0; /* arbitrary */
 334
 335         case PIPE_CAPF_MAX_POINT_WIDTH:
 336
 337         /* fall-through */
 338         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 339                 return 255.0; /* arbitrary */
 340
 341         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 342                 return 16.0;
 343
 344         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 345                 return 16.0; /* arbitrary */
 346
 347         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 348         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 349         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 350                 return 0.0f;
 351
 352         default:
 353                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 354                 return 0.0;
 355         }
 356 }
 357
 358 /**
 359  * Query format support for creating a texture, drawing surface, etc.
 360  * \param format  the format to test
 361  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 362  */
 363 static boolean
 364 panfrost_is_format_supported( struct pipe_screen *screen,
 365                               enum pipe_format format,
 366                               enum pipe_texture_target target,
 367                               unsigned sample_count,
 368                               unsigned storage_sample_count,
 369                               unsigned bind)
 370 {
 371         const struct util_format_description *format_desc;
 372
 373         assert(target == PIPE_BUFFER ||
 374                target == PIPE_TEXTURE_1D ||
 375                target == PIPE_TEXTURE_1D_ARRAY ||
 376                target == PIPE_TEXTURE_2D ||
 377                target == PIPE_TEXTURE_2D_ARRAY ||
 378                target == PIPE_TEXTURE_RECT ||
 379                target == PIPE_TEXTURE_3D ||
 380                target == PIPE_TEXTURE_CUBE ||
 381                target == PIPE_TEXTURE_CUBE_ARRAY);
 382
 383         format_desc = util_format_description(format);
 384
 385         if (!format_desc)
 386                 return FALSE;
 387
 388         if (sample_count > 1)
 389                 return FALSE;
 390
 391         /* Format wishlist */
 392         if (format == PIPE_FORMAT_Z24X8_UNORM || format == PIPE_FORMAT_X8Z24_UNORM)
 393                 return FALSE;
 394
 395         if (format == PIPE_FORMAT_A1B5G5R5_UNORM || format == PIPE_FORMAT_X1B5G5R5_UNORM)
 396                 return FALSE;
 397
 398         /* TODO */
 399         if (format == PIPE_FORMAT_B5G5R5A1_UNORM)
 400                 return FALSE;
 401
 402         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 403          * more alpha than they ask for */
 404         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 405         if (scanout && !util_format_is_rgba8_variant(format_desc))
 406                 return FALSE;
 407
 408         if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN &&
 409                         format_desc->layout != UTIL_FORMAT_LAYOUT_OTHER) {
 410                 /* Compressed formats not yet hooked up. */
 411                 return FALSE;
 412         }
 413
 414         return TRUE;
 415 }
 416
 417
 418 static void
 419 panfrost_destroy_screen(struct pipe_screen *pscreen)
 420 {
 421         struct panfrost_screen *screen = pan_screen(pscreen);
 422         panfrost_resource_screen_deinit(screen);
 423         ralloc_free(screen);
 424 }
 425
 426 static void
 427 panfrost_flush_frontbuffer(struct pipe_screen *_screen,
 428                            struct pipe_resource *resource,
 429                            unsigned level, unsigned layer,
 430                            void *context_private,
 431                            struct pipe_box *sub_box)
 432 {
 433         /* TODO: Display target integration */
 434 }
 435
 436 static uint64_t
 437 panfrost_get_timestamp(struct pipe_screen *_screen)
 438 {
 439         return os_time_get_nano();
 440 }
 441
 442 static void
 443 panfrost_fence_reference(struct pipe_screen *pscreen,
 444                          struct pipe_fence_handle **ptr,
 445                          struct pipe_fence_handle *fence)
 446 {
 447         panfrost_drm_fence_reference(pscreen, ptr, fence);
 448 }
 449
 450 static boolean
 451 panfrost_fence_finish(struct pipe_screen *pscreen,
 452                       struct pipe_context *ctx,
 453                       struct pipe_fence_handle *fence,
 454                       uint64_t timeout)
 455 {
 456         return panfrost_drm_fence_finish(pscreen, ctx, fence, timeout);
 457 }
 458
 459 static const void *
 460 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 461                                      enum pipe_shader_ir ir,
 462                                      enum pipe_shader_type shader)
 463 {
 464         return &midgard_nir_options;
 465 }
 466
 467 struct pipe_screen *
 468 panfrost_create_screen(int fd, struct renderonly *ro)
 469 {
 470         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 471
 472         pan_debug = debug_get_option_pan_debug();
 473
 474         if (!screen)
 475                 return NULL;
 476
 477         if (ro) {
 478                 screen->ro = renderonly_dup(ro);
 479                 if (!screen->ro) {
 480                         fprintf(stderr, "Failed to dup renderonly object\n");
 481                         free(screen);
 482                         return NULL;
 483                 }
 484         }
 485
 486         screen->fd = fd;
 487
 488         screen->gpu_id = panfrost_drm_query_gpu_version(screen);
 489
 490         /* Check if we're loading against a supported GPU model
 491          * paired with a supported CPU (differences from
 492          * armhf/aarch64 break models on incompatible CPUs at the
 493          * moment -- this is a TODO). In other words, we whitelist
 494          * RK3288, RK3399, and S912, which are verified to work. */
 495
 496         switch (screen->gpu_id) {
 497 #ifdef __LP64__
 498                 case 0x820: /* T820 */
 499                 case 0x860: /* T860 */
 500                         break;
 501 #else
 502                 case 0x750: /* T760 */
 503                         break;
 504 #endif
 505
 506                 default:
 507                         /* Fail to load against untested models */
 508                         debug_printf("panfrost: Unsupported model %X",
 509                                         screen->gpu_id);
 510                         return NULL;
 511         }
 512
 513         if (pan_debug & PAN_DBG_TRACE)
 514                 pandecode_initialize();
 515
 516         screen->base.destroy = panfrost_destroy_screen;
 517
 518         screen->base.get_name = panfrost_get_name;
 519         screen->base.get_vendor = panfrost_get_vendor;
 520         screen->base.get_device_vendor = panfrost_get_device_vendor;
 521         screen->base.get_param = panfrost_get_param;
 522         screen->base.get_shader_param = panfrost_get_shader_param;
 523         screen->base.get_paramf = panfrost_get_paramf;
 524         screen->base.get_timestamp = panfrost_get_timestamp;
 525         screen->base.is_format_supported = panfrost_is_format_supported;
 526         screen->base.context_create = panfrost_create_context;
 527         screen->base.flush_frontbuffer = panfrost_flush_frontbuffer;
 528         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 529         screen->base.fence_reference = panfrost_fence_reference;
 530         screen->base.fence_finish = panfrost_fence_finish;
 531
 532         screen->last_fragment_flushed = true;
 533         screen->last_job = NULL;
 534
 535         panfrost_resource_screen_init(screen);
 536
 537         return &screen->base;
 538 }