src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32 #include "util/format/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "util/u_process.h"
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_screen.h"
  39 #include "draw/draw_context.h"
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44 #include "drm-uapi/panfrost_drm.h"
  45
  46 #include "pan_bo.h"
  47 #include "pan_screen.h"
  48 #include "pan_resource.h"
  49 #include "pan_public.h"
  50 #include "pan_util.h"
  51 #include "pandecode/decode.h"
  52
  53 #include "pan_context.h"
  54 #include "midgard/midgard_compile.h"
  55 #include "bifrost/bifrost_compile.h"
  56 #include "panfrost-quirks.h"
  57
  58 static const struct debug_named_value debug_options[] = {
  59         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  60         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  61         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  62         {"afbc",      PAN_DBG_AFBC,     "Enable non-conformant AFBC impl"},
  63         {"sync",      PAN_DBG_SYNC,     "Wait for each job's completion and check for any GPU fault"},
  64         {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
  65         {"gles3",     PAN_DBG_GLES3,    "Enable experimental GLES3 implementation"},
  66         DEBUG_NAMED_VALUE_END
  67 };
  68
  69 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug, "PAN_MESA_DEBUG", debug_options, 0)
  70
  71 int pan_debug = 0;
  72
  73 static const char *
  74 panfrost_get_name(struct pipe_screen *screen)
  75 {
  76         return panfrost_model_name(pan_device(screen)->gpu_id);
  77 }
  78
  79 static const char *
  80 panfrost_get_vendor(struct pipe_screen *screen)
  81 {
  82         return "Panfrost";
  83 }
  84
  85 static const char *
  86 panfrost_get_device_vendor(struct pipe_screen *screen)
  87 {
  88         return "Arm";
  89 }
  90
  91 static int
  92 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  93 {
  94         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  95         bool is_deqp = pan_debug & PAN_DBG_DEQP;
  96
  97         /* Our GLES3 implementation is WIP */
  98         bool is_gles3 = pan_debug & PAN_DBG_GLES3;
  99         is_gles3 |= is_deqp;
 100
 101         switch (param) {
 102         case PIPE_CAP_NPOT_TEXTURES:
 103         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 104         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 105         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 106         case PIPE_CAP_VERTEX_SHADER_SATURATE:
 107         case PIPE_CAP_POINT_SPRITE:
 108                 return 1;
 109
 110         case PIPE_CAP_MAX_RENDER_TARGETS:
 111                 return is_gles3 ? 4 : 1;
 112
 113         /* Throttling frames breaks pipelining */
 114         case PIPE_CAP_THROTTLE:
 115                 return 0;
 116
 117         case PIPE_CAP_OCCLUSION_QUERY:
 118                 return 1;
 119         case PIPE_CAP_QUERY_TIME_ELAPSED:
 120         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 121         case PIPE_CAP_QUERY_TIMESTAMP:
 122         case PIPE_CAP_QUERY_SO_OVERFLOW:
 123                 return 0;
 124
 125         case PIPE_CAP_TEXTURE_SWIZZLE:
 126                 return 1;
 127
 128         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 129         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 130                 return 1;
 131
 132         case PIPE_CAP_TGSI_INSTANCEID:
 133         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 134         case PIPE_CAP_PRIMITIVE_RESTART:
 135                 return 1;
 136
 137         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 138                 return is_gles3 ? 4 : 0;
 139         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 140         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 141                 return is_gles3 ? 64 : 0;
 142         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 143                 return 1;
 144
 145         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 146                 return 256;
 147
 148         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 149         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 150                 return is_gles3 ? 140 : 120;
 151         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 152                 return is_gles3 ? 300 : 120;
 153
 154         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 155                 return 16;
 156
 157                 return is_deqp;
 158
 159         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 160                 return is_gles3;
 161
 162         /* For faking GLES 3.1 for dEQP-GLES31 */
 163         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 164         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 165         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 166         case PIPE_CAP_CUBE_MAP_ARRAY:
 167                 return is_deqp;
 168
 169         /* For faking compute shaders */
 170         case PIPE_CAP_COMPUTE:
 171                 return is_deqp;
 172
 173         /* TODO: Where does this req come from in practice? */
 174         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 175                 return 1;
 176
 177         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 178                 return 4096;
 179         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 180         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 181                 return 13;
 182
 183         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 184         case PIPE_CAP_INDEP_BLEND_ENABLE:
 185         case PIPE_CAP_INDEP_BLEND_FUNC:
 186                 return 1;
 187
 188         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 189                 /* Hardware is natively upper left */
 190                 return 0;
 191
 192         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 193         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 194         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 195         case PIPE_CAP_GENERATE_MIPMAP:
 196                 return 1;
 197
 198         /* We would prefer varyings */
 199         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 200         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 201                 return 0;
 202
 203         /* I really don't want to set this CAP but let's not swim against the
 204          * tide.. */
 205         case PIPE_CAP_TGSI_TEXCOORD:
 206                 return 1;
 207
 208         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 209         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 210                 return 1;
 211
 212         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 213                 return 0xffff;
 214
 215         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 216                 return 1;
 217
 218         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 219                 return 65536;
 220
 221         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 222                 return 0;
 223
 224         case PIPE_CAP_ENDIANNESS:
 225                 return PIPE_ENDIAN_NATIVE;
 226
 227         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 228                 return 1;
 229
 230         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 231                 return -8;
 232
 233         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 234                 return 7;
 235
 236         case PIPE_CAP_VENDOR_ID:
 237         case PIPE_CAP_DEVICE_ID:
 238                 return 0xFFFFFFFF;
 239
 240         case PIPE_CAP_ACCELERATED:
 241         case PIPE_CAP_UMA:
 242         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 243         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 244         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 245         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 246                 return 1;
 247
 248         case PIPE_CAP_VIDEO_MEMORY: {
 249                 uint64_t system_memory;
 250
 251                 if (!os_get_total_physical_memory(&system_memory))
 252                         return 0;
 253
 254                 return (int)(system_memory >> 20);
 255         }
 256
 257         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 258                 return 1;
 259
 260         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 261                 return 4;
 262
 263         case PIPE_CAP_MAX_VARYINGS:
 264                 return 16;
 265
 266         case PIPE_CAP_ALPHA_TEST:
 267         case PIPE_CAP_FLATSHADE:
 268         case PIPE_CAP_TWO_SIDED_COLOR:
 269         case PIPE_CAP_CLIP_PLANES:
 270                 return 0;
 271
 272         case PIPE_CAP_PACKED_STREAM_OUTPUT:
 273                 return 0;
 274
 275         case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
 276         case PIPE_CAP_PSIZ_CLAMPED:
 277                 return 1;
 278
 279         default:
 280                 return u_pipe_screen_get_param_defaults(screen, param);
 281         }
 282 }
 283
 284 static int
 285 panfrost_get_shader_param(struct pipe_screen *screen,
 286                           enum pipe_shader_type shader,
 287                           enum pipe_shader_cap param)
 288 {
 289         bool is_deqp = pan_debug & PAN_DBG_DEQP;
 290         struct panfrost_device *dev = pan_device(screen);
 291
 292         if (shader != PIPE_SHADER_VERTEX &&
 293             shader != PIPE_SHADER_FRAGMENT &&
 294             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 295                 return 0;
 296
 297         /* this is probably not totally correct.. but it's a start: */
 298         switch (param) {
 299         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 300         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 301         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 302         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 303                 return 16384;
 304
 305         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 306                 return 1024;
 307
 308         case PIPE_SHADER_CAP_MAX_INPUTS:
 309                 return 16;
 310
 311         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 312                 return shader == PIPE_SHADER_FRAGMENT ? 4 : 16;
 313
 314         case PIPE_SHADER_CAP_MAX_TEMPS:
 315                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 316
 317         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 318                 return 16 * 1024 * sizeof(float);
 319
 320         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 321                 return PAN_MAX_CONST_BUFFERS;
 322
 323         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 324                 return 0;
 325
 326         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 327                 return 1;
 328         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 329                 return 0;
 330
 331         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 332                 return 0;
 333
 334         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 335                 return 1;
 336
 337         case PIPE_SHADER_CAP_SUBROUTINES:
 338                 return 0;
 339
 340         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 341                 return 0;
 342
 343         case PIPE_SHADER_CAP_INTEGERS:
 344                 return 1;
 345
 346         case PIPE_SHADER_CAP_FP16:
 347                 return !(dev->quirks & MIDGARD_BROKEN_FP16);
 348
 349         case PIPE_SHADER_CAP_INT64_ATOMICS:
 350         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 351         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 352         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 353         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 354         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 355                 return 0;
 356
 357         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 358         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 359                 return 16; /* XXX: How many? */
 360
 361         case PIPE_SHADER_CAP_PREFERRED_IR:
 362                 return PIPE_SHADER_IR_NIR;
 363
 364         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 365                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
 366
 367         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 368                 return 32;
 369
 370         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 371         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 372                 return is_deqp ? 8 : 0;
 373         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 374         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 375                 return 0;
 376
 377         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 378         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 379                 return 0;
 380
 381         default:
 382                 DBG("unknown shader param %d\n", param);
 383                 return 0;
 384         }
 385
 386         return 0;
 387 }
 388
 389 static float
 390 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 391 {
 392         switch (param) {
 393         case PIPE_CAPF_MAX_LINE_WIDTH:
 394
 395         /* fall-through */
 396         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 397                 return 255.0; /* arbitrary */
 398
 399         case PIPE_CAPF_MAX_POINT_WIDTH:
 400
 401         /* fall-through */
 402         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 403                 return 1024.0;
 404
 405         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 406                 return 16.0;
 407
 408         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 409                 return 16.0; /* arbitrary */
 410
 411         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 412         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 413         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 414                 return 0.0f;
 415
 416         default:
 417                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 418                 return 0.0;
 419         }
 420 }
 421
 422 /**
 423  * Query format support for creating a texture, drawing surface, etc.
 424  * \param format  the format to test
 425  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 426  */
 427 static bool
 428 panfrost_is_format_supported( struct pipe_screen *screen,
 429                               enum pipe_format format,
 430                               enum pipe_texture_target target,
 431                               unsigned sample_count,
 432                               unsigned storage_sample_count,
 433                               unsigned bind)
 434 {
 435         const struct util_format_description *format_desc;
 436
 437         assert(target == PIPE_BUFFER ||
 438                target == PIPE_TEXTURE_1D ||
 439                target == PIPE_TEXTURE_1D_ARRAY ||
 440                target == PIPE_TEXTURE_2D ||
 441                target == PIPE_TEXTURE_2D_ARRAY ||
 442                target == PIPE_TEXTURE_RECT ||
 443                target == PIPE_TEXTURE_3D ||
 444                target == PIPE_TEXTURE_CUBE ||
 445                target == PIPE_TEXTURE_CUBE_ARRAY);
 446
 447         format_desc = util_format_description(format);
 448
 449         if (!format_desc)
 450                 return false;
 451
 452         /* MSAA 4x supported, but no more. Technically some revisions of the
 453          * hardware can go up to 16x but we don't support higher modes yet. */
 454
 455         if (sample_count > 1 && !(pan_debug & PAN_DBG_DEQP))
 456                 return false;
 457
 458         if (sample_count > 4)
 459                 return false;
 460
 461         if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
 462                 return false;
 463
 464         /* Format wishlist */
 465         if (format == PIPE_FORMAT_X8Z24_UNORM)
 466                 return false;
 467
 468         if (format == PIPE_FORMAT_A1B5G5R5_UNORM ||
 469             format == PIPE_FORMAT_X1B5G5R5_UNORM ||
 470             format == PIPE_FORMAT_B2G3R3_UNORM)
 471                 return false;
 472
 473         /* TODO */
 474         if (format == PIPE_FORMAT_B5G5R5A1_UNORM)
 475                 return FALSE;
 476
 477         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 478          * more alpha than they ask for */
 479
 480         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 481         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 482
 483         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 484                 return false;
 485
 486         switch (format_desc->layout) {
 487                 case UTIL_FORMAT_LAYOUT_PLAIN:
 488                 case UTIL_FORMAT_LAYOUT_OTHER:
 489                         break;
 490                 case UTIL_FORMAT_LAYOUT_ETC:
 491                 case UTIL_FORMAT_LAYOUT_ASTC:
 492                         return true;
 493                 default:
 494                         return false;
 495         }
 496
 497         if (format_desc->channel[0].size > 32)
 498             return false;
 499
 500         /* Internally, formats that are depth/stencil renderable are limited.
 501          *
 502          * In particular: Z16, Z24, Z24S8, S8 are all identical from the GPU
 503          * rendering perspective. That is, we render to Z24S8 (which we can
 504          * AFBC compress), ignore the different when texturing (who cares?),
 505          * and then in the off-chance there's a CPU read we blit back to
 506          * staging.
 507          *
 508          * ...alternatively, we can make the state tracker deal with that. */
 509
 510         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 511                 switch (format) {
 512                         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 513                         case PIPE_FORMAT_Z24X8_UNORM:
 514                         case PIPE_FORMAT_Z32_UNORM:
 515                         case PIPE_FORMAT_Z32_FLOAT:
 516                         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 517                                 return true;
 518
 519                         default:
 520                                 return false;
 521                 }
 522         }
 523
 524         return true;
 525 }
 526
 527 static int
 528 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 529                 enum pipe_compute_cap param, void *ret)
 530 {
 531         const char * const ir = "panfrost";
 532
 533         if (!(pan_debug & PAN_DBG_DEQP))
 534                 return 0;
 535
 536 #define RET(x) do {                  \
 537    if (ret)                          \
 538       memcpy(ret, x, sizeof(x));     \
 539    return sizeof(x);                 \
 540 } while (0)
 541
 542         switch (param) {
 543         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 544                 RET((uint32_t []){ 64 });
 545
 546         case PIPE_COMPUTE_CAP_IR_TARGET:
 547                 if (ret)
 548                         sprintf(ret, "%s", ir);
 549                 return strlen(ir) * sizeof(char);
 550
 551         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 552                 RET((uint64_t []) { 3 });
 553
 554         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 555                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 556
 557         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 558                 RET(((uint64_t []) { 1024, 1024, 64 }));
 559
 560         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 561                 RET((uint64_t []) { 1024 });
 562
 563         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 564                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 565
 566         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 567                 RET((uint64_t []) { 32768 });
 568
 569         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 570         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 571                 RET((uint64_t []) { 4096 });
 572
 573         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 574                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 575
 576         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 577                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 578
 579         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 580                 RET((uint32_t []) { 9999 });  // TODO
 581
 582         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 583                 RET((uint32_t []) { 1 }); // TODO
 584
 585         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 586                 RET((uint32_t []) { 32 });  // TODO
 587
 588         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 589                 RET((uint64_t []) { 1024 }); // TODO
 590         }
 591
 592         return 0;
 593 }
 594
 595 static void
 596 panfrost_destroy_screen(struct pipe_screen *pscreen)
 597 {
 598         panfrost_close_device(pan_device(pscreen));
 599         ralloc_free(pscreen);
 600 }
 601
 602 static uint64_t
 603 panfrost_get_timestamp(struct pipe_screen *_screen)
 604 {
 605         return os_time_get_nano();
 606 }
 607
 608 static void
 609 panfrost_fence_reference(struct pipe_screen *pscreen,
 610                          struct pipe_fence_handle **ptr,
 611                          struct pipe_fence_handle *fence)
 612 {
 613         struct panfrost_fence **p = (struct panfrost_fence **)ptr;
 614         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 615         struct panfrost_fence *old = *p;
 616
 617         if (pipe_reference(&(*p)->reference, &f->reference)) {
 618                 util_dynarray_foreach(&old->syncfds, int, fd)
 619                         close(*fd);
 620                 util_dynarray_fini(&old->syncfds);
 621                 free(old);
 622         }
 623         *p = f;
 624 }
 625
 626 static bool
 627 panfrost_fence_finish(struct pipe_screen *pscreen,
 628                       struct pipe_context *ctx,
 629                       struct pipe_fence_handle *fence,
 630                       uint64_t timeout)
 631 {
 632         struct panfrost_device *dev = pan_device(pscreen);
 633         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 634         struct util_dynarray syncobjs;
 635         int ret;
 636
 637         /* All fences were already signaled */
 638         if (!util_dynarray_num_elements(&f->syncfds, int))
 639                 return true;
 640
 641         util_dynarray_init(&syncobjs, NULL);
 642         util_dynarray_foreach(&f->syncfds, int, fd) {
 643                 uint32_t syncobj;
 644
 645                 ret = drmSyncobjCreate(dev->fd, 0, &syncobj);
 646                 assert(!ret);
 647
 648                 ret = drmSyncobjImportSyncFile(dev->fd, syncobj, *fd);
 649                 assert(!ret);
 650                 util_dynarray_append(&syncobjs, uint32_t, syncobj);
 651         }
 652
 653         uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 654         if (abs_timeout == OS_TIMEOUT_INFINITE)
 655                 abs_timeout = INT64_MAX;
 656
 657         ret = drmSyncobjWait(dev->fd, util_dynarray_begin(&syncobjs),
 658                              util_dynarray_num_elements(&syncobjs, uint32_t),
 659                              abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
 660                              NULL);
 661
 662         util_dynarray_foreach(&syncobjs, uint32_t, syncobj)
 663                 drmSyncobjDestroy(dev->fd, *syncobj);
 664
 665         return ret >= 0;
 666 }
 667
 668 struct panfrost_fence *
 669 panfrost_fence_create(struct panfrost_context *ctx,
 670                       struct util_dynarray *fences)
 671 {
 672         struct panfrost_device *device = pan_device(ctx->base.screen);
 673         struct panfrost_fence *f = calloc(1, sizeof(*f));
 674         if (!f)
 675                 return NULL;
 676
 677         util_dynarray_init(&f->syncfds, NULL);
 678
 679         /* Export fences from all pending batches. */
 680         util_dynarray_foreach(fences, struct panfrost_batch_fence *, fence) {
 681                 int fd = -1;
 682
 683                 /* The fence is already signaled, no need to export it. */
 684                 if ((*fence)->signaled)
 685                         continue;
 686
 687                 drmSyncobjExportSyncFile(device->fd, (*fence)->syncobj, &fd);
 688                 if (fd == -1)
 689                         fprintf(stderr, "export failed: %m\n");
 690
 691                 assert(fd != -1);
 692                 util_dynarray_append(&f->syncfds, int, fd);
 693         }
 694
 695         pipe_reference_init(&f->reference, 1);
 696
 697         return f;
 698 }
 699
 700 static const void *
 701 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 702                                      enum pipe_shader_ir ir,
 703                                      enum pipe_shader_type shader)
 704 {
 705         if (pan_device(pscreen)->quirks & IS_BIFROST)
 706                 return &bifrost_nir_options;
 707         else
 708                 return &midgard_nir_options;
 709 }
 710
 711 struct pipe_screen *
 712 panfrost_create_screen(int fd, struct renderonly *ro)
 713 {
 714         pan_debug = debug_get_option_pan_debug();
 715
 716         /* Blacklist apps known to be buggy under Panfrost */
 717         const char *proc = util_get_process_name();
 718         const char *blacklist[] = {
 719                 "chromium",
 720                 "chrome",
 721         };
 722
 723         for (unsigned i = 0; i < ARRAY_SIZE(blacklist); ++i) {
 724                 if ((strcmp(blacklist[i], proc) == 0))
 725                         return NULL;
 726         }
 727
 728         /* Create the screen */
 729         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 730
 731         if (!screen)
 732                 return NULL;
 733
 734         struct panfrost_device *dev = pan_device(&screen->base);
 735         panfrost_open_device(screen, fd, dev);
 736
 737         if (ro) {
 738                 dev->ro = renderonly_dup(ro);
 739                 if (!dev->ro) {
 740                         DBG("Failed to dup renderonly object\n");
 741                         free(screen);
 742                         return NULL;
 743                 }
 744         }
 745
 746         /* Check if we're loading against a supported GPU model. */
 747
 748         switch (dev->gpu_id) {
 749         case 0x720: /* T720 */
 750         case 0x750: /* T760 */
 751         case 0x820: /* T820 */
 752         case 0x860: /* T860 */
 753                 break;
 754         default:
 755                 /* Fail to load against untested models */
 756                 debug_printf("panfrost: Unsupported model %X", dev->gpu_id);
 757                 panfrost_destroy_screen(&(screen->base));
 758                 return NULL;
 759         }
 760
 761         if (pan_debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
 762                 pandecode_initialize(!(pan_debug & PAN_DBG_TRACE));
 763
 764         screen->base.destroy = panfrost_destroy_screen;
 765
 766         screen->base.get_name = panfrost_get_name;
 767         screen->base.get_vendor = panfrost_get_vendor;
 768         screen->base.get_device_vendor = panfrost_get_device_vendor;
 769         screen->base.get_param = panfrost_get_param;
 770         screen->base.get_shader_param = panfrost_get_shader_param;
 771         screen->base.get_compute_param = panfrost_get_compute_param;
 772         screen->base.get_paramf = panfrost_get_paramf;
 773         screen->base.get_timestamp = panfrost_get_timestamp;
 774         screen->base.is_format_supported = panfrost_is_format_supported;
 775         screen->base.context_create = panfrost_create_context;
 776         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 777         screen->base.fence_reference = panfrost_fence_reference;
 778         screen->base.fence_finish = panfrost_fence_finish;
 779         screen->base.set_damage_region = panfrost_resource_set_damage_region;
 780
 781         panfrost_resource_screen_init(&screen->base);
 782
 783         return &screen->base;
 784 }