src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32 #include "util/format/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "util/u_process.h"
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_screen.h"
  39 #include "draw/draw_context.h"
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44 #include "drm-uapi/panfrost_drm.h"
  45
  46 #include "pan_bo.h"
  47 #include "pan_screen.h"
  48 #include "pan_resource.h"
  49 #include "pan_public.h"
  50 #include "pan_util.h"
  51 #include "pandecode/decode.h"
  52
  53 #include "pan_context.h"
  54 #include "midgard/midgard_compile.h"
  55 #include "bifrost/bifrost_compile.h"
  56 #include "panfrost-quirks.h"
  57
  58 static const struct debug_named_value debug_options[] = {
  59         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  60         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  61         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  62         {"afbc",      PAN_DBG_AFBC,     "Enable non-conformant AFBC impl"},
  63         {"sync",      PAN_DBG_SYNC,     "Wait for each job's completion and check for any GPU fault"},
  64         {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
  65         {"gles3",     PAN_DBG_GLES3,    "Enable experimental GLES3 implementation"},
  66         {"fp16",     PAN_DBG_FP16,     "Enable buggy experimental (don't use!) fp16"},
  67         {"bifrost",   PAN_DBG_BIFROST, "Enable experimental Mali G31 and G52 support"},
  68         DEBUG_NAMED_VALUE_END
  69 };
  70
  71 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug, "PAN_MESA_DEBUG", debug_options, 0)
  72
  73 int pan_debug = 0;
  74
  75 static const char *
  76 panfrost_get_name(struct pipe_screen *screen)
  77 {
  78         return panfrost_model_name(pan_device(screen)->gpu_id);
  79 }
  80
  81 static const char *
  82 panfrost_get_vendor(struct pipe_screen *screen)
  83 {
  84         return "Panfrost";
  85 }
  86
  87 static const char *
  88 panfrost_get_device_vendor(struct pipe_screen *screen)
  89 {
  90         return "Arm";
  91 }
  92
  93 static int
  94 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  95 {
  96         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  97         bool is_deqp = pan_debug & PAN_DBG_DEQP;
  98         struct panfrost_device *dev = pan_device(screen);
  99
 100         /* Our GLES3 implementation is WIP */
 101         bool is_gles3 = pan_debug & PAN_DBG_GLES3;
 102         is_gles3 |= is_deqp;
 103
 104         switch (param) {
 105         case PIPE_CAP_NPOT_TEXTURES:
 106         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 107         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 108         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 109         case PIPE_CAP_VERTEX_SHADER_SATURATE:
 110         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 111         case PIPE_CAP_POINT_SPRITE:
 112                 return 1;
 113
 114         case PIPE_CAP_MAX_RENDER_TARGETS:
 115                 return is_gles3 ? 4 : 1;
 116
 117         /* Throttling frames breaks pipelining */
 118         case PIPE_CAP_THROTTLE:
 119                 return 0;
 120
 121         case PIPE_CAP_OCCLUSION_QUERY:
 122                 return 1;
 123         case PIPE_CAP_QUERY_TIME_ELAPSED:
 124         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 125         case PIPE_CAP_QUERY_TIMESTAMP:
 126         case PIPE_CAP_QUERY_SO_OVERFLOW:
 127                 return 0;
 128
 129         case PIPE_CAP_TEXTURE_SWIZZLE:
 130                 return 1;
 131
 132         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 133         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 134                 return 1;
 135
 136         case PIPE_CAP_TGSI_INSTANCEID:
 137         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 138         case PIPE_CAP_PRIMITIVE_RESTART:
 139                 return 1;
 140
 141         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 142                 return is_gles3 ? 4 : 0;
 143         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 144         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 145                 return is_gles3 ? 64 : 0;
 146         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 147                 return 1;
 148
 149         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 150                 return 256;
 151
 152         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 153         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 154                 return is_gles3 ? 140 : 120;
 155         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 156                 return is_gles3 ? 300 : 120;
 157
 158         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 159                 return 16;
 160
 161         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 162                 return is_gles3;
 163
 164         /* For faking GLES 3.1 for dEQP-GLES31 */
 165         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 166         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 167         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 168         case PIPE_CAP_CUBE_MAP_ARRAY:
 169                 return is_deqp;
 170
 171         /* For faking compute shaders */
 172         case PIPE_CAP_COMPUTE:
 173                 return is_deqp;
 174
 175         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 176                 return 4096;
 177         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 178         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 179                 return 13;
 180
 181         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 182         case PIPE_CAP_INDEP_BLEND_ENABLE:
 183         case PIPE_CAP_INDEP_BLEND_FUNC:
 184                 return 1;
 185
 186         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 187                 /* Hardware is natively upper left */
 188                 return 0;
 189
 190         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 191         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 192         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 193         case PIPE_CAP_GENERATE_MIPMAP:
 194                 return 1;
 195
 196         /* We would prefer varyings on Midgard, but proper sysvals on Bifrost */
 197         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 198         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 199         case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
 200                 return dev->quirks & IS_BIFROST;
 201
 202         /* I really don't want to set this CAP but let's not swim against the
 203          * tide.. */
 204         case PIPE_CAP_TGSI_TEXCOORD:
 205                 return 1;
 206
 207         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 208         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 209                 return 1;
 210
 211         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 212                 return 0xffff;
 213
 214         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 215                 return 1;
 216
 217         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 218                 return 65536;
 219
 220         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 221                 return 0;
 222
 223         case PIPE_CAP_ENDIANNESS:
 224                 return PIPE_ENDIAN_NATIVE;
 225
 226         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 227                 return 1;
 228
 229         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 230                 return -8;
 231
 232         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 233                 return 7;
 234
 235         case PIPE_CAP_VENDOR_ID:
 236         case PIPE_CAP_DEVICE_ID:
 237                 return 0xFFFFFFFF;
 238
 239         case PIPE_CAP_ACCELERATED:
 240         case PIPE_CAP_UMA:
 241         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 242         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 243         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 244         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 245                 return 1;
 246
 247         case PIPE_CAP_VIDEO_MEMORY: {
 248                 uint64_t system_memory;
 249
 250                 if (!os_get_total_physical_memory(&system_memory))
 251                         return 0;
 252
 253                 return (int)(system_memory >> 20);
 254         }
 255
 256         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 257                 return 1;
 258
 259         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 260                 return 4;
 261
 262         case PIPE_CAP_MAX_VARYINGS:
 263                 return 16;
 264
 265         case PIPE_CAP_ALPHA_TEST:
 266         case PIPE_CAP_FLATSHADE:
 267         case PIPE_CAP_TWO_SIDED_COLOR:
 268         case PIPE_CAP_CLIP_PLANES:
 269                 return 0;
 270
 271         case PIPE_CAP_PACKED_STREAM_OUTPUT:
 272                 return 0;
 273
 274         case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
 275         case PIPE_CAP_PSIZ_CLAMPED:
 276                 return 1;
 277
 278         default:
 279                 return u_pipe_screen_get_param_defaults(screen, param);
 280         }
 281 }
 282
 283 static int
 284 panfrost_get_shader_param(struct pipe_screen *screen,
 285                           enum pipe_shader_type shader,
 286                           enum pipe_shader_cap param)
 287 {
 288         bool is_deqp = pan_debug & PAN_DBG_DEQP;
 289         bool is_fp16 = pan_debug & PAN_DBG_FP16;
 290         struct panfrost_device *dev = pan_device(screen);
 291
 292         if (shader != PIPE_SHADER_VERTEX &&
 293             shader != PIPE_SHADER_FRAGMENT &&
 294             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 295                 return 0;
 296
 297         /* this is probably not totally correct.. but it's a start: */
 298         switch (param) {
 299         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 300         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 301         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 302         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 303                 return 16384;
 304
 305         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 306                 return 1024;
 307
 308         case PIPE_SHADER_CAP_MAX_INPUTS:
 309                 return 16;
 310
 311         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 312                 return shader == PIPE_SHADER_FRAGMENT ? 4 : 16;
 313
 314         case PIPE_SHADER_CAP_MAX_TEMPS:
 315                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 316
 317         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 318                 return 16 * 1024 * sizeof(float);
 319
 320         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 321                 return PAN_MAX_CONST_BUFFERS;
 322
 323         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 324                 return 0;
 325
 326         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 327                 return 1;
 328         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 329                 return 0;
 330
 331         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 332                 return 0;
 333
 334         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 335                 return 1;
 336
 337         case PIPE_SHADER_CAP_SUBROUTINES:
 338                 return 0;
 339
 340         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 341                 return 0;
 342
 343         case PIPE_SHADER_CAP_INTEGERS:
 344                 return 1;
 345
 346         case PIPE_SHADER_CAP_FP16:
 347                 return !(dev->quirks & MIDGARD_BROKEN_FP16) || is_fp16;
 348
 349         case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 350         case PIPE_SHADER_CAP_INT16:
 351         case PIPE_SHADER_CAP_INT64_ATOMICS:
 352         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 353         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 354         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 355         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 356         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 357                 return 0;
 358
 359         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 360         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 361                 return 16; /* XXX: How many? */
 362
 363         case PIPE_SHADER_CAP_PREFERRED_IR:
 364                 return PIPE_SHADER_IR_NIR;
 365
 366         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 367                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
 368
 369         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 370                 return 32;
 371
 372         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 373         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 374                 return is_deqp ? 8 : 0;
 375         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 376         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 377                 return 0;
 378
 379         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 380         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 381                 return 0;
 382
 383         default:
 384                 DBG("unknown shader param %d\n", param);
 385                 return 0;
 386         }
 387
 388         return 0;
 389 }
 390
 391 static float
 392 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 393 {
 394         switch (param) {
 395         case PIPE_CAPF_MAX_LINE_WIDTH:
 396
 397         /* fall-through */
 398         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 399                 return 255.0; /* arbitrary */
 400
 401         case PIPE_CAPF_MAX_POINT_WIDTH:
 402
 403         /* fall-through */
 404         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 405                 return 1024.0;
 406
 407         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 408                 return 16.0;
 409
 410         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 411                 return 16.0; /* arbitrary */
 412
 413         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 414         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 415         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 416                 return 0.0f;
 417
 418         default:
 419                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 420                 return 0.0;
 421         }
 422 }
 423
 424 /**
 425  * Query format support for creating a texture, drawing surface, etc.
 426  * \param format  the format to test
 427  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 428  */
 429 static bool
 430 panfrost_is_format_supported( struct pipe_screen *screen,
 431                               enum pipe_format format,
 432                               enum pipe_texture_target target,
 433                               unsigned sample_count,
 434                               unsigned storage_sample_count,
 435                               unsigned bind)
 436 {
 437         const struct util_format_description *format_desc;
 438
 439         assert(target == PIPE_BUFFER ||
 440                target == PIPE_TEXTURE_1D ||
 441                target == PIPE_TEXTURE_1D_ARRAY ||
 442                target == PIPE_TEXTURE_2D ||
 443                target == PIPE_TEXTURE_2D_ARRAY ||
 444                target == PIPE_TEXTURE_RECT ||
 445                target == PIPE_TEXTURE_3D ||
 446                target == PIPE_TEXTURE_CUBE ||
 447                target == PIPE_TEXTURE_CUBE_ARRAY);
 448
 449         format_desc = util_format_description(format);
 450
 451         if (!format_desc)
 452                 return false;
 453
 454         /* MSAA 4x supported, but no more. Technically some revisions of the
 455          * hardware can go up to 16x but we don't support higher modes yet. */
 456
 457         if (sample_count > 1 && !(pan_debug & PAN_DBG_DEQP))
 458                 return false;
 459
 460         if (sample_count > 4)
 461                 return false;
 462
 463         if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
 464                 return false;
 465
 466         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 467          * more alpha than they ask for */
 468
 469         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 470         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 471
 472         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 473                 return false;
 474
 475         /* Check we support the format with the given bind */
 476
 477         unsigned relevant_bind = bind &
 478                 ( PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET
 479                 | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_SAMPLER_VIEW);
 480
 481         struct panfrost_format fmt = panfrost_pipe_format_table[format];
 482         return fmt.hw && ((relevant_bind & ~fmt.bind) == 0);
 483 }
 484
 485 static int
 486 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 487                 enum pipe_compute_cap param, void *ret)
 488 {
 489         const char * const ir = "panfrost";
 490
 491         if (!(pan_debug & PAN_DBG_DEQP))
 492                 return 0;
 493
 494 #define RET(x) do {                  \
 495    if (ret)                          \
 496       memcpy(ret, x, sizeof(x));     \
 497    return sizeof(x);                 \
 498 } while (0)
 499
 500         switch (param) {
 501         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 502                 RET((uint32_t []){ 64 });
 503
 504         case PIPE_COMPUTE_CAP_IR_TARGET:
 505                 if (ret)
 506                         sprintf(ret, "%s", ir);
 507                 return strlen(ir) * sizeof(char);
 508
 509         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 510                 RET((uint64_t []) { 3 });
 511
 512         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 513                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 514
 515         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 516                 RET(((uint64_t []) { 1024, 1024, 64 }));
 517
 518         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 519                 RET((uint64_t []) { 1024 });
 520
 521         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 522                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 523
 524         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 525                 RET((uint64_t []) { 32768 });
 526
 527         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 528         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 529                 RET((uint64_t []) { 4096 });
 530
 531         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 532                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 533
 534         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 535                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 536
 537         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 538                 RET((uint32_t []) { 9999 });  // TODO
 539
 540         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 541                 RET((uint32_t []) { 1 }); // TODO
 542
 543         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 544                 RET((uint32_t []) { 32 });  // TODO
 545
 546         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 547                 RET((uint64_t []) { 1024 }); // TODO
 548         }
 549
 550         return 0;
 551 }
 552
 553 static void
 554 panfrost_destroy_screen(struct pipe_screen *pscreen)
 555 {
 556         panfrost_close_device(pan_device(pscreen));
 557         ralloc_free(pscreen);
 558 }
 559
 560 static uint64_t
 561 panfrost_get_timestamp(struct pipe_screen *_screen)
 562 {
 563         return os_time_get_nano();
 564 }
 565
 566 static void
 567 panfrost_fence_reference(struct pipe_screen *pscreen,
 568                          struct pipe_fence_handle **ptr,
 569                          struct pipe_fence_handle *fence)
 570 {
 571         struct panfrost_fence **p = (struct panfrost_fence **)ptr;
 572         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 573         struct panfrost_fence *old = *p;
 574
 575         if (pipe_reference(&(*p)->reference, &f->reference)) {
 576                 util_dynarray_foreach(&old->syncfds, int, fd)
 577                         close(*fd);
 578                 util_dynarray_fini(&old->syncfds);
 579                 free(old);
 580         }
 581         *p = f;
 582 }
 583
 584 static bool
 585 panfrost_fence_finish(struct pipe_screen *pscreen,
 586                       struct pipe_context *ctx,
 587                       struct pipe_fence_handle *fence,
 588                       uint64_t timeout)
 589 {
 590         struct panfrost_device *dev = pan_device(pscreen);
 591         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 592         struct util_dynarray syncobjs;
 593         int ret;
 594
 595         /* All fences were already signaled */
 596         if (!util_dynarray_num_elements(&f->syncfds, int))
 597                 return true;
 598
 599         util_dynarray_init(&syncobjs, NULL);
 600         util_dynarray_foreach(&f->syncfds, int, fd) {
 601                 uint32_t syncobj;
 602
 603                 ret = drmSyncobjCreate(dev->fd, 0, &syncobj);
 604                 assert(!ret);
 605
 606                 ret = drmSyncobjImportSyncFile(dev->fd, syncobj, *fd);
 607                 assert(!ret);
 608                 util_dynarray_append(&syncobjs, uint32_t, syncobj);
 609         }
 610
 611         uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 612         if (abs_timeout == OS_TIMEOUT_INFINITE)
 613                 abs_timeout = INT64_MAX;
 614
 615         ret = drmSyncobjWait(dev->fd, util_dynarray_begin(&syncobjs),
 616                              util_dynarray_num_elements(&syncobjs, uint32_t),
 617                              abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
 618                              NULL);
 619
 620         util_dynarray_foreach(&syncobjs, uint32_t, syncobj)
 621                 drmSyncobjDestroy(dev->fd, *syncobj);
 622
 623         return ret >= 0;
 624 }
 625
 626 struct panfrost_fence *
 627 panfrost_fence_create(struct panfrost_context *ctx,
 628                       struct util_dynarray *fences)
 629 {
 630         struct panfrost_device *device = pan_device(ctx->base.screen);
 631         struct panfrost_fence *f = calloc(1, sizeof(*f));
 632         if (!f)
 633                 return NULL;
 634
 635         util_dynarray_init(&f->syncfds, NULL);
 636
 637         /* Export fences from all pending batches. */
 638         util_dynarray_foreach(fences, struct panfrost_batch_fence *, fence) {
 639                 int fd = -1;
 640
 641                 /* The fence is already signaled, no need to export it. */
 642                 if ((*fence)->signaled)
 643                         continue;
 644
 645                 drmSyncobjExportSyncFile(device->fd, (*fence)->syncobj, &fd);
 646                 if (fd == -1)
 647                         fprintf(stderr, "export failed: %m\n");
 648
 649                 assert(fd != -1);
 650                 util_dynarray_append(&f->syncfds, int, fd);
 651         }
 652
 653         pipe_reference_init(&f->reference, 1);
 654
 655         return f;
 656 }
 657
 658 static const void *
 659 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 660                                      enum pipe_shader_ir ir,
 661                                      enum pipe_shader_type shader)
 662 {
 663         if (pan_device(pscreen)->quirks & IS_BIFROST)
 664                 return &bifrost_nir_options;
 665         else
 666                 return &midgard_nir_options;
 667 }
 668
 669 struct pipe_screen *
 670 panfrost_create_screen(int fd, struct renderonly *ro)
 671 {
 672         pan_debug = debug_get_option_pan_debug();
 673
 674         /* Blacklist apps known to be buggy under Panfrost */
 675         const char *proc = util_get_process_name();
 676         const char *blacklist[] = {
 677                 "chromium",
 678                 "chrome",
 679         };
 680
 681         for (unsigned i = 0; i < ARRAY_SIZE(blacklist); ++i) {
 682                 if ((strcmp(blacklist[i], proc) == 0))
 683                         return NULL;
 684         }
 685
 686         /* Create the screen */
 687         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 688
 689         if (!screen)
 690                 return NULL;
 691
 692         struct panfrost_device *dev = pan_device(&screen->base);
 693         panfrost_open_device(screen, fd, dev);
 694
 695         if (ro) {
 696                 dev->ro = renderonly_dup(ro);
 697                 if (!dev->ro) {
 698                         DBG("Failed to dup renderonly object\n");
 699                         free(screen);
 700                         return NULL;
 701                 }
 702         }
 703
 704         /* Check if we're loading against a supported GPU model. */
 705
 706         switch (dev->gpu_id) {
 707         case 0x720: /* T720 */
 708         case 0x750: /* T760 */
 709         case 0x820: /* T820 */
 710         case 0x860: /* T860 */
 711                 break;
 712         case 0x7093: /* G31 */
 713         case 0x7212: /* G52 */
 714                 if (pan_debug & PAN_DBG_BIFROST)
 715                         break;
 716
 717                 /* fallthrough */
 718         default:
 719                 /* Fail to load against untested models */
 720                 debug_printf("panfrost: Unsupported model %X", dev->gpu_id);
 721                 panfrost_destroy_screen(&(screen->base));
 722                 return NULL;
 723         }
 724
 725         if (pan_debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
 726                 pandecode_initialize(!(pan_debug & PAN_DBG_TRACE));
 727
 728         screen->base.destroy = panfrost_destroy_screen;
 729
 730         screen->base.get_name = panfrost_get_name;
 731         screen->base.get_vendor = panfrost_get_vendor;
 732         screen->base.get_device_vendor = panfrost_get_device_vendor;
 733         screen->base.get_param = panfrost_get_param;
 734         screen->base.get_shader_param = panfrost_get_shader_param;
 735         screen->base.get_compute_param = panfrost_get_compute_param;
 736         screen->base.get_paramf = panfrost_get_paramf;
 737         screen->base.get_timestamp = panfrost_get_timestamp;
 738         screen->base.is_format_supported = panfrost_is_format_supported;
 739         screen->base.context_create = panfrost_create_context;
 740         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 741         screen->base.fence_reference = panfrost_fence_reference;
 742         screen->base.fence_finish = panfrost_fence_finish;
 743         screen->base.set_damage_region = panfrost_resource_set_damage_region;
 744
 745         panfrost_resource_screen_init(&screen->base);
 746
 747         return &screen->base;
 748 }