src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_format.h"
  32 #include "util/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "util/u_process.h"
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_screen.h"
  39 #include "draw/draw_context.h"
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44 #include "drm-uapi/panfrost_drm.h"
  45
  46 #include "pan_screen.h"
  47 #include "pan_resource.h"
  48 #include "pan_public.h"
  49 #include "pan_util.h"
  50 #include "pandecode/decode.h"
  51
  52 #include "pan_context.h"
  53 #include "midgard/midgard_compile.h"
  54
  55 static const struct debug_named_value debug_options[] = {
  56         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  57         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  58         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  59         {"afbc",      PAN_DBG_AFBC,     "Enable non-conformant AFBC impl"},
  60         DEBUG_NAMED_VALUE_END
  61 };
  62
  63 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug, "PAN_MESA_DEBUG", debug_options, 0)
  64
  65 int pan_debug = 0;
  66
  67 static const char *
  68 panfrost_get_name(struct pipe_screen *screen)
  69 {
  70         return "panfrost";
  71 }
  72
  73 static const char *
  74 panfrost_get_vendor(struct pipe_screen *screen)
  75 {
  76         return "panfrost";
  77 }
  78
  79 static const char *
  80 panfrost_get_device_vendor(struct pipe_screen *screen)
  81 {
  82         return "Arm";
  83 }
  84
  85 static int
  86 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  87 {
  88         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  89         bool is_deqp = pan_debug & PAN_DBG_DEQP;
  90
  91         switch (param) {
  92         case PIPE_CAP_NPOT_TEXTURES:
  93         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  94         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  95         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  96         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  97         case PIPE_CAP_POINT_SPRITE:
  98                 return 1;
  99
 100         case PIPE_CAP_MAX_RENDER_TARGETS:
 101                 return is_deqp ? 4 : 1;
 102
 103
 104         case PIPE_CAP_OCCLUSION_QUERY:
 105                 return 1;
 106         case PIPE_CAP_QUERY_TIME_ELAPSED:
 107         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 108         case PIPE_CAP_QUERY_TIMESTAMP:
 109         case PIPE_CAP_QUERY_SO_OVERFLOW:
 110                 return 0;
 111
 112         case PIPE_CAP_TEXTURE_SWIZZLE:
 113                 return 1;
 114
 115         case PIPE_CAP_TGSI_INSTANCEID:
 116         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 117                 return is_deqp ? 1 : 0;
 118
 119         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 120                 return is_deqp ? 4 : 0;
 121         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 122         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 123                 return is_deqp ? 64 : 0;
 124         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 125                 return 1;
 126
 127         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 128                 return is_deqp ? 256 : 0; /* for GL3 */
 129
 130         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 131         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 132                 return is_deqp ? 140 : 120;
 133         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 134                 return is_deqp ? 300 : 120;
 135
 136         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 137                 return is_deqp ? 16 : 0;
 138
 139         case PIPE_CAP_CUBE_MAP_ARRAY:
 140                 return is_deqp;
 141
 142         /* For faking GLES 3.1 for dEQP-GLES31 */
 143         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 144         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 145         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 146         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 147                 return is_deqp;
 148
 149         /* For faking compute shaders */
 150         case PIPE_CAP_COMPUTE:
 151                 return is_deqp;
 152
 153         /* TODO: Where does this req come from in practice? */
 154         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 155                 return 1;
 156
 157         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 158                 return 4096;
 159         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 160         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 161                 return 13;
 162
 163         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 164         case PIPE_CAP_INDEP_BLEND_ENABLE:
 165         case PIPE_CAP_INDEP_BLEND_FUNC:
 166                 return 1;
 167
 168         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 169                 /* Hardware is natively upper left */
 170                 return 0;
 171
 172         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 173         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 174         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 175         case PIPE_CAP_GENERATE_MIPMAP:
 176                 return 1;
 177
 178         /* We would prefer varyings */
 179         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 180         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 181                 return 0;
 182
 183         /* I really don't want to set this CAP but let's not swim against the
 184          * tide.. */
 185         case PIPE_CAP_TGSI_TEXCOORD:
 186                 return 1;
 187
 188         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 189         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 190                 return 1;
 191
 192         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 193                 return 0xffff;
 194
 195         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 196                 return 1;
 197
 198         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 199                 return 65536;
 200
 201         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 202                 return 0;
 203
 204         case PIPE_CAP_ENDIANNESS:
 205                 return PIPE_ENDIAN_NATIVE;
 206
 207         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 208                 return 1;
 209
 210         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 211                 return -8;
 212
 213         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 214                 return 7;
 215
 216         case PIPE_CAP_VENDOR_ID:
 217         case PIPE_CAP_DEVICE_ID:
 218                 return 0xFFFFFFFF;
 219
 220         case PIPE_CAP_ACCELERATED:
 221         case PIPE_CAP_UMA:
 222         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 223         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 224         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 225         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 226                 return 1;
 227
 228         case PIPE_CAP_VIDEO_MEMORY: {
 229                 uint64_t system_memory;
 230
 231                 if (!os_get_total_physical_memory(&system_memory))
 232                         return 0;
 233
 234                 return (int)(system_memory >> 20);
 235         }
 236
 237         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 238                 return 4;
 239
 240         case PIPE_CAP_MAX_VARYINGS:
 241                 return 16;
 242
 243         default:
 244                 return u_pipe_screen_get_param_defaults(screen, param);
 245         }
 246 }
 247
 248 static int
 249 panfrost_get_shader_param(struct pipe_screen *screen,
 250                           enum pipe_shader_type shader,
 251                           enum pipe_shader_cap param)
 252 {
 253         bool is_deqp = pan_debug & PAN_DBG_DEQP;
 254
 255         if (shader != PIPE_SHADER_VERTEX &&
 256             shader != PIPE_SHADER_FRAGMENT &&
 257             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 258                 return 0;
 259
 260         /* this is probably not totally correct.. but it's a start: */
 261         switch (param) {
 262         case PIPE_SHADER_CAP_SCALAR_ISA:
 263                 return 0;
 264
 265         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 266         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 267         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 268         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 269                 return 16384;
 270
 271         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 272                 return 1024;
 273
 274         case PIPE_SHADER_CAP_MAX_INPUTS:
 275                 return 16;
 276
 277         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 278                 return shader == PIPE_SHADER_FRAGMENT ? 4 : 8;
 279
 280         case PIPE_SHADER_CAP_MAX_TEMPS:
 281                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 282
 283         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 284                 return 16 * 1024 * sizeof(float);
 285
 286         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 287                 return PAN_MAX_CONST_BUFFERS;
 288
 289         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 290                 return 0;
 291
 292         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 293                 return 1;
 294         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 295                 return 0;
 296
 297         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 298                 return 0;
 299
 300         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 301                 return 1;
 302
 303         case PIPE_SHADER_CAP_SUBROUTINES:
 304                 return 0;
 305
 306         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 307                 return 0;
 308
 309         case PIPE_SHADER_CAP_INTEGERS:
 310                 return 1;
 311
 312         case PIPE_SHADER_CAP_INT64_ATOMICS:
 313         case PIPE_SHADER_CAP_FP16:
 314         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 315         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 316         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 317         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 318         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 319                 return 0;
 320
 321         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 322         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 323                 return 16; /* XXX: How many? */
 324
 325         case PIPE_SHADER_CAP_PREFERRED_IR:
 326                 return PIPE_SHADER_IR_NIR;
 327
 328         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 329                 return (1 << PIPE_SHADER_IR_NIR);
 330
 331         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 332                 return 32;
 333
 334         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 335         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 336                 return is_deqp ? 4 : 0;
 337         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 338         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 339                 return 0;
 340
 341         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 342         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 343                 return 0;
 344
 345         default:
 346                 fprintf(stderr, "unknown shader param %d\n", param);
 347                 return 0;
 348         }
 349
 350         return 0;
 351 }
 352
 353 static float
 354 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 355 {
 356         switch (param) {
 357         case PIPE_CAPF_MAX_LINE_WIDTH:
 358
 359         /* fall-through */
 360         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 361                 return 255.0; /* arbitrary */
 362
 363         case PIPE_CAPF_MAX_POINT_WIDTH:
 364
 365         /* fall-through */
 366         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 367                 return 1024.0;
 368
 369         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 370                 return 16.0;
 371
 372         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 373                 return 16.0; /* arbitrary */
 374
 375         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 376         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 377         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 378                 return 0.0f;
 379
 380         default:
 381                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 382                 return 0.0;
 383         }
 384 }
 385
 386 /**
 387  * Query format support for creating a texture, drawing surface, etc.
 388  * \param format  the format to test
 389  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 390  */
 391 static bool
 392 panfrost_is_format_supported( struct pipe_screen *screen,
 393                               enum pipe_format format,
 394                               enum pipe_texture_target target,
 395                               unsigned sample_count,
 396                               unsigned storage_sample_count,
 397                               unsigned bind)
 398 {
 399         const struct util_format_description *format_desc;
 400
 401         assert(target == PIPE_BUFFER ||
 402                target == PIPE_TEXTURE_1D ||
 403                target == PIPE_TEXTURE_1D_ARRAY ||
 404                target == PIPE_TEXTURE_2D ||
 405                target == PIPE_TEXTURE_2D_ARRAY ||
 406                target == PIPE_TEXTURE_RECT ||
 407                target == PIPE_TEXTURE_3D ||
 408                target == PIPE_TEXTURE_CUBE ||
 409                target == PIPE_TEXTURE_CUBE_ARRAY);
 410
 411         format_desc = util_format_description(format);
 412
 413         if (!format_desc)
 414                 return false;
 415
 416         if (sample_count > 1)
 417                 return false;
 418
 419         /* Format wishlist */
 420         if (format == PIPE_FORMAT_X8Z24_UNORM)
 421                 return false;
 422
 423         if (format == PIPE_FORMAT_A1B5G5R5_UNORM || format == PIPE_FORMAT_X1B5G5R5_UNORM)
 424                 return false;
 425
 426         /* TODO */
 427         if (format == PIPE_FORMAT_B5G5R5A1_UNORM)
 428                 return FALSE;
 429
 430         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 431          * more alpha than they ask for */
 432
 433         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 434         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 435
 436         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 437                 return false;
 438
 439         if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN &&
 440             format_desc->layout != UTIL_FORMAT_LAYOUT_OTHER) {
 441                 /* Compressed formats not yet hooked up. */
 442                 return false;
 443         }
 444
 445         /* Internally, formats that are depth/stencil renderable are limited.
 446          *
 447          * In particular: Z16, Z24, Z24S8, S8 are all identical from the GPU
 448          * rendering perspective. That is, we render to Z24S8 (which we can
 449          * AFBC compress), ignore the different when texturing (who cares?),
 450          * and then in the off-chance there's a CPU read we blit back to
 451          * staging.
 452          *
 453          * ...alternatively, we can make the state tracker deal with that. */
 454
 455         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 456                 switch (format) {
 457                         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 458                         case PIPE_FORMAT_Z24X8_UNORM:
 459                         case PIPE_FORMAT_Z32_UNORM:
 460                         case PIPE_FORMAT_Z32_FLOAT:
 461                         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 462                                 return true;
 463
 464                         default:
 465                                 return false;
 466                 }
 467         }
 468
 469         return true;
 470 }
 471
 472 static int
 473 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 474                 enum pipe_compute_cap param, void *ret)
 475 {
 476         const char * const ir = "panfrost";
 477
 478         if (!(pan_debug & PAN_DBG_DEQP))
 479                 return 0;
 480
 481 #define RET(x) do {                  \
 482    if (ret)                          \
 483       memcpy(ret, x, sizeof(x));     \
 484    return sizeof(x);                 \
 485 } while (0)
 486
 487         switch (param) {
 488         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 489                 /* TODO: We'll want 64-bit pointers soon */
 490                 RET((uint32_t []){ 32 });
 491
 492         case PIPE_COMPUTE_CAP_IR_TARGET:
 493                 if (ret)
 494                         sprintf(ret, "%s", ir);
 495                 return strlen(ir) * sizeof(char);
 496
 497         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 498                 RET((uint64_t []) { 3 });
 499
 500         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 501                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 502
 503         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 504                 RET(((uint64_t []) { 1024, 1024, 64 }));
 505
 506         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 507                 RET((uint64_t []) { 1024 });
 508
 509         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 510                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 511
 512         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 513                 RET((uint64_t []) { 32768 });
 514
 515         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 516         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 517                 RET((uint64_t []) { 4096 });
 518
 519         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 520                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 521
 522         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 523                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 524
 525         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 526                 RET((uint32_t []) { 9999 });  // TODO
 527
 528         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 529                 RET((uint32_t []) { 1 }); // TODO
 530
 531         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 532                 RET((uint32_t []) { 32 });  // TODO
 533
 534         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 535                 RET((uint64_t []) { 1024 }); // TODO
 536         }
 537
 538         return 0;
 539 }
 540
 541 static void
 542 panfrost_destroy_screen(struct pipe_screen *pscreen)
 543 {
 544         struct panfrost_screen *screen = pan_screen(pscreen);
 545         panfrost_bo_cache_evict_all(screen);
 546         pthread_mutex_destroy(&screen->bo_cache_lock);
 547         drmFreeVersion(screen->kernel_version);
 548         ralloc_free(screen);
 549 }
 550
 551 static void
 552 panfrost_flush_frontbuffer(struct pipe_screen *_screen,
 553                            struct pipe_resource *resource,
 554                            unsigned level, unsigned layer,
 555                            void *context_private,
 556                            struct pipe_box *sub_box)
 557 {
 558         /* TODO: Display target integration */
 559 }
 560
 561 static uint64_t
 562 panfrost_get_timestamp(struct pipe_screen *_screen)
 563 {
 564         return os_time_get_nano();
 565 }
 566
 567 static void
 568 panfrost_fence_reference(struct pipe_screen *pscreen,
 569                          struct pipe_fence_handle **ptr,
 570                          struct pipe_fence_handle *fence)
 571 {
 572         struct panfrost_fence **p = (struct panfrost_fence **)ptr;
 573         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 574         struct panfrost_fence *old = *p;
 575
 576         if (pipe_reference(&(*p)->reference, &f->reference)) {
 577                 close(old->fd);
 578                 free(old);
 579         }
 580         *p = f;
 581 }
 582
 583 static bool
 584 panfrost_fence_finish(struct pipe_screen *pscreen,
 585                       struct pipe_context *ctx,
 586                       struct pipe_fence_handle *fence,
 587                       uint64_t timeout)
 588 {
 589         struct panfrost_screen *screen = pan_screen(pscreen);
 590         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 591         int ret;
 592
 593         unsigned syncobj;
 594         ret = drmSyncobjCreate(screen->fd, 0, &syncobj);
 595         if (ret) {
 596                 fprintf(stderr, "Failed to create syncobj to wait on: %m\n");
 597                 return false;
 598         }
 599
 600         ret = drmSyncobjImportSyncFile(screen->fd, syncobj, f->fd);
 601         if (ret) {
 602                 fprintf(stderr, "Failed to import fence to syncobj: %m\n");
 603                 return false;
 604         }
 605
 606         uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 607         if (abs_timeout == OS_TIMEOUT_INFINITE)
 608                 abs_timeout = INT64_MAX;
 609
 610         ret = drmSyncobjWait(screen->fd, &syncobj, 1, abs_timeout, 0, NULL);
 611
 612         drmSyncobjDestroy(screen->fd, syncobj);
 613
 614         return ret >= 0;
 615 }
 616
 617 struct panfrost_fence *
 618 panfrost_fence_create(struct panfrost_context *ctx)
 619 {
 620         struct panfrost_screen *screen = pan_screen(ctx->base.screen);
 621         struct panfrost_fence *f = calloc(1, sizeof(*f));
 622         if (!f)
 623                 return NULL;
 624
 625         /* Snapshot the last Panfrost's rendering's out fence.  We'd rather have
 626          * another syncobj instead of a sync file, but this is all we get.
 627          * (HandleToFD/FDToHandle just gives you another syncobj ID for the
 628          * same syncobj).
 629          */
 630         drmSyncobjExportSyncFile(screen->fd, ctx->out_sync, &f->fd);
 631         if (f->fd == -1) {
 632                 fprintf(stderr, "export failed: %m\n");
 633                 free(f);
 634                 return NULL;
 635         }
 636
 637         pipe_reference_init(&f->reference, 1);
 638
 639         return f;
 640 }
 641
 642 static const void *
 643 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 644                                      enum pipe_shader_ir ir,
 645                                      enum pipe_shader_type shader)
 646 {
 647         return &midgard_nir_options;
 648 }
 649
 650 static unsigned
 651 panfrost_query_gpu_version(struct panfrost_screen *screen)
 652 {
 653         struct drm_panfrost_get_param get_param = {0,};
 654         ASSERTED int ret;
 655
 656         get_param.param = DRM_PANFROST_PARAM_GPU_PROD_ID;
 657         ret = drmIoctl(screen->fd, DRM_IOCTL_PANFROST_GET_PARAM, &get_param);
 658         assert(!ret);
 659
 660         return get_param.value;
 661 }
 662
 663 struct pipe_screen *
 664 panfrost_create_screen(int fd, struct renderonly *ro)
 665 {
 666         pan_debug = debug_get_option_pan_debug();
 667
 668         /* Blacklist apps known to be buggy under Panfrost */
 669         const char *proc = util_get_process_name();
 670         const char *blacklist[] = {
 671                 "chromium",
 672                 "chrome",
 673         };
 674
 675         for (unsigned i = 0; i < ARRAY_SIZE(blacklist); ++i) {
 676                 if ((strcmp(blacklist[i], proc) == 0))
 677                         return NULL;
 678         }
 679
 680         /* Create the screen */
 681         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 682
 683         if (!screen)
 684                 return NULL;
 685
 686         if (ro) {
 687                 screen->ro = renderonly_dup(ro);
 688                 if (!screen->ro) {
 689                         fprintf(stderr, "Failed to dup renderonly object\n");
 690                         free(screen);
 691                         return NULL;
 692                 }
 693         }
 694
 695         screen->fd = fd;
 696
 697         screen->gpu_id = panfrost_query_gpu_version(screen);
 698         screen->require_sfbd = screen->gpu_id < 0x0750; /* T760 is the first to support MFBD */
 699         screen->kernel_version = drmGetVersion(fd);
 700
 701         /* Check if we're loading against a supported GPU model. */
 702
 703         switch (screen->gpu_id) {
 704         case 0x750: /* T760 */
 705         case 0x820: /* T820 */
 706         case 0x860: /* T860 */
 707                 break;
 708         default:
 709                 /* Fail to load against untested models */
 710                 debug_printf("panfrost: Unsupported model %X",
 711                              screen->gpu_id);
 712                 return NULL;
 713         }
 714
 715         pthread_mutex_init(&screen->bo_cache_lock, NULL);
 716         for (unsigned i = 0; i < ARRAY_SIZE(screen->bo_cache); ++i)
 717                 list_inithead(&screen->bo_cache[i]);
 718
 719         if (pan_debug & PAN_DBG_TRACE)
 720                 pandecode_initialize();
 721
 722         screen->base.destroy = panfrost_destroy_screen;
 723
 724         screen->base.get_name = panfrost_get_name;
 725         screen->base.get_vendor = panfrost_get_vendor;
 726         screen->base.get_device_vendor = panfrost_get_device_vendor;
 727         screen->base.get_param = panfrost_get_param;
 728         screen->base.get_shader_param = panfrost_get_shader_param;
 729         screen->base.get_compute_param = panfrost_get_compute_param;
 730         screen->base.get_paramf = panfrost_get_paramf;
 731         screen->base.get_timestamp = panfrost_get_timestamp;
 732         screen->base.is_format_supported = panfrost_is_format_supported;
 733         screen->base.context_create = panfrost_create_context;
 734         screen->base.flush_frontbuffer = panfrost_flush_frontbuffer;
 735         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 736         screen->base.fence_reference = panfrost_fence_reference;
 737         screen->base.fence_finish = panfrost_fence_finish;
 738         screen->base.set_damage_region = panfrost_resource_set_damage_region;
 739
 740         panfrost_resource_screen_init(screen);
 741
 742         return &screen->base;
 743 }