2 * Copyright (C) 2009 Nicolai Haehnle.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "radeon_opcodes.h"
29 #include "radeon_program.h"
31 #include "radeon_program_constants.h"
33 struct rc_opcode_info rc_opcodes
[MAX_RC_OPCODE
] = {
35 .Opcode
= RC_OPCODE_NOP
,
39 .Opcode
= RC_OPCODE_ILLEGAL_OPCODE
,
40 .Name
= "ILLEGAL OPCODE"
43 .Opcode
= RC_OPCODE_ABS
,
50 .Opcode
= RC_OPCODE_ADD
,
57 .Opcode
= RC_OPCODE_ARL
,
63 .Opcode
= RC_OPCODE_CEIL
,
70 .Opcode
= RC_OPCODE_CLAMP
,
77 .Opcode
= RC_OPCODE_CMP
,
84 .Opcode
= RC_OPCODE_CND
,
91 .Opcode
= RC_OPCODE_COS
,
98 .Opcode
= RC_OPCODE_DDX
,
105 .Opcode
= RC_OPCODE_DDY
,
112 .Opcode
= RC_OPCODE_DP2
,
118 .Opcode
= RC_OPCODE_DP3
,
124 .Opcode
= RC_OPCODE_DP4
,
130 .Opcode
= RC_OPCODE_DPH
,
136 .Opcode
= RC_OPCODE_DST
,
142 .Opcode
= RC_OPCODE_EX2
,
146 .IsStandardScalar
= 1
149 .Opcode
= RC_OPCODE_EXP
,
155 .Opcode
= RC_OPCODE_FLR
,
162 .Opcode
= RC_OPCODE_FRC
,
169 .Opcode
= RC_OPCODE_KIL
,
174 .Opcode
= RC_OPCODE_LG2
,
178 .IsStandardScalar
= 1
181 .Opcode
= RC_OPCODE_LIT
,
187 .Opcode
= RC_OPCODE_LOG
,
193 .Opcode
= RC_OPCODE_LRP
,
200 .Opcode
= RC_OPCODE_MAD
,
207 .Opcode
= RC_OPCODE_MAX
,
214 .Opcode
= RC_OPCODE_MIN
,
221 .Opcode
= RC_OPCODE_MOV
,
228 .Opcode
= RC_OPCODE_MUL
,
235 .Opcode
= RC_OPCODE_POW
,
239 .IsStandardScalar
= 1
242 .Opcode
= RC_OPCODE_RCP
,
246 .IsStandardScalar
= 1
249 .Opcode
= RC_OPCODE_RSQ
,
253 .IsStandardScalar
= 1
256 .Opcode
= RC_OPCODE_SCS
,
262 .Opcode
= RC_OPCODE_SEQ
,
269 .Opcode
= RC_OPCODE_SFL
,
276 .Opcode
= RC_OPCODE_SGE
,
283 .Opcode
= RC_OPCODE_SGT
,
290 .Opcode
= RC_OPCODE_SIN
,
294 .IsStandardScalar
= 1
297 .Opcode
= RC_OPCODE_SLE
,
304 .Opcode
= RC_OPCODE_SLT
,
311 .Opcode
= RC_OPCODE_SNE
,
318 .Opcode
= RC_OPCODE_SSG
,
325 .Opcode
= RC_OPCODE_SUB
,
332 .Opcode
= RC_OPCODE_SWZ
,
339 .Opcode
= RC_OPCODE_XPD
,
345 .Opcode
= RC_OPCODE_TEX
,
352 .Opcode
= RC_OPCODE_TXB
,
359 .Opcode
= RC_OPCODE_TXD
,
366 .Opcode
= RC_OPCODE_TXL
,
373 .Opcode
= RC_OPCODE_TXP
,
380 .Opcode
= RC_OPCODE_IF
,
386 .Opcode
= RC_OPCODE_ELSE
,
392 .Opcode
= RC_OPCODE_ENDIF
,
398 .Opcode
= RC_OPCODE_BGNLOOP
,
404 .Opcode
= RC_OPCODE_BRK
,
410 .Opcode
= RC_OPCODE_ENDLOOP
,
416 .Opcode
= RC_OPCODE_CONT
,
422 .Opcode
= RC_OPCODE_REPL_ALPHA
,
423 .Name
= "REPL_ALPHA",
427 .Opcode
= RC_OPCODE_BEGIN_TEX
,
431 .Opcode
= RC_OPCODE_KILP
,
436 void rc_compute_sources_for_writemask(
437 const struct rc_instruction
*inst
,
438 unsigned int writemask
,
439 unsigned int *srcmasks
)
441 const struct rc_opcode_info
* opcode
= rc_get_opcode_info(inst
->U
.I
.Opcode
);
446 if (opcode
->Opcode
== RC_OPCODE_KIL
)
447 srcmasks
[0] |= RC_MASK_XYZW
;
448 else if (opcode
->Opcode
== RC_OPCODE_IF
)
449 srcmasks
[0] |= RC_MASK_X
;
454 if (opcode
->IsComponentwise
) {
455 for(unsigned int src
= 0; src
< opcode
->NumSrcRegs
; ++src
)
456 srcmasks
[src
] |= writemask
;
457 } else if (opcode
->IsStandardScalar
) {
458 for(unsigned int src
= 0; src
< opcode
->NumSrcRegs
; ++src
)
459 srcmasks
[src
] |= RC_MASK_X
;
461 switch(opcode
->Opcode
) {
463 srcmasks
[0] |= RC_MASK_X
;
466 srcmasks
[0] |= RC_MASK_XY
;
467 srcmasks
[1] |= RC_MASK_XY
;
471 srcmasks
[0] |= RC_MASK_XYZ
;
472 srcmasks
[1] |= RC_MASK_XYZ
;
475 srcmasks
[0] |= RC_MASK_XYZW
;
476 srcmasks
[1] |= RC_MASK_XYZW
;
479 srcmasks
[0] |= RC_MASK_XYZ
;
480 srcmasks
[1] |= RC_MASK_XYZW
;
485 srcmasks
[0] |= RC_MASK_W
;
488 switch (inst
->U
.I
.TexSrcTarget
) {
490 srcmasks
[0] |= RC_MASK_X
;
493 case RC_TEXTURE_RECT
:
494 case RC_TEXTURE_1D_ARRAY
:
495 srcmasks
[0] |= RC_MASK_XY
;
498 case RC_TEXTURE_CUBE
:
499 case RC_TEXTURE_2D_ARRAY
:
500 srcmasks
[0] |= RC_MASK_XYZ
;
505 switch (inst
->U
.I
.TexSrcTarget
) {
506 case RC_TEXTURE_1D_ARRAY
:
507 srcmasks
[0] |= RC_MASK_Y
;
510 srcmasks
[0] |= RC_MASK_X
;
511 srcmasks
[1] |= RC_MASK_X
;
512 srcmasks
[2] |= RC_MASK_X
;
514 case RC_TEXTURE_2D_ARRAY
:
515 srcmasks
[0] |= RC_MASK_Z
;
518 case RC_TEXTURE_RECT
:
519 srcmasks
[0] |= RC_MASK_XY
;
520 srcmasks
[1] |= RC_MASK_XY
;
521 srcmasks
[2] |= RC_MASK_XY
;
524 case RC_TEXTURE_CUBE
:
525 srcmasks
[0] |= RC_MASK_XYZ
;
526 srcmasks
[1] |= RC_MASK_XYZ
;
527 srcmasks
[2] |= RC_MASK_XYZ
;
532 srcmasks
[0] |= RC_MASK_Y
| RC_MASK_Z
;
533 srcmasks
[1] |= RC_MASK_Y
| RC_MASK_W
;
537 srcmasks
[0] |= RC_MASK_XY
;
540 srcmasks
[0] |= RC_MASK_X
| RC_MASK_Y
| RC_MASK_W
;