2 * Copyright (C) 2009 Nicolai Haehnle.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #ifndef RADEON_OPCODES_H
29 #define RADEON_OPCODES_H
34 * Opcodes understood by the Radeon compiler.
38 RC_OPCODE_ILLEGAL_OPCODE
,
40 /** vec4 instruction: dst.c = abs(src0.c); */
43 /** vec4 instruction: dst.c = src0.c + src1.c; */
46 /** special instruction: load address register
47 * dst.x = floor(src.x), where dst must be an address register */
50 /** special instruction: load address register with round
51 * dst.x = round(src.x), where dst must be an address register */
54 /** vec4 instruction: dst.c = ceil(src0.c) */
57 /** vec4 instruction: dst.c = clamp(src0.c, src1.c, src2.c) */
60 /** vec4 instruction: dst.c = src0.c < 0.0 ? src1.c : src2.c */
63 /** vec4 instruction: dst.c = src2.c > 0.5 ? src0.c : src1.c */
66 /** scalar instruction: dst = cos(src0.x) */
69 /** special instruction: take vec4 partial derivative in X direction
70 * dst.c = d src0.c / dx */
73 /** special instruction: take vec4 partial derivative in Y direction
74 * dst.c = d src0.c / dy */
77 /** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y */
80 /** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z */
83 /** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z + src0.w*src1.w */
86 /** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z + src1.w */
89 /** special instruction, see ARB_fragment_program */
92 /** scalar instruction: dst = 2**src0.x */
95 /** special instruction, see ARB_vertex_program */
98 /** vec4 instruction: dst.c = floor(src0.c) */
101 /** vec4 instruction: dst.c = src0.c - floor(src0.c) */
104 /** special instruction: stop execution if any component of src0 is negative */
107 /** scalar instruction: dst = log_2(src0.x) */
110 /** special instruction, see ARB_vertex_program */
113 /** special instruction, see ARB_vertex_program */
116 /** vec4 instruction: dst.c = src0.c*src1.c + (1 - src0.c)*src2.c */
119 /** vec4 instruction: dst.c = src0.c*src1.c + src2.c */
122 /** vec4 instruction: dst.c = max(src0.c, src1.c) */
125 /** vec4 instruction: dst.c = min(src0.c, src1.c) */
128 /** vec4 instruction: dst.c = src0.c */
131 /** vec4 instruction: dst.c = src0.c*src1.c */
134 /** scalar instruction: dst = src0.x ** src1.x */
137 /** scalar instruction: dst = 1 / src0.x */
140 /** vec4 instruction: dst.c = floor(src0.c + 0.5) */
143 /** scalar instruction: dst = 1 / sqrt(src0.x) */
146 /** special instruction, see ARB_fragment_program */
149 /** vec4 instruction: dst.c = (src0.c == src1.c) ? 1.0 : 0.0 */
152 /** vec4 instruction: dst.c = 0.0 */
155 /** vec4 instruction: dst.c = (src0.c >= src1.c) ? 1.0 : 0.0 */
158 /** vec4 instruction: dst.c = (src0.c > src1.c) ? 1.0 : 0.0 */
161 /** scalar instruction: dst = sin(src0.x) */
164 /** vec4 instruction: dst.c = (src0.c <= src1.c) ? 1.0 : 0.0 */
167 /** vec4 instruction: dst.c = (src0.c < src1.c) ? 1.0 : 0.0 */
170 /** vec4 instruction: dst.c = (src0.c != src1.c) ? 1.0 : 0.0 */
173 /** vec4 instruction: dst.c = (src0.c < 0 ?) -1 : ((src0.c > 0) : 1 : 0) */
176 /** vec4 instruction: dst.c = src0.c - src1.c */
179 /** vec4 instruction: dst.c = src0.c */
182 /** vec4 instruction: dst.c = (abs(src0.c) - fract(abs(src0.c))) * sgn(src0.c) */
185 /** special instruction, see ARB_fragment_program */
194 /** branch instruction:
195 * If src0.x != 0.0, continue with the next instruction;
196 * otherwise, jump to matching RC_OPCODE_ELSE or RC_OPCODE_ENDIF.
200 /** branch instruction: jump to matching RC_OPCODE_ENDIF */
203 /** branch instruction: has no effect */
214 /** special instruction, used in R300-R500 fragment program pair instructions
215 * indicates that the result of the alpha operation shall be replicated
216 * across all other channels */
217 RC_OPCODE_REPL_ALPHA
,
219 /** special instruction, used in R300-R500 fragment programs
220 * to indicate the start of a block of texture instructions that
221 * can run simultaneously. */
224 /** Stop execution of the shader (GLSL discard) */
227 /* Vertex shader CF Instructions */
235 RC_ME_PRED_SET_RESTORE
,
240 RC_VE_PRED_SNEQ_PUSH
,
246 struct rc_opcode_info
{
250 /** true if the instruction reads from a texture.
252 * \note This is false for the KIL instruction, even though KIL is
253 * a texture instruction from a hardware point of view. */
254 unsigned int HasTexture
:1;
256 unsigned int NumSrcRegs
:2;
257 unsigned int HasDstReg
:1;
259 /** true if this instruction affects control flow */
260 unsigned int IsFlowControl
:1;
262 /** true if this is a vector instruction that operates on components in parallel
263 * without any cross-component interaction */
264 unsigned int IsComponentwise
:1;
266 /** true if this instruction sources only its operands X components
267 * to compute one result which is smeared across all output channels */
268 unsigned int IsStandardScalar
:1;
271 extern struct rc_opcode_info rc_opcodes
[MAX_RC_OPCODE
];
273 static inline const struct rc_opcode_info
* rc_get_opcode_info(rc_opcode opcode
)
275 assert((unsigned int)opcode
< MAX_RC_OPCODE
);
276 assert(rc_opcodes
[opcode
].Opcode
== opcode
);
278 return &rc_opcodes
[opcode
];
281 struct rc_instruction
;
283 void rc_compute_sources_for_writemask(
284 const struct rc_instruction
*inst
,
285 unsigned int writemask
,
286 unsigned int *srcmasks
);
288 #endif /* RADEON_OPCODES_H */