nvc0: do not set tiled mode on gart bo when fence debugging is used
[mesa.git] / src / gallium / drivers / r300 / r300_chipset.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2011 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 #include "r300_chipset.h"
25 #include "../../winsys/radeon/drm/radeon_winsys.h"
26
27 #include "util/u_debug.h"
28 #include "util/u_memory.h"
29
30 #include <stdio.h>
31 #include <errno.h>
32
33 /* r300_chipset: A file all to itself for deducing the various properties of
34 * Radeons. */
35
36 static void r300_apply_hyperz_blacklist(struct r300_capabilities* caps)
37 {
38 static const char *list[] = {
39 "X", /* the DDX or indirect rendering */
40 "Xorg", /* (alternative name) */
41 "check_gl_texture_size", /* compiz */
42 "Compiz",
43 "gnome-session-check-accelerated-helper",
44 "gnome-shell",
45 "kwin_opengl_test",
46 "kwin",
47 "firefox",
48 };
49 int i;
50
51 for (i = 0; i < Elements(list); i++) {
52 if (strcmp(list[i], program_invocation_short_name) == 0) {
53 caps->zmask_ram = 0;
54 caps->hiz_ram = 0;
55 break;
56 }
57 }
58 }
59
60 /* Parse a PCI ID and fill an r300_capabilities struct with information. */
61 void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps)
62 {
63 switch (pci_id) {
64 #define CHIPSET(pci_id, name, chipfamily) \
65 case pci_id: \
66 caps->family = CHIP_##chipfamily; \
67 break;
68 #include "pci_ids/r300_pci_ids.h"
69 #undef CHIPSET
70
71 default:
72 fprintf(stderr, "r300: Warning: Unknown chipset 0x%x\nAborting...",
73 pci_id);
74 abort();
75 }
76
77 /* Defaults. */
78 caps->high_second_pipe = FALSE;
79 caps->num_vert_fpus = 0;
80 caps->hiz_ram = 0;
81 caps->zmask_ram = 0;
82
83
84 switch (caps->family) {
85 case CHIP_R300:
86 case CHIP_R350:
87 caps->high_second_pipe = TRUE;
88 caps->num_vert_fpus = 4;
89 caps->hiz_ram = R300_HIZ_LIMIT;
90 caps->zmask_ram = PIPE_ZMASK_SIZE;
91 break;
92
93 case CHIP_RV350:
94 case CHIP_RV370:
95 caps->high_second_pipe = TRUE;
96 caps->num_vert_fpus = 2;
97 caps->zmask_ram = RV3xx_ZMASK_SIZE;
98 break;
99
100 case CHIP_RV380:
101 caps->high_second_pipe = TRUE;
102 caps->num_vert_fpus = 2;
103 caps->hiz_ram = R300_HIZ_LIMIT;
104 caps->zmask_ram = RV3xx_ZMASK_SIZE;
105 break;
106
107 case CHIP_RS400:
108 case CHIP_RS600:
109 case CHIP_RS690:
110 case CHIP_RS740:
111 break;
112
113 case CHIP_RC410:
114 case CHIP_RS480:
115 caps->zmask_ram = RV3xx_ZMASK_SIZE;
116 break;
117
118 case CHIP_R420:
119 case CHIP_R423:
120 case CHIP_R430:
121 case CHIP_R480:
122 case CHIP_R481:
123 case CHIP_RV410:
124 caps->num_vert_fpus = 6;
125 caps->hiz_ram = R300_HIZ_LIMIT;
126 caps->zmask_ram = PIPE_ZMASK_SIZE;
127 break;
128
129 case CHIP_R520:
130 caps->num_vert_fpus = 8;
131 caps->hiz_ram = R300_HIZ_LIMIT;
132 caps->zmask_ram = PIPE_ZMASK_SIZE;
133 break;
134
135 case CHIP_RV515:
136 caps->num_vert_fpus = 2;
137 caps->hiz_ram = R300_HIZ_LIMIT;
138 caps->zmask_ram = PIPE_ZMASK_SIZE;
139 break;
140
141 case CHIP_RV530:
142 caps->num_vert_fpus = 5;
143 caps->hiz_ram = RV530_HIZ_LIMIT;
144 caps->zmask_ram = PIPE_ZMASK_SIZE;
145 break;
146
147 case CHIP_R580:
148 case CHIP_RV560:
149 case CHIP_RV570:
150 caps->num_vert_fpus = 8;
151 caps->hiz_ram = RV530_HIZ_LIMIT;
152 caps->zmask_ram = PIPE_ZMASK_SIZE;
153 break;
154 }
155
156 caps->num_tex_units = 16;
157 caps->is_r400 = caps->family >= CHIP_R420 && caps->family < CHIP_RV515;
158 caps->is_r500 = caps->family >= CHIP_RV515;
159 caps->is_rv350 = caps->family >= CHIP_RV350;
160 caps->z_compress = caps->is_rv350 ? R300_ZCOMP_8X8 : R300_ZCOMP_4X4;
161 caps->dxtc_swizzle = caps->is_r400 || caps->is_r500;
162 caps->has_us_format = caps->family == CHIP_R520;
163 caps->has_tcl = caps->num_vert_fpus > 0;
164
165 if (caps->has_tcl) {
166 caps->has_tcl = debug_get_bool_option("RADEON_NO_TCL", FALSE) ? FALSE : TRUE;
167 }
168
169 r300_apply_hyperz_blacklist(caps);
170 }