Merge branch 'mesa_7_6_branch'
[mesa.git] / src / gallium / drivers / r300 / r300_chipset.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 #include "r300_chipset.h"
24
25 #include "util/u_debug.h"
26
27 /* r300_chipset: A file all to itself for deducing the various properties of
28 * Radeons. */
29
30 /* Parse a PCI ID and fill an r300_capabilities struct with information. */
31 void r300_parse_chipset(struct r300_capabilities* caps)
32 {
33 /* Reasonable defaults */
34 caps->num_vert_fpus = 4;
35 caps->has_tcl = debug_get_bool_option("RADEON_NO_TCL", FALSE) ? FALSE : TRUE;
36 caps->is_r500 = FALSE;
37 caps->high_second_pipe = FALSE;
38
39
40 /* Note: These are not ordered by PCI ID. I leave that task to GCC,
41 * which will perform the ordering while collating jump tables. Instead,
42 * I've tried to group them according to capabilities and age. */
43 switch (caps->pci_id) {
44 case 0x4144:
45 caps->family = CHIP_FAMILY_R300;
46 caps->high_second_pipe = TRUE;
47 break;
48
49 case 0x4145:
50 case 0x4146:
51 case 0x4147:
52 case 0x4E44:
53 case 0x4E45:
54 case 0x4E46:
55 case 0x4E47:
56 caps->family = CHIP_FAMILY_R300;
57 caps->high_second_pipe = TRUE;
58 break;
59
60 case 0x4150:
61 case 0x4151:
62 case 0x4152:
63 case 0x4153:
64 case 0x4154:
65 case 0x4155:
66 case 0x4156:
67 case 0x4E50:
68 case 0x4E51:
69 case 0x4E52:
70 case 0x4E53:
71 case 0x4E54:
72 case 0x4E56:
73 caps->family = CHIP_FAMILY_RV350;
74 caps->high_second_pipe = TRUE;
75 break;
76
77 case 0x4148:
78 case 0x4149:
79 case 0x414A:
80 case 0x414B:
81 case 0x4E48:
82 case 0x4E49:
83 case 0x4E4B:
84 caps->family = CHIP_FAMILY_R350;
85 caps->high_second_pipe = TRUE;
86 break;
87
88 case 0x4E4A:
89 caps->family = CHIP_FAMILY_R360;
90 caps->high_second_pipe = TRUE;
91 break;
92
93 case 0x5460:
94 case 0x5462:
95 case 0x5464:
96 case 0x5B60:
97 case 0x5B62:
98 case 0x5B63:
99 case 0x5B64:
100 case 0x5B65:
101 caps->family = CHIP_FAMILY_RV370;
102 caps->high_second_pipe = TRUE;
103 break;
104
105 case 0x3150:
106 case 0x3152:
107 case 0x3154:
108 case 0x3E50:
109 case 0x3E54:
110 caps->family = CHIP_FAMILY_RV380;
111 caps->high_second_pipe = TRUE;
112 break;
113
114 case 0x4A48:
115 case 0x4A49:
116 case 0x4A4A:
117 case 0x4A4B:
118 case 0x4A4C:
119 case 0x4A4D:
120 case 0x4A4E:
121 case 0x4A4F:
122 case 0x4A50:
123 case 0x4A54:
124 caps->family = CHIP_FAMILY_R420;
125 caps->num_vert_fpus = 6;
126 break;
127
128 case 0x5548:
129 case 0x5549:
130 case 0x554A:
131 case 0x554B:
132 case 0x5550:
133 case 0x5551:
134 case 0x5552:
135 case 0x5554:
136 case 0x5D57:
137 caps->family = CHIP_FAMILY_R423;
138 caps->num_vert_fpus = 6;
139 break;
140
141 case 0x554C:
142 case 0x554D:
143 case 0x554E:
144 case 0x554F:
145 case 0x5D48:
146 case 0x5D49:
147 case 0x5D4A:
148 caps->family = CHIP_FAMILY_R430;
149 caps->num_vert_fpus = 6;
150 break;
151
152 case 0x5D4C:
153 case 0x5D4D:
154 case 0x5D4E:
155 case 0x5D4F:
156 case 0x5D50:
157 case 0x5D52:
158 caps->family = CHIP_FAMILY_R480;
159 caps->num_vert_fpus = 6;
160 break;
161
162 case 0x4B48:
163 case 0x4B49:
164 case 0x4B4A:
165 case 0x4B4B:
166 case 0x4B4C:
167 caps->family = CHIP_FAMILY_R481;
168 caps->num_vert_fpus = 6;
169 break;
170
171 case 0x5E4C:
172 case 0x5E4F:
173 case 0x564A:
174 case 0x564B:
175 case 0x564F:
176 case 0x5652:
177 case 0x5653:
178 case 0x5657:
179 case 0x5E48:
180 case 0x5E4A:
181 case 0x5E4B:
182 case 0x5E4D:
183 caps->family = CHIP_FAMILY_RV410;
184 caps->num_vert_fpus = 6;
185 break;
186
187 case 0x5954:
188 case 0x5955:
189 caps->family = CHIP_FAMILY_RS480;
190 caps->has_tcl = FALSE;
191 break;
192
193 case 0x5974:
194 case 0x5975:
195 caps->family = CHIP_FAMILY_RS482;
196 caps->has_tcl = FALSE;
197 break;
198
199 case 0x5A41:
200 case 0x5A42:
201 caps->family = CHIP_FAMILY_RS400;
202 caps->has_tcl = FALSE;
203 break;
204
205 case 0x5A61:
206 case 0x5A62:
207 caps->family = CHIP_FAMILY_RC410;
208 caps->has_tcl = FALSE;
209 break;
210
211 case 0x791E:
212 case 0x791F:
213 caps->family = CHIP_FAMILY_RS690;
214 caps->has_tcl = FALSE;
215 break;
216
217 case 0x793F:
218 case 0x7941:
219 case 0x7942:
220 caps->family = CHIP_FAMILY_RS600;
221 caps->has_tcl = FALSE;
222 break;
223
224 case 0x796C:
225 case 0x796D:
226 case 0x796E:
227 case 0x796F:
228 caps->family = CHIP_FAMILY_RS740;
229 caps->has_tcl = FALSE;
230 break;
231
232 case 0x7100:
233 case 0x7101:
234 case 0x7102:
235 case 0x7103:
236 case 0x7104:
237 case 0x7105:
238 case 0x7106:
239 case 0x7108:
240 case 0x7109:
241 case 0x710A:
242 case 0x710B:
243 case 0x710C:
244 case 0x710E:
245 case 0x710F:
246 caps->family = CHIP_FAMILY_R520;
247 caps->num_vert_fpus = 8;
248 caps->is_r500 = TRUE;
249 break;
250
251 case 0x7140:
252 case 0x7141:
253 case 0x7142:
254 case 0x7143:
255 case 0x7144:
256 case 0x7145:
257 case 0x7146:
258 case 0x7147:
259 case 0x7149:
260 case 0x714A:
261 case 0x714B:
262 case 0x714C:
263 case 0x714D:
264 case 0x714E:
265 case 0x714F:
266 case 0x7151:
267 case 0x7152:
268 case 0x7153:
269 case 0x715E:
270 case 0x715F:
271 case 0x7180:
272 case 0x7181:
273 case 0x7183:
274 case 0x7186:
275 case 0x7187:
276 case 0x7188:
277 case 0x718A:
278 case 0x718B:
279 case 0x718C:
280 case 0x718D:
281 case 0x718F:
282 case 0x7193:
283 case 0x7196:
284 case 0x719B:
285 case 0x719F:
286 case 0x7200:
287 case 0x7210:
288 case 0x7211:
289 caps->family = CHIP_FAMILY_RV515;
290 caps->num_vert_fpus = 2;
291 caps->is_r500 = TRUE;
292 break;
293
294 case 0x71C0:
295 case 0x71C1:
296 case 0x71C2:
297 case 0x71C3:
298 case 0x71C4:
299 case 0x71C5:
300 case 0x71C6:
301 case 0x71C7:
302 case 0x71CD:
303 case 0x71CE:
304 case 0x71D2:
305 case 0x71D4:
306 case 0x71D5:
307 case 0x71D6:
308 case 0x71DA:
309 case 0x71DE:
310 caps->family = CHIP_FAMILY_RV530;
311 caps->num_vert_fpus = 5;
312 caps->is_r500 = TRUE;
313 break;
314
315 case 0x7240:
316 case 0x7243:
317 case 0x7244:
318 case 0x7245:
319 case 0x7246:
320 case 0x7247:
321 case 0x7248:
322 case 0x7249:
323 case 0x724A:
324 case 0x724B:
325 case 0x724C:
326 case 0x724D:
327 case 0x724E:
328 case 0x724F:
329 case 0x7284:
330 caps->family = CHIP_FAMILY_R580;
331 caps->num_vert_fpus = 8;
332 caps->is_r500 = TRUE;
333 break;
334
335 case 0x7280:
336 caps->family = CHIP_FAMILY_RV570;
337 caps->num_vert_fpus = 5;
338 caps->is_r500 = TRUE;
339 break;
340
341 case 0x7281:
342 case 0x7283:
343 case 0x7287:
344 case 0x7288:
345 case 0x7289:
346 case 0x728B:
347 case 0x728C:
348 case 0x7290:
349 case 0x7291:
350 case 0x7293:
351 case 0x7297:
352 caps->family = CHIP_FAMILY_RV560;
353 caps->num_vert_fpus = 5;
354 caps->is_r500 = TRUE;
355 break;
356
357 default:
358 debug_printf("r300: Warning: Unknown chipset 0x%x\n",
359 caps->pci_id);
360 break;
361 }
362 }