src/gallium/drivers/r300/r300_chipset.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  22
  23 #include "r300_chipset.h"
  24
  25 #include "util/u_debug.h"
  26
  27 #include <stdio.h>
  28
  29 /* r300_chipset: A file all to itself for deducing the various properties of
  30  * Radeons. */
  31
  32 /* Parse a PCI ID and fill an r300_capabilities struct with information. */
  33 void r300_parse_chipset(struct r300_capabilities* caps)
  34 {
  35     /* Reasonable defaults */
  36     caps->num_vert_fpus = 2;
  37     caps->num_tex_units = 16;
  38     caps->has_tcl = debug_get_bool_option("RADEON_NO_TCL", FALSE) ? FALSE : TRUE;
  39     caps->hiz_ram = 0;
  40     caps->is_r400 = FALSE;
  41     caps->is_r500 = FALSE;
  42     caps->high_second_pipe = FALSE;
  43
  44     /* Note: These are not ordered by PCI ID. I leave that task to GCC,
  45      * which will perform the ordering while collating jump tables. Instead,
  46      * I've tried to group them according to capabilities and age. */
  47     switch (caps->pci_id) {
  48         case 0x4144:
  49             caps->family = CHIP_FAMILY_R300;
  50             caps->high_second_pipe = TRUE;
  51             caps->num_vert_fpus = 4;
  52             caps->hiz_ram = R300_HIZ_LIMIT;
  53             caps->zmask_ram = PIPE_ZMASK_SIZE;
  54             break;
  55
  56         case 0x4145:
  57         case 0x4146:
  58         case 0x4147:
  59         case 0x4E44:
  60         case 0x4E45:
  61         case 0x4E46:
  62         case 0x4E47:
  63             caps->family = CHIP_FAMILY_R300;
  64             caps->high_second_pipe = TRUE;
  65             caps->num_vert_fpus = 4;
  66             caps->hiz_ram = R300_HIZ_LIMIT;
  67             caps->zmask_ram = PIPE_ZMASK_SIZE;
  68             break;
  69
  70         case 0x4150:
  71         case 0x4151:
  72         case 0x4152:
  73         case 0x4153:
  74         case 0x4154:
  75         case 0x4155:
  76         case 0x4156:
  77         case 0x4E50:
  78         case 0x4E51:
  79         case 0x4E52:
  80         case 0x4E53:
  81         case 0x4E54:
  82         case 0x4E56:
  83             caps->family = CHIP_FAMILY_RV350;
  84             caps->high_second_pipe = TRUE;
  85             caps->zmask_ram = RV3xx_ZMASK_SIZE;
  86             break;
  87
  88         case 0x4148:
  89         case 0x4149:
  90         case 0x414A:
  91         case 0x414B:
  92         case 0x4E48:
  93         case 0x4E49:
  94         case 0x4E4B:
  95             caps->family = CHIP_FAMILY_R350;
  96             caps->high_second_pipe = TRUE;
  97             caps->num_vert_fpus = 4;
  98             caps->hiz_ram = R300_HIZ_LIMIT;
  99             caps->zmask_ram = PIPE_ZMASK_SIZE;
 100             break;
 101
 102         case 0x4E4A:
 103             caps->family = CHIP_FAMILY_R360;
 104             caps->high_second_pipe = TRUE;
 105             caps->num_vert_fpus = 4;
 106             caps->hiz_ram = R300_HIZ_LIMIT;
 107             caps->zmask_ram = PIPE_ZMASK_SIZE;
 108             break;
 109
 110         case 0x5460:
 111         case 0x5462:
 112         case 0x5464:
 113         case 0x5B60:
 114         case 0x5B62:
 115         case 0x5B63:
 116         case 0x5B64:
 117         case 0x5B65:
 118             caps->family = CHIP_FAMILY_RV370;
 119             caps->high_second_pipe = TRUE;
 120             caps->zmask_ram = RV3xx_ZMASK_SIZE;
 121             break;
 122
 123         case 0x3150:
 124         case 0x3152:
 125         case 0x3154:
 126         case 0x3155:
 127         case 0x3E50:
 128         case 0x3E54:
 129             caps->family = CHIP_FAMILY_RV380;
 130             caps->high_second_pipe = TRUE;
 131             caps->hiz_ram = R300_HIZ_LIMIT;
 132             caps->zmask_ram = RV3xx_ZMASK_SIZE;
 133             break;
 134
 135         case 0x4A48:
 136         case 0x4A49:
 137         case 0x4A4A:
 138         case 0x4A4B:
 139         case 0x4A4C:
 140         case 0x4A4D:
 141         case 0x4A4E:
 142         case 0x4A4F:
 143         case 0x4A50:
 144         case 0x4A54:
 145             caps->family = CHIP_FAMILY_R420;
 146             caps->num_vert_fpus = 6;
 147             caps->is_r400 = TRUE;
 148             caps->hiz_ram = R300_HIZ_LIMIT;
 149             caps->zmask_ram = PIPE_ZMASK_SIZE;
 150             break;
 151
 152         case 0x5548:
 153         case 0x5549:
 154         case 0x554A:
 155         case 0x554B:
 156         case 0x5550:
 157         case 0x5551:
 158         case 0x5552:
 159         case 0x5554:
 160         case 0x5D57:
 161             caps->family = CHIP_FAMILY_R423;
 162             caps->num_vert_fpus = 6;
 163             caps->is_r400 = TRUE;
 164             caps->hiz_ram = R300_HIZ_LIMIT;
 165             caps->zmask_ram = PIPE_ZMASK_SIZE;
 166             break;
 167
 168         case 0x554C:
 169         case 0x554D:
 170         case 0x554E:
 171         case 0x554F:
 172         case 0x5D48:
 173         case 0x5D49:
 174         case 0x5D4A:
 175             caps->family = CHIP_FAMILY_R430;
 176             caps->num_vert_fpus = 6;
 177             caps->is_r400 = TRUE;
 178             caps->hiz_ram = R300_HIZ_LIMIT;
 179             caps->zmask_ram = PIPE_ZMASK_SIZE;
 180             break;
 181
 182         case 0x5D4C:
 183         case 0x5D4D:
 184         case 0x5D4E:
 185         case 0x5D4F:
 186         case 0x5D50:
 187         case 0x5D52:
 188             caps->family = CHIP_FAMILY_R480;
 189             caps->num_vert_fpus = 6;
 190             caps->is_r400 = TRUE;
 191             caps->hiz_ram = R300_HIZ_LIMIT;
 192             caps->zmask_ram = PIPE_ZMASK_SIZE;
 193             break;
 194
 195         case 0x4B48:
 196         case 0x4B49:
 197         case 0x4B4A:
 198         case 0x4B4B:
 199         case 0x4B4C:
 200             caps->family = CHIP_FAMILY_R481;
 201             caps->num_vert_fpus = 6;
 202             caps->is_r400 = TRUE;
 203             caps->hiz_ram = R300_HIZ_LIMIT;
 204             caps->zmask_ram = PIPE_ZMASK_SIZE;
 205             break;
 206
 207         case 0x5E4C:
 208         case 0x5E4F:
 209         case 0x564A:
 210         case 0x564B:
 211         case 0x564F:
 212         case 0x5652:
 213         case 0x5653:
 214         case 0x5657:
 215         case 0x5E48:
 216         case 0x5E4A:
 217         case 0x5E4B:
 218         case 0x5E4D:
 219             caps->family = CHIP_FAMILY_RV410;
 220             caps->num_vert_fpus = 6;
 221             caps->is_r400 = TRUE;
 222             caps->hiz_ram = R300_HIZ_LIMIT;
 223             caps->zmask_ram = PIPE_ZMASK_SIZE;
 224             break;
 225
 226         case 0x5954:
 227         case 0x5955:
 228             caps->family = CHIP_FAMILY_RS480;
 229             caps->has_tcl = FALSE;
 230             caps->zmask_ram = RV3xx_ZMASK_SIZE;
 231             break;
 232
 233         case 0x5974:
 234         case 0x5975:
 235             caps->family = CHIP_FAMILY_RS482;
 236             caps->has_tcl = FALSE;
 237             caps->zmask_ram = RV3xx_ZMASK_SIZE;
 238             break;
 239
 240         case 0x5A41:
 241         case 0x5A42:
 242             caps->family = CHIP_FAMILY_RS400;
 243             caps->has_tcl = FALSE;
 244             break;
 245
 246         case 0x5A61:
 247         case 0x5A62:
 248             caps->family = CHIP_FAMILY_RC410;
 249             caps->has_tcl = FALSE;
 250             caps->zmask_ram = RV3xx_ZMASK_SIZE;
 251             break;
 252
 253         case 0x791E:
 254         case 0x791F:
 255             caps->family = CHIP_FAMILY_RS690;
 256             caps->has_tcl = FALSE;
 257             caps->is_r400 = TRUE;
 258             caps->hiz_ram = R300_HIZ_LIMIT;
 259             caps->zmask_ram = PIPE_ZMASK_SIZE;
 260             break;
 261
 262         case 0x793F:
 263         case 0x7941:
 264         case 0x7942:
 265             caps->family = CHIP_FAMILY_RS600;
 266             caps->has_tcl = FALSE;
 267             caps->is_r400 = TRUE;
 268             caps->hiz_ram = R300_HIZ_LIMIT;
 269             caps->zmask_ram = PIPE_ZMASK_SIZE;
 270             break;
 271
 272         case 0x796C:
 273         case 0x796D:
 274         case 0x796E:
 275         case 0x796F:
 276             caps->family = CHIP_FAMILY_RS740;
 277             caps->has_tcl = FALSE;
 278             caps->is_r400 = TRUE;
 279             caps->hiz_ram = R300_HIZ_LIMIT;
 280             caps->zmask_ram = PIPE_ZMASK_SIZE;
 281             break;
 282
 283         case 0x7100:
 284         case 0x7101:
 285         case 0x7102:
 286         case 0x7103:
 287         case 0x7104:
 288         case 0x7105:
 289         case 0x7106:
 290         case 0x7108:
 291         case 0x7109:
 292         case 0x710A:
 293         case 0x710B:
 294         case 0x710C:
 295         case 0x710E:
 296         case 0x710F:
 297             caps->family = CHIP_FAMILY_R520;
 298             caps->num_vert_fpus = 8;
 299             caps->is_r500 = TRUE;
 300             caps->hiz_ram = R300_HIZ_LIMIT;
 301             caps->zmask_ram = PIPE_ZMASK_SIZE;
 302             break;
 303
 304         case 0x7140:
 305         case 0x7141:
 306         case 0x7142:
 307         case 0x7143:
 308         case 0x7144:
 309         case 0x7145:
 310         case 0x7146:
 311         case 0x7147:
 312         case 0x7149:
 313         case 0x714A:
 314         case 0x714B:
 315         case 0x714C:
 316         case 0x714D:
 317         case 0x714E:
 318         case 0x714F:
 319         case 0x7151:
 320         case 0x7152:
 321         case 0x7153:
 322         case 0x715E:
 323         case 0x715F:
 324         case 0x7180:
 325         case 0x7181:
 326         case 0x7183:
 327         case 0x7186:
 328         case 0x7187:
 329         case 0x7188:
 330         case 0x718A:
 331         case 0x718B:
 332         case 0x718C:
 333         case 0x718D:
 334         case 0x718F:
 335         case 0x7193:
 336         case 0x7196:
 337         case 0x719B:
 338         case 0x719F:
 339         case 0x7200:
 340         case 0x7210:
 341         case 0x7211:
 342             caps->family = CHIP_FAMILY_RV515;
 343             caps->num_vert_fpus = 2;
 344             caps->is_r500 = TRUE;
 345             caps->hiz_ram = R300_HIZ_LIMIT;
 346             caps->zmask_ram = PIPE_ZMASK_SIZE;
 347             break;
 348
 349         case 0x71C0:
 350         case 0x71C1:
 351         case 0x71C2:
 352         case 0x71C3:
 353         case 0x71C4:
 354         case 0x71C5:
 355         case 0x71C6:
 356         case 0x71C7:
 357         case 0x71CD:
 358         case 0x71CE:
 359         case 0x71D2:
 360         case 0x71D4:
 361         case 0x71D5:
 362         case 0x71D6:
 363         case 0x71DA:
 364         case 0x71DE:
 365             caps->family = CHIP_FAMILY_RV530;
 366             caps->num_vert_fpus = 5;
 367             caps->is_r500 = TRUE;
 368             caps->hiz_ram = RV530_HIZ_LIMIT;
 369             caps->zmask_ram = PIPE_ZMASK_SIZE;
 370             break;
 371
 372         case 0x7240:
 373         case 0x7243:
 374         case 0x7244:
 375         case 0x7245:
 376         case 0x7246:
 377         case 0x7247:
 378         case 0x7248:
 379         case 0x7249:
 380         case 0x724A:
 381         case 0x724B:
 382         case 0x724C:
 383         case 0x724D:
 384         case 0x724E:
 385         case 0x724F:
 386         case 0x7284:
 387             caps->family = CHIP_FAMILY_R580;
 388             caps->num_vert_fpus = 8;
 389             caps->is_r500 = TRUE;
 390             caps->hiz_ram = RV530_HIZ_LIMIT;
 391             caps->zmask_ram = PIPE_ZMASK_SIZE;
 392             break;
 393
 394         case 0x7280:
 395             caps->family = CHIP_FAMILY_RV570;
 396             caps->num_vert_fpus = 8;
 397             caps->is_r500 = TRUE;
 398             caps->hiz_ram = RV530_HIZ_LIMIT;
 399             caps->zmask_ram = PIPE_ZMASK_SIZE;
 400             break;
 401
 402         case 0x7281:
 403         case 0x7283:
 404         case 0x7287:
 405         case 0x7288:
 406         case 0x7289:
 407         case 0x728B:
 408         case 0x728C:
 409         case 0x7290:
 410         case 0x7291:
 411         case 0x7293:
 412         case 0x7297:
 413             caps->family = CHIP_FAMILY_RV560;
 414             caps->num_vert_fpus = 8;
 415             caps->is_r500 = TRUE;
 416             caps->hiz_ram = RV530_HIZ_LIMIT;
 417             caps->zmask_ram = PIPE_ZMASK_SIZE;
 418             break;
 419
 420         default:
 421             fprintf(stderr, "r300: Warning: Unknown chipset 0x%x\n",
 422                     caps->pci_id);
 423     }
 424
 425     caps->is_rv350 = caps->family >= CHIP_FAMILY_RV350;
 426     caps->z_compress = caps->is_rv350 ? R300_ZCOMP_8X8 : R300_ZCOMP_4X4;
 427     caps->dxtc_swizzle = caps->is_r400 || caps->is_r500;
 428 }