Merge remote-tracking branch 'origin/master' into pipe-video
[mesa.git] / src / gallium / drivers / r300 / r300_chipset.h
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 #ifndef R300_CHIPSET_H
24 #define R300_CHIPSET_H
25
26 #include "pipe/p_compiler.h"
27
28 /* these are sizes in dwords */
29 #define R300_HIZ_LIMIT 10240
30 #define RV530_HIZ_LIMIT 15360
31
32 /* rv3xx have only one pipe */
33 #define PIPE_ZMASK_SIZE 4096
34 #define RV3xx_ZMASK_SIZE 5120
35
36 /* The size of a compressed tile. Each compressed tile takes 2 bits
37 * in the ZMASK RAM, so there is always 16 tiles per one dword. */
38 enum r300_zmask_compression {
39 R300_ZCOMP_4X4 = 4,
40 R300_ZCOMP_8X8 = 8
41 };
42
43 /* Structure containing all the possible information about a specific Radeon
44 * in the R3xx, R4xx, and R5xx families. */
45 struct r300_capabilities {
46 /* PCI ID */
47 uint32_t pci_id;
48 /* Chipset family */
49 int family;
50 /* The number of vertex floating-point units */
51 unsigned num_vert_fpus;
52 /* The number of fragment pipes */
53 unsigned num_frag_pipes;
54 /* The number of z pipes */
55 unsigned num_z_pipes;
56 /* The number of texture units. */
57 unsigned num_tex_units;
58 /* Whether or not TCL is physically present */
59 boolean has_tcl;
60 /* Some chipsets do not have HiZ RAM - other have varying amounts. */
61 int hiz_ram;
62 /* Some chipsets have zmask ram per pipe some don't. */
63 int zmask_ram;
64 /* Compression mode for ZMASK. */
65 enum r300_zmask_compression z_compress;
66 /* Whether or not this is RV350 or newer, including all r400 and r500
67 * chipsets. The differences compared to the oldest r300 chips are:
68 * - Blend LTE/GTE thresholds
69 * - Better MACRO_SWITCH in texture tiling
70 * - Half float vertex
71 * - More HyperZ optimizations */
72 boolean is_rv350;
73 /* Whether or not this is R400. The differences compared their rv350
74 * cousins are:
75 * - Extended fragment shader registers
76 * - 3DC texture compression (RGTC2) */
77 boolean is_r400;
78 /* Whether or not this is an RV515 or newer; R500s have many differences
79 * that require extra consideration, compared to their rv350 cousins:
80 * - Extra bit of width and height on texture sizes
81 * - Blend color is split across two registers
82 * - Universal Shader (US) block used for fragment shaders
83 * - FP16 blending and multisampling
84 * - Full RGTC texture compression
85 * - 24-bit depth textures
86 * - Stencil back-face reference value
87 * - Ability to render up to 2^24 - 1 vertices with signed index offset */
88 boolean is_r500;
89 /* Whether or not the second pixel pipe is accessed with the high bit */
90 boolean high_second_pipe;
91 /* DXTC texture swizzling. */
92 boolean dxtc_swizzle;
93 /* Whether R500_US_FORMAT0_0 exists (R520-only and depends on DRM). */
94 boolean has_us_format;
95 };
96
97 /* Enumerations for legibility and telling which card we're running on. */
98 enum {
99 CHIP_FAMILY_R300 = 0, /* R3xx-based cores. */
100 CHIP_FAMILY_R350,
101 CHIP_FAMILY_RV350,
102 CHIP_FAMILY_RV370,
103 CHIP_FAMILY_RV380,
104 CHIP_FAMILY_RS400,
105 CHIP_FAMILY_RC410,
106 CHIP_FAMILY_RS480,
107 CHIP_FAMILY_R420, /* R4xx-based cores. */
108 CHIP_FAMILY_R423,
109 CHIP_FAMILY_R430,
110 CHIP_FAMILY_R480,
111 CHIP_FAMILY_R481,
112 CHIP_FAMILY_RV410,
113 CHIP_FAMILY_RS600,
114 CHIP_FAMILY_RS690,
115 CHIP_FAMILY_RS740,
116 CHIP_FAMILY_RV515, /* R5xx-based cores. */
117 CHIP_FAMILY_R520,
118 CHIP_FAMILY_RV530,
119 CHIP_FAMILY_R580,
120 CHIP_FAMILY_RV560,
121 CHIP_FAMILY_RV570
122 };
123
124 void r300_parse_chipset(struct r300_capabilities* caps);
125
126 #endif /* R300_CHIPSET_H */