src/gallium/drivers/r300/r300_context.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  22
  23 #include "draw/draw_context.h"
  24
  25 #include "util/u_memory.h"
  26 #include "util/u_sampler.h"
  27 #include "util/u_simple_list.h"
  28 #include "util/u_upload_mgr.h"
  29 #include "os/os_time.h"
  30
  31 #include "r300_cb.h"
  32 #include "r300_context.h"
  33 #include "r300_emit.h"
  34 #include "r300_screen.h"
  35 #include "r300_screen_buffer.h"
  36
  37 static void r300_update_num_contexts(struct r300_screen *r300screen,
  38                                      int diff)
  39 {
  40     pipe_mutex_lock(r300screen->num_contexts_mutex);
  41     if (diff > 0) {
  42         r300screen->num_contexts++;
  43
  44         if (r300screen->num_contexts > 1)
  45             util_slab_set_thread_safety(&r300screen->pool_buffers,
  46                                         UTIL_SLAB_MULTITHREADED);
  47     } else {
  48         r300screen->num_contexts--;
  49
  50         if (r300screen->num_contexts <= 1)
  51             util_slab_set_thread_safety(&r300screen->pool_buffers,
  52                                         UTIL_SLAB_SINGLETHREADED);
  53     }
  54     pipe_mutex_unlock(r300screen->num_contexts_mutex);
  55 }
  56
  57 static void r300_release_referenced_objects(struct r300_context *r300)
  58 {
  59     struct pipe_framebuffer_state *fb =
  60             (struct pipe_framebuffer_state*)r300->fb_state.state;
  61     struct r300_textures_state *textures =
  62             (struct r300_textures_state*)r300->textures_state.state;
  63     struct r300_query *query, *temp;
  64     unsigned i;
  65
  66     /* Framebuffer state. */
  67     util_unreference_framebuffer_state(fb);
  68
  69     /* Textures. */
  70     for (i = 0; i < textures->sampler_view_count; i++)
  71         pipe_sampler_view_reference(
  72                 (struct pipe_sampler_view**)&textures->sampler_views[i], NULL);
  73
  74     /* The special dummy texture for texkill. */
  75     if (r300->texkill_sampler) {
  76         pipe_sampler_view_reference(
  77                 (struct pipe_sampler_view**)&r300->texkill_sampler,
  78                 NULL);
  79     }
  80
  81     /* Manually-created vertex buffers. */
  82     pipe_resource_reference(&r300->dummy_vb, NULL);
  83     pipe_resource_reference(&r300->vbo, NULL);
  84
  85     /* If there are any queries pending or not destroyed, remove them now. */
  86     foreach_s(query, temp, &r300->query_list) {
  87         remove_from_list(query);
  88         FREE(query);
  89     }
  90
  91     r300->context.delete_depth_stencil_alpha_state(&r300->context,
  92                                                    r300->dsa_decompress_zmask);
  93 }
  94
  95 static void r300_destroy_context(struct pipe_context* context)
  96 {
  97     struct r300_context* r300 = r300_context(context);
  98
  99     if (r300->cs && r300->hyperz_enabled) {
 100         r300->rws->cs_request_feature(r300->cs, RADEON_FID_HYPERZ_RAM_ACCESS, FALSE);
 101     }
 102
 103     if (r300->blitter)
 104         util_blitter_destroy(r300->blitter);
 105     if (r300->draw)
 106         draw_destroy(r300->draw);
 107
 108     if (r300->vbuf_mgr)
 109         u_vbuf_mgr_destroy(r300->vbuf_mgr);
 110
 111     /* XXX: This function assumes r300->query_list was initialized */
 112     r300_release_referenced_objects(r300);
 113
 114     if (r300->cs)
 115         r300->rws->cs_destroy(r300->cs);
 116
 117     /* XXX: No way to tell if this was initialized or not? */
 118     util_slab_destroy(&r300->pool_transfers);
 119
 120     r300_update_num_contexts(r300->screen, -1);
 121
 122     /* Free the structs allocated in r300_setup_atoms() */
 123     if (r300->aa_state.state) {
 124         FREE(r300->aa_state.state);
 125         FREE(r300->blend_color_state.state);
 126         FREE(r300->clip_state.state);
 127         FREE(r300->fb_state.state);
 128         FREE(r300->gpu_flush.state);
 129         FREE(r300->hyperz_state.state);
 130         FREE(r300->invariant_state.state);
 131         FREE(r300->rs_block_state.state);
 132         FREE(r300->scissor_state.state);
 133         FREE(r300->textures_state.state);
 134         FREE(r300->vap_invariant_state.state);
 135         FREE(r300->viewport_state.state);
 136         FREE(r300->ztop_state.state);
 137         FREE(r300->fs_constants.state);
 138         FREE(r300->vs_constants.state);
 139         if (!r300->screen->caps.has_tcl) {
 140             FREE(r300->vertex_stream_state.state);
 141         }
 142     }
 143     FREE(r300);
 144 }
 145
 146 static void r300_flush_callback(void *data, unsigned flags)
 147 {
 148     struct r300_context* const cs_context_copy = data;
 149
 150     r300_flush(&cs_context_copy->context, flags, NULL);
 151 }
 152
 153 #define R300_INIT_ATOM(atomname, atomsize) \
 154  do { \
 155     r300->atomname.name = #atomname; \
 156     r300->atomname.state = NULL; \
 157     r300->atomname.size = atomsize; \
 158     r300->atomname.emit = r300_emit_##atomname; \
 159     r300->atomname.dirty = FALSE; \
 160  } while (0)
 161
 162 #define R300_ALLOC_ATOM(atomname, statetype) \
 163 do { \
 164     r300->atomname.state = CALLOC_STRUCT(statetype); \
 165     if (r300->atomname.state == NULL) \
 166         return FALSE; \
 167 } while (0)
 168
 169 static boolean r300_setup_atoms(struct r300_context* r300)
 170 {
 171     boolean is_rv350 = r300->screen->caps.is_rv350;
 172     boolean is_r500 = r300->screen->caps.is_r500;
 173     boolean has_tcl = r300->screen->caps.has_tcl;
 174     boolean drm_2_6_0 = r300->rws->get_value(r300->rws, RADEON_VID_DRM_2_6_0);
 175
 176     /* Create the actual atom list.
 177      *
 178      * Some atoms never change size, others change every emit - those have
 179      * the size of 0 here.
 180      *
 181      * NOTE: The framebuffer state is split into these atoms:
 182      * - gpu_flush          (unpipelined regs)
 183      * - aa_state           (unpipelined regs)
 184      * - fb_state           (unpipelined regs)
 185      * - hyperz_state       (unpipelined regs followed by pipelined ones)
 186      * - fb_state_pipelined (pipelined regs)
 187      * The motivation behind this is to be able to emit a strict
 188      * subset of the regs, and to have reasonable register ordering. */
 189     /* SC, GB (unpipelined), RB3D (unpipelined), ZB (unpipelined). */
 190     R300_INIT_ATOM(gpu_flush, 9);
 191     R300_INIT_ATOM(aa_state, 4);
 192     R300_INIT_ATOM(fb_state, 0);
 193     R300_INIT_ATOM(hyperz_state, is_r500 || (is_rv350 && drm_2_6_0) ? 10 : 8);
 194     /* ZB (unpipelined), SC. */
 195     R300_INIT_ATOM(ztop_state, 2);
 196     /* ZB, FG. */
 197     R300_INIT_ATOM(dsa_state, is_r500 ? (drm_2_6_0 ? 10 : 8) : 6);
 198     /* RB3D. */
 199     R300_INIT_ATOM(blend_state, 8);
 200     R300_INIT_ATOM(blend_color_state, is_r500 ? 3 : 2);
 201     /* SC. */
 202     R300_INIT_ATOM(scissor_state, 3);
 203     /* GB, FG, GA, SU, SC, RB3D. */
 204     R300_INIT_ATOM(invariant_state, 16 + (is_rv350 ? 4 : 0) + (is_r500 ? 4 : 0));
 205     /* VAP. */
 206     R300_INIT_ATOM(viewport_state, 9);
 207     R300_INIT_ATOM(pvs_flush, 2);
 208     R300_INIT_ATOM(vap_invariant_state, is_r500 ? 11 : 9);
 209     R300_INIT_ATOM(vertex_stream_state, 0);
 210     R300_INIT_ATOM(vs_state, 0);
 211     R300_INIT_ATOM(vs_constants, 0);
 212     R300_INIT_ATOM(clip_state, has_tcl ? 5 + (6 * 4) : 2);
 213     /* VAP, RS, GA, GB, SU, SC. */
 214     R300_INIT_ATOM(rs_block_state, 0);
 215     R300_INIT_ATOM(rs_state, 0);
 216     /* SC, US. */
 217     R300_INIT_ATOM(fb_state_pipelined, 8);
 218     /* US. */
 219     R300_INIT_ATOM(fs, 0);
 220     R300_INIT_ATOM(fs_rc_constant_state, 0);
 221     R300_INIT_ATOM(fs_constants, 0);
 222     /* TX. */
 223     R300_INIT_ATOM(texture_cache_inval, 2);
 224     R300_INIT_ATOM(textures_state, 0);
 225     /* HiZ Clear */
 226     R300_INIT_ATOM(hiz_clear, r300->screen->caps.hiz_ram > 0 ? 4 : 0);
 227     /* zmask clear */
 228     R300_INIT_ATOM(zmask_clear, r300->screen->caps.zmask_ram > 0 ? 4 : 0);
 229     /* ZB (unpipelined), SU. */
 230     R300_INIT_ATOM(query_start, 4);
 231
 232     /* Replace emission functions for r500. */
 233     if (is_r500) {
 234         r300->fs.emit = r500_emit_fs;
 235         r300->fs_rc_constant_state.emit = r500_emit_fs_rc_constant_state;
 236         r300->fs_constants.emit = r500_emit_fs_constants;
 237     }
 238
 239     /* Some non-CSO atoms need explicit space to store the state locally. */
 240     R300_ALLOC_ATOM(aa_state, r300_aa_state);
 241     R300_ALLOC_ATOM(blend_color_state, r300_blend_color_state);
 242     R300_ALLOC_ATOM(clip_state, r300_clip_state);
 243     R300_ALLOC_ATOM(hyperz_state, r300_hyperz_state);
 244     R300_ALLOC_ATOM(invariant_state, r300_invariant_state);
 245     R300_ALLOC_ATOM(textures_state, r300_textures_state);
 246     R300_ALLOC_ATOM(vap_invariant_state, r300_vap_invariant_state);
 247     R300_ALLOC_ATOM(viewport_state, r300_viewport_state);
 248     R300_ALLOC_ATOM(ztop_state, r300_ztop_state);
 249     R300_ALLOC_ATOM(fb_state, pipe_framebuffer_state);
 250     R300_ALLOC_ATOM(gpu_flush, pipe_framebuffer_state);
 251     R300_ALLOC_ATOM(scissor_state, pipe_scissor_state);
 252     R300_ALLOC_ATOM(rs_block_state, r300_rs_block);
 253     R300_ALLOC_ATOM(fs_constants, r300_constant_buffer);
 254     R300_ALLOC_ATOM(vs_constants, r300_constant_buffer);
 255     if (!r300->screen->caps.has_tcl) {
 256         R300_ALLOC_ATOM(vertex_stream_state, r300_vertex_stream_state);
 257     }
 258
 259     /* Some non-CSO atoms don't use the state pointer. */
 260     r300->fb_state_pipelined.allow_null_state = TRUE;
 261     r300->fs_rc_constant_state.allow_null_state = TRUE;
 262     r300->pvs_flush.allow_null_state = TRUE;
 263     r300->query_start.allow_null_state = TRUE;
 264     r300->texture_cache_inval.allow_null_state = TRUE;
 265
 266     /* Some states must be marked as dirty here to properly set up
 267      * hardware in the first command stream. */
 268     r300_mark_atom_dirty(r300, &r300->invariant_state);
 269     r300_mark_atom_dirty(r300, &r300->pvs_flush);
 270     r300_mark_atom_dirty(r300, &r300->vap_invariant_state);
 271     r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
 272     r300_mark_atom_dirty(r300, &r300->textures_state);
 273
 274     return TRUE;
 275 }
 276
 277 /* Not every state tracker calls every driver function before the first draw
 278  * call and we must initialize the command buffers somehow. */
 279 static void r300_init_states(struct pipe_context *pipe)
 280 {
 281     struct r300_context *r300 = r300_context(pipe);
 282     struct pipe_blend_color bc = {{0}};
 283     struct pipe_clip_state cs = {{{0}}};
 284     struct pipe_scissor_state ss = {0};
 285     struct r300_clip_state *clip =
 286             (struct r300_clip_state*)r300->clip_state.state;
 287     struct r300_gpu_flush *gpuflush =
 288             (struct r300_gpu_flush*)r300->gpu_flush.state;
 289     struct r300_vap_invariant_state *vap_invariant =
 290             (struct r300_vap_invariant_state*)r300->vap_invariant_state.state;
 291     struct r300_invariant_state *invariant =
 292             (struct r300_invariant_state*)r300->invariant_state.state;
 293
 294     CB_LOCALS;
 295
 296     pipe->set_blend_color(pipe, &bc);
 297     pipe->set_scissor_state(pipe, &ss);
 298
 299     /* Initialize the clip state. */
 300     if (r300->screen->caps.has_tcl) {
 301         pipe->set_clip_state(pipe, &cs);
 302     } else {
 303         BEGIN_CB(clip->cb, 2);
 304         OUT_CB_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
 305         END_CB;
 306     }
 307
 308     /* Initialize the GPU flush. */
 309     {
 310         BEGIN_CB(gpuflush->cb_flush_clean, 6);
 311
 312         /* Flush and free renderbuffer caches. */
 313         OUT_CB_REG(R300_RB3D_DSTCACHE_CTLSTAT,
 314             R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
 315             R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 316         OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
 317             R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 318             R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
 319
 320         /* Wait until the GPU is idle.
 321          * This fixes random pixels sometimes appearing probably caused
 322          * by incomplete rendering. */
 323         OUT_CB_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
 324         END_CB;
 325     }
 326
 327     /* Initialize the VAP invariant state. */
 328     {
 329         BEGIN_CB(vap_invariant->cb, r300->vap_invariant_state.size);
 330         OUT_CB_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
 331         OUT_CB_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
 332         OUT_CB_32F(1.0);
 333         OUT_CB_32F(1.0);
 334         OUT_CB_32F(1.0);
 335         OUT_CB_32F(1.0);
 336         OUT_CB_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
 337
 338         if (r300->screen->caps.is_r500) {
 339             OUT_CB_REG(R500_VAP_TEX_TO_COLOR_CNTL, 0);
 340         }
 341         END_CB;
 342     }
 343
 344     /* Initialize the invariant state. */
 345     {
 346         BEGIN_CB(invariant->cb, r300->invariant_state.size);
 347         OUT_CB_REG(R300_GB_SELECT, 0);
 348         OUT_CB_REG(R300_FG_FOG_BLEND, 0);
 349         OUT_CB_REG(R300_GA_OFFSET, 0);
 350         OUT_CB_REG(R300_SU_TEX_WRAP, 0);
 351         OUT_CB_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
 352         OUT_CB_REG(R300_SU_DEPTH_OFFSET, 0);
 353         OUT_CB_REG(R300_SC_EDGERULE, 0x2DA49525);
 354         OUT_CB_REG(R300_SC_SCREENDOOR, 0xffffff);
 355
 356         if (r300->screen->caps.is_rv350) {
 357             OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x01010101);
 358             OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFEFEFEFE);
 359         }
 360
 361         if (r300->screen->caps.is_r500) {
 362             OUT_CB_REG(R500_GA_COLOR_CONTROL_PS3, 0);
 363             OUT_CB_REG(R500_SU_TEX_WRAP_PS3, 0);
 364         }
 365         END_CB;
 366     }
 367
 368     /* Initialize the hyperz state. */
 369     {
 370         struct r300_hyperz_state *hyperz =
 371             (struct r300_hyperz_state*)r300->hyperz_state.state;
 372         BEGIN_CB(&hyperz->cb_flush_begin, r300->hyperz_state.size);
 373         OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
 374                    R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 375         OUT_CB_REG(R300_ZB_BW_CNTL, 0);
 376         OUT_CB_REG(R300_ZB_DEPTHCLEARVALUE, 0);
 377         OUT_CB_REG(R300_SC_HYPERZ, R300_SC_HYPERZ_ADJ_2);
 378
 379         if (r300->screen->caps.is_r500 ||
 380             (r300->screen->caps.is_rv350 &&
 381              r300->rws->get_value(r300->rws, RADEON_VID_DRM_2_6_0))) {
 382             OUT_CB_REG(R300_GB_Z_PEQ_CONFIG, 0);
 383         }
 384         END_CB;
 385     }
 386 }
 387
 388 struct pipe_context* r300_create_context(struct pipe_screen* screen,
 389                                          void *priv)
 390 {
 391     struct r300_context* r300 = CALLOC_STRUCT(r300_context);
 392     struct r300_screen* r300screen = r300_screen(screen);
 393     struct radeon_winsys *rws = r300screen->rws;
 394
 395     if (!r300)
 396         return NULL;
 397
 398     r300_update_num_contexts(r300screen, 1);
 399
 400     r300->rws = rws;
 401     r300->screen = r300screen;
 402
 403     r300->context.winsys = (struct pipe_winsys*)rws;
 404     r300->context.screen = screen;
 405     r300->context.priv = priv;
 406
 407     r300->context.destroy = r300_destroy_context;
 408
 409     make_empty_list(&r300->query_list);
 410
 411     util_slab_create(&r300->pool_transfers,
 412                      sizeof(struct pipe_transfer), 64,
 413                      UTIL_SLAB_SINGLETHREADED);
 414
 415     r300->cs = rws->cs_create(rws);
 416     if (r300->cs == NULL)
 417         goto fail;
 418
 419     if (!r300screen->caps.has_tcl) {
 420         /* Create a Draw. This is used for SW TCL. */
 421         r300->draw = draw_create(&r300->context);
 422         if (r300->draw == NULL)
 423             goto fail;
 424         /* Enable our renderer. */
 425         draw_set_rasterize_stage(r300->draw, r300_draw_stage(r300));
 426         /* Disable converting points/lines to triangles. */
 427         draw_wide_line_threshold(r300->draw, 10000000.f);
 428         draw_wide_point_threshold(r300->draw, 10000000.f);
 429     }
 430
 431     if (!r300_setup_atoms(r300))
 432         goto fail;
 433
 434     r300_init_blit_functions(r300);
 435     r300_init_flush_functions(r300);
 436     r300_init_query_functions(r300);
 437     r300_init_state_functions(r300);
 438     r300_init_resource_functions(r300);
 439
 440     r300->vbuf_mgr = u_vbuf_mgr_create(&r300->context, 1024 * 1024, 16,
 441                                        PIPE_BIND_VERTEX_BUFFER |
 442                                        PIPE_BIND_INDEX_BUFFER,
 443                                        U_VERTEX_FETCH_DWORD_ALIGNED);
 444     if (!r300->vbuf_mgr)
 445         goto fail;
 446
 447     r300->blitter = util_blitter_create(&r300->context);
 448     if (r300->blitter == NULL)
 449         goto fail;
 450
 451     /* Render functions must be initialized after blitter. */
 452     r300_init_render_functions(r300);
 453     r300_init_states(&r300->context);
 454
 455     rws->cs_set_flush(r300->cs, r300_flush_callback, r300);
 456
 457     /* The KIL opcode needs the first texture unit to be enabled
 458      * on r3xx-r4xx. In order to calm down the CS checker, we bind this
 459      * dummy texture there. */
 460     if (!r300->screen->caps.is_r500) {
 461         struct pipe_resource *tex;
 462         struct pipe_resource rtempl = {{0}};
 463         struct pipe_sampler_view vtempl = {{0}};
 464
 465         rtempl.target = PIPE_TEXTURE_2D;
 466         rtempl.format = PIPE_FORMAT_I8_UNORM;
 467         rtempl.bind = PIPE_BIND_SAMPLER_VIEW;
 468         rtempl.usage = PIPE_USAGE_IMMUTABLE;
 469         rtempl.width0 = 1;
 470         rtempl.height0 = 1;
 471         rtempl.depth0 = 1;
 472         tex = screen->resource_create(screen, &rtempl);
 473
 474         u_sampler_view_default_template(&vtempl, tex, tex->format);
 475
 476         r300->texkill_sampler = (struct r300_sampler_view*)
 477             r300->context.create_sampler_view(&r300->context, tex, &vtempl);
 478
 479         pipe_resource_reference(&tex, NULL);
 480     }
 481
 482     {
 483         struct pipe_resource vb;
 484         memset(&vb, 0, sizeof(vb));
 485         vb.target = PIPE_BUFFER;
 486         vb.format = PIPE_FORMAT_R8_UNORM;
 487         vb.bind = PIPE_BIND_VERTEX_BUFFER;
 488         vb.usage = PIPE_USAGE_IMMUTABLE;
 489         vb.width0 = sizeof(float) * 16;
 490         vb.height0 = 1;
 491         vb.depth0 = 1;
 492
 493         r300->dummy_vb = screen->resource_create(screen, &vb);
 494     }
 495
 496     {
 497         struct pipe_depth_stencil_alpha_state dsa;
 498         memset(&dsa, 0, sizeof(dsa));
 499         dsa.depth.writemask = 1;
 500
 501         r300->dsa_decompress_zmask =
 502             r300->context.create_depth_stencil_alpha_state(&r300->context,
 503                                                            &dsa);
 504     }
 505
 506     r300->hyperz_time_of_last_flush = os_time_get();
 507
 508     /* Print driver info. */
 509 #ifdef DEBUG
 510     {
 511 #else
 512     if (DBG_ON(r300, DBG_INFO)) {
 513 #endif
 514         fprintf(stderr,
 515                 "r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
 516                 "r300: GART size: %d MB, VRAM size: %d MB\n"
 517                 "r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
 518                 rws->get_value(rws, RADEON_VID_DRM_MAJOR),
 519                 rws->get_value(rws, RADEON_VID_DRM_MINOR),
 520                 rws->get_value(rws, RADEON_VID_DRM_PATCHLEVEL),
 521                 screen->get_name(screen),
 522                 rws->get_value(rws, RADEON_VID_PCI_ID),
 523                 rws->get_value(rws, RADEON_VID_R300_GB_PIPES),
 524                 rws->get_value(rws, RADEON_VID_R300_Z_PIPES),
 525                 rws->get_value(rws, RADEON_VID_GART_SIZE) >> 20,
 526                 rws->get_value(rws, RADEON_VID_VRAM_SIZE) >> 20,
 527                 "YES", /* XXX really? */
 528                 r300->screen->caps.zmask_ram ? "YES" : "NO",
 529                 r300->screen->caps.hiz_ram ? "YES" : "NO");
 530     }
 531
 532     return &r300->context;
 533
 534 fail:
 535     r300_destroy_context(&r300->context);
 536     return NULL;
 537 }