2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23 #include "draw/draw_context.h"
25 #include "util/u_memory.h"
26 #include "util/u_sampler.h"
27 #include "util/u_simple_list.h"
28 #include "util/u_upload_mgr.h"
29 #include "os/os_time.h"
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
34 #include "r300_context.h"
35 #include "r300_emit.h"
36 #include "r300_screen.h"
37 #include "r300_screen_buffer.h"
38 #include "compiler/radeon_regalloc.h"
40 static void r300_release_referenced_objects(struct r300_context
*r300
)
42 struct pipe_framebuffer_state
*fb
=
43 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
44 struct r300_textures_state
*textures
=
45 (struct r300_textures_state
*)r300
->textures_state
.state
;
48 /* Framebuffer state. */
49 util_unreference_framebuffer_state(fb
);
52 for (i
= 0; i
< textures
->sampler_view_count
; i
++)
53 pipe_sampler_view_reference(
54 (struct pipe_sampler_view
**)&textures
->sampler_views
[i
], NULL
);
56 /* The special dummy texture for texkill. */
57 if (r300
->texkill_sampler
) {
58 pipe_sampler_view_reference(
59 (struct pipe_sampler_view
**)&r300
->texkill_sampler
,
63 /* Manually-created vertex buffers. */
64 pipe_resource_reference(&r300
->dummy_vb
.buffer
, NULL
);
65 pb_reference(&r300
->vbo
, NULL
);
67 r300
->context
.delete_depth_stencil_alpha_state(&r300
->context
,
68 r300
->dsa_decompress_zmask
);
71 static void r300_destroy_context(struct pipe_context
* context
)
73 struct r300_context
* r300
= r300_context(context
);
75 if (r300
->cs
&& r300
->hyperz_enabled
) {
76 r300
->rws
->cs_request_feature(r300
->cs
, RADEON_FID_R300_HYPERZ_ACCESS
, FALSE
);
78 if (r300
->cs
&& r300
->cmask_access
) {
79 r300
->rws
->cs_request_feature(r300
->cs
, RADEON_FID_R300_CMASK_ACCESS
, FALSE
);
83 util_blitter_destroy(r300
->blitter
);
85 draw_destroy(r300
->draw
);
88 u_upload_destroy(r300
->uploader
);
90 /* XXX: This function assumes r300->query_list was initialized */
91 r300_release_referenced_objects(r300
);
94 r300
->rws
->cs_destroy(r300
->cs
);
96 rc_destroy_regalloc_state(&r300
->fs_regalloc_state
);
98 /* XXX: No way to tell if this was initialized or not? */
99 util_slab_destroy(&r300
->pool_transfers
);
101 /* Free the structs allocated in r300_setup_atoms() */
102 if (r300
->aa_state
.state
) {
103 FREE(r300
->aa_state
.state
);
104 FREE(r300
->blend_color_state
.state
);
105 FREE(r300
->clip_state
.state
);
106 FREE(r300
->fb_state
.state
);
107 FREE(r300
->gpu_flush
.state
);
108 FREE(r300
->hyperz_state
.state
);
109 FREE(r300
->invariant_state
.state
);
110 FREE(r300
->rs_block_state
.state
);
111 FREE(r300
->sample_mask
.state
);
112 FREE(r300
->scissor_state
.state
);
113 FREE(r300
->textures_state
.state
);
114 FREE(r300
->vap_invariant_state
.state
);
115 FREE(r300
->viewport_state
.state
);
116 FREE(r300
->ztop_state
.state
);
117 FREE(r300
->fs_constants
.state
);
118 FREE(r300
->vs_constants
.state
);
119 if (!r300
->screen
->caps
.has_tcl
) {
120 FREE(r300
->vertex_stream_state
.state
);
126 static void r300_flush_callback(void *data
, unsigned flags
)
128 struct r300_context
* const cs_context_copy
= data
;
130 r300_flush(&cs_context_copy
->context
, flags
, NULL
);
133 #define R300_INIT_ATOM(atomname, atomsize) \
135 r300->atomname.name = #atomname; \
136 r300->atomname.state = NULL; \
137 r300->atomname.size = atomsize; \
138 r300->atomname.emit = r300_emit_##atomname; \
139 r300->atomname.dirty = FALSE; \
142 #define R300_ALLOC_ATOM(atomname, statetype) \
144 r300->atomname.state = CALLOC_STRUCT(statetype); \
145 if (r300->atomname.state == NULL) \
149 static boolean
r300_setup_atoms(struct r300_context
* r300
)
151 boolean is_rv350
= r300
->screen
->caps
.is_rv350
;
152 boolean is_r500
= r300
->screen
->caps
.is_r500
;
153 boolean has_tcl
= r300
->screen
->caps
.has_tcl
;
154 boolean drm_2_6_0
= r300
->screen
->info
.drm_minor
>= 6;
156 /* Create the actual atom list.
158 * Some atoms never change size, others change every emit - those have
159 * the size of 0 here.
161 * NOTE: The framebuffer state is split into these atoms:
162 * - gpu_flush (unpipelined regs)
163 * - aa_state (unpipelined regs)
164 * - fb_state (unpipelined regs)
165 * - hyperz_state (unpipelined regs followed by pipelined ones)
166 * - fb_state_pipelined (pipelined regs)
167 * The motivation behind this is to be able to emit a strict
168 * subset of the regs, and to have reasonable register ordering. */
169 /* SC, GB (unpipelined), RB3D (unpipelined), ZB (unpipelined). */
170 R300_INIT_ATOM(gpu_flush
, 9);
171 R300_INIT_ATOM(aa_state
, 4);
172 R300_INIT_ATOM(fb_state
, 0);
173 R300_INIT_ATOM(hyperz_state
, is_r500
|| (is_rv350
&& drm_2_6_0
) ? 10 : 8);
174 /* ZB (unpipelined), SC. */
175 R300_INIT_ATOM(ztop_state
, 2);
177 R300_INIT_ATOM(dsa_state
, is_r500
? (drm_2_6_0
? 10 : 8) : 6);
179 R300_INIT_ATOM(blend_state
, 8);
180 R300_INIT_ATOM(blend_color_state
, is_r500
? 3 : 2);
182 R300_INIT_ATOM(sample_mask
, 2);
183 R300_INIT_ATOM(scissor_state
, 3);
184 /* GB, FG, GA, SU, SC, RB3D. */
185 R300_INIT_ATOM(invariant_state
, 14 + (is_rv350
? 4 : 0) + (is_r500
? 4 : 0));
187 R300_INIT_ATOM(viewport_state
, 9);
188 R300_INIT_ATOM(pvs_flush
, 2);
189 R300_INIT_ATOM(vap_invariant_state
, is_r500
? 11 : 9);
190 R300_INIT_ATOM(vertex_stream_state
, 0);
191 R300_INIT_ATOM(vs_state
, 0);
192 R300_INIT_ATOM(vs_constants
, 0);
193 R300_INIT_ATOM(clip_state
, has_tcl
? 3 + (6 * 4) : 0);
194 /* VAP, RS, GA, GB, SU, SC. */
195 R300_INIT_ATOM(rs_block_state
, 0);
196 R300_INIT_ATOM(rs_state
, 0);
198 R300_INIT_ATOM(fb_state_pipelined
, 8);
200 R300_INIT_ATOM(fs
, 0);
201 R300_INIT_ATOM(fs_rc_constant_state
, 0);
202 R300_INIT_ATOM(fs_constants
, 0);
204 R300_INIT_ATOM(texture_cache_inval
, 2);
205 R300_INIT_ATOM(textures_state
, 0);
207 R300_INIT_ATOM(hiz_clear
, r300
->screen
->caps
.hiz_ram
> 0 ? 4 : 0);
208 R300_INIT_ATOM(zmask_clear
, r300
->screen
->caps
.zmask_ram
> 0 ? 4 : 0);
209 R300_INIT_ATOM(cmask_clear
, 4);
210 /* ZB (unpipelined), SU. */
211 R300_INIT_ATOM(query_start
, 4);
213 /* Replace emission functions for r500. */
215 r300
->fs
.emit
= r500_emit_fs
;
216 r300
->fs_rc_constant_state
.emit
= r500_emit_fs_rc_constant_state
;
217 r300
->fs_constants
.emit
= r500_emit_fs_constants
;
220 /* Some non-CSO atoms need explicit space to store the state locally. */
221 R300_ALLOC_ATOM(aa_state
, r300_aa_state
);
222 R300_ALLOC_ATOM(blend_color_state
, r300_blend_color_state
);
223 R300_ALLOC_ATOM(clip_state
, r300_clip_state
);
224 R300_ALLOC_ATOM(hyperz_state
, r300_hyperz_state
);
225 R300_ALLOC_ATOM(invariant_state
, r300_invariant_state
);
226 R300_ALLOC_ATOM(textures_state
, r300_textures_state
);
227 R300_ALLOC_ATOM(vap_invariant_state
, r300_vap_invariant_state
);
228 R300_ALLOC_ATOM(viewport_state
, r300_viewport_state
);
229 R300_ALLOC_ATOM(ztop_state
, r300_ztop_state
);
230 R300_ALLOC_ATOM(fb_state
, pipe_framebuffer_state
);
231 R300_ALLOC_ATOM(gpu_flush
, pipe_framebuffer_state
);
232 r300
->sample_mask
.state
= malloc(4);
233 R300_ALLOC_ATOM(scissor_state
, pipe_scissor_state
);
234 R300_ALLOC_ATOM(rs_block_state
, r300_rs_block
);
235 R300_ALLOC_ATOM(fs_constants
, r300_constant_buffer
);
236 R300_ALLOC_ATOM(vs_constants
, r300_constant_buffer
);
237 if (!r300
->screen
->caps
.has_tcl
) {
238 R300_ALLOC_ATOM(vertex_stream_state
, r300_vertex_stream_state
);
241 /* Some non-CSO atoms don't use the state pointer. */
242 r300
->fb_state_pipelined
.allow_null_state
= TRUE
;
243 r300
->fs_rc_constant_state
.allow_null_state
= TRUE
;
244 r300
->pvs_flush
.allow_null_state
= TRUE
;
245 r300
->query_start
.allow_null_state
= TRUE
;
246 r300
->texture_cache_inval
.allow_null_state
= TRUE
;
248 /* Some states must be marked as dirty here to properly set up
249 * hardware in the first command stream. */
250 r300_mark_atom_dirty(r300
, &r300
->invariant_state
);
251 r300_mark_atom_dirty(r300
, &r300
->pvs_flush
);
252 r300_mark_atom_dirty(r300
, &r300
->vap_invariant_state
);
253 r300_mark_atom_dirty(r300
, &r300
->texture_cache_inval
);
254 r300_mark_atom_dirty(r300
, &r300
->textures_state
);
259 /* Not every state tracker calls every driver function before the first draw
260 * call and we must initialize the command buffers somehow. */
261 static void r300_init_states(struct pipe_context
*pipe
)
263 struct r300_context
*r300
= r300_context(pipe
);
264 struct pipe_blend_color bc
= {{0}};
265 struct pipe_clip_state cs
= {{{0}}};
266 struct pipe_scissor_state ss
= {0};
267 struct r300_gpu_flush
*gpuflush
=
268 (struct r300_gpu_flush
*)r300
->gpu_flush
.state
;
269 struct r300_vap_invariant_state
*vap_invariant
=
270 (struct r300_vap_invariant_state
*)r300
->vap_invariant_state
.state
;
271 struct r300_invariant_state
*invariant
=
272 (struct r300_invariant_state
*)r300
->invariant_state
.state
;
276 pipe
->set_blend_color(pipe
, &bc
);
277 pipe
->set_clip_state(pipe
, &cs
);
278 pipe
->set_scissor_states(pipe
, 0, 1, &ss
);
279 pipe
->set_sample_mask(pipe
, ~0);
281 /* Initialize the GPU flush. */
283 BEGIN_CB(gpuflush
->cb_flush_clean
, 6);
285 /* Flush and free renderbuffer caches. */
286 OUT_CB_REG(R300_RB3D_DSTCACHE_CTLSTAT
,
287 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS
|
288 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
289 OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT
,
290 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
291 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
293 /* Wait until the GPU is idle.
294 * This fixes random pixels sometimes appearing probably caused
295 * by incomplete rendering. */
296 OUT_CB_REG(RADEON_WAIT_UNTIL
, RADEON_WAIT_3D_IDLECLEAN
);
300 /* Initialize the VAP invariant state. */
302 BEGIN_CB(vap_invariant
->cb
, r300
->vap_invariant_state
.size
);
303 OUT_CB_REG(VAP_PVS_VTX_TIMEOUT_REG
, 0xffff);
304 OUT_CB_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ
, 4);
309 OUT_CB_REG(R300_VAP_PSC_SGN_NORM_CNTL
, R300_SGN_NORM_NO_ZERO
);
311 if (r300
->screen
->caps
.is_r500
) {
312 OUT_CB_REG(R500_VAP_TEX_TO_COLOR_CNTL
, 0);
317 /* Initialize the invariant state. */
319 BEGIN_CB(invariant
->cb
, r300
->invariant_state
.size
);
320 OUT_CB_REG(R300_GB_SELECT
, 0);
321 OUT_CB_REG(R300_FG_FOG_BLEND
, 0);
322 OUT_CB_REG(R300_GA_OFFSET
, 0);
323 OUT_CB_REG(R300_SU_TEX_WRAP
, 0);
324 OUT_CB_REG(R300_SU_DEPTH_SCALE
, 0x4B7FFFFF);
325 OUT_CB_REG(R300_SU_DEPTH_OFFSET
, 0);
326 OUT_CB_REG(R300_SC_EDGERULE
, 0x2DA49525);
328 if (r300
->screen
->caps
.is_rv350
) {
329 OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
, 0x01010101);
330 OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
, 0xFEFEFEFE);
333 if (r300
->screen
->caps
.is_r500
) {
334 OUT_CB_REG(R500_GA_COLOR_CONTROL_PS3
, 0);
335 OUT_CB_REG(R500_SU_TEX_WRAP_PS3
, 0);
340 /* Initialize the hyperz state. */
342 struct r300_hyperz_state
*hyperz
=
343 (struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
344 BEGIN_CB(&hyperz
->cb_flush_begin
, r300
->hyperz_state
.size
);
345 OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT
,
346 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
);
347 OUT_CB_REG(R300_ZB_BW_CNTL
, 0);
348 OUT_CB_REG(R300_ZB_DEPTHCLEARVALUE
, 0);
349 OUT_CB_REG(R300_SC_HYPERZ
, R300_SC_HYPERZ_ADJ_2
);
351 if (r300
->screen
->caps
.is_r500
||
352 (r300
->screen
->caps
.is_rv350
&&
353 r300
->screen
->info
.drm_minor
>= 6)) {
354 OUT_CB_REG(R300_GB_Z_PEQ_CONFIG
, 0);
360 struct pipe_context
* r300_create_context(struct pipe_screen
* screen
,
363 struct r300_context
* r300
= CALLOC_STRUCT(r300_context
);
364 struct r300_screen
* r300screen
= r300_screen(screen
);
365 struct radeon_winsys
*rws
= r300screen
->rws
;
371 r300
->screen
= r300screen
;
373 r300
->context
.screen
= screen
;
374 r300
->context
.priv
= priv
;
376 r300
->context
.destroy
= r300_destroy_context
;
378 util_slab_create(&r300
->pool_transfers
,
379 sizeof(struct pipe_transfer
), 64,
380 UTIL_SLAB_SINGLETHREADED
);
382 r300
->cs
= rws
->cs_create(rws
, RING_GFX
, NULL
);
383 if (r300
->cs
== NULL
)
386 if (!r300screen
->caps
.has_tcl
) {
387 /* Create a Draw. This is used for SW TCL. */
388 r300
->draw
= draw_create(&r300
->context
);
389 if (r300
->draw
== NULL
)
391 /* Enable our renderer. */
392 draw_set_rasterize_stage(r300
->draw
, r300_draw_stage(r300
));
393 /* Disable converting points/lines to triangles. */
394 draw_wide_line_threshold(r300
->draw
, 10000000.f
);
395 draw_wide_point_threshold(r300
->draw
, 10000000.f
);
396 draw_wide_point_sprites(r300
->draw
, FALSE
);
397 draw_enable_line_stipple(r300
->draw
, TRUE
);
398 draw_enable_point_sprites(r300
->draw
, FALSE
);
401 if (!r300_setup_atoms(r300
))
404 r300_init_blit_functions(r300
);
405 r300_init_flush_functions(r300
);
406 r300_init_query_functions(r300
);
407 r300_init_state_functions(r300
);
408 r300_init_resource_functions(r300
);
409 r300_init_render_functions(r300
);
410 r300_init_states(&r300
->context
);
412 r300
->context
.create_video_codec
= vl_create_decoder
;
413 r300
->context
.create_video_buffer
= vl_video_buffer_create
;
415 r300
->uploader
= u_upload_create(&r300
->context
, 256 * 1024, 4,
418 r300
->blitter
= util_blitter_create(&r300
->context
);
419 if (r300
->blitter
== NULL
)
421 r300
->blitter
->draw_rectangle
= r300_blitter_draw_rectangle
;
423 rws
->cs_set_flush_callback(r300
->cs
, r300_flush_callback
, r300
);
425 /* The KIL opcode needs the first texture unit to be enabled
426 * on r3xx-r4xx. In order to calm down the CS checker, we bind this
427 * dummy texture there. */
428 if (!r300
->screen
->caps
.is_r500
) {
429 struct pipe_resource
*tex
;
430 struct pipe_resource rtempl
= {{0}};
431 struct pipe_sampler_view vtempl
= {{0}};
433 rtempl
.target
= PIPE_TEXTURE_2D
;
434 rtempl
.format
= PIPE_FORMAT_I8_UNORM
;
435 rtempl
.usage
= PIPE_USAGE_IMMUTABLE
;
439 tex
= screen
->resource_create(screen
, &rtempl
);
441 u_sampler_view_default_template(&vtempl
, tex
, tex
->format
);
443 r300
->texkill_sampler
= (struct r300_sampler_view
*)
444 r300
->context
.create_sampler_view(&r300
->context
, tex
, &vtempl
);
446 pipe_resource_reference(&tex
, NULL
);
449 if (r300screen
->caps
.has_tcl
) {
450 struct pipe_resource vb
;
451 memset(&vb
, 0, sizeof(vb
));
452 vb
.target
= PIPE_BUFFER
;
453 vb
.format
= PIPE_FORMAT_R8_UNORM
;
454 vb
.usage
= PIPE_USAGE_STATIC
;
455 vb
.width0
= sizeof(float) * 16;
459 r300
->dummy_vb
.buffer
= screen
->resource_create(screen
, &vb
);
460 r300
->context
.set_vertex_buffers(&r300
->context
, 0, 1, &r300
->dummy_vb
);
464 struct pipe_depth_stencil_alpha_state dsa
;
465 memset(&dsa
, 0, sizeof(dsa
));
466 dsa
.depth
.writemask
= 1;
468 r300
->dsa_decompress_zmask
=
469 r300
->context
.create_depth_stencil_alpha_state(&r300
->context
,
473 r300
->hyperz_time_of_last_flush
= os_time_get();
475 /* Register allocator state */
476 rc_init_regalloc_state(&r300
->fs_regalloc_state
);
478 /* Print driver info. */
482 if (DBG_ON(r300
, DBG_INFO
)) {
485 "r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
486 "r300: GART size: %d MB, VRAM size: %d MB\n"
487 "r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
488 r300
->screen
->info
.drm_major
,
489 r300
->screen
->info
.drm_minor
,
490 r300
->screen
->info
.drm_patchlevel
,
491 screen
->get_name(screen
),
492 r300
->screen
->info
.pci_id
,
493 r300
->screen
->info
.r300_num_gb_pipes
,
494 r300
->screen
->info
.r300_num_z_pipes
,
495 r300
->screen
->info
.gart_size
>> 20,
496 r300
->screen
->info
.vram_size
>> 20,
497 "YES", /* XXX really? */
498 r300
->screen
->caps
.zmask_ram
? "YES" : "NO",
499 r300
->screen
->caps
.hiz_ram
? "YES" : "NO");
502 return &r300
->context
;
505 r300_destroy_context(&r300
->context
);