src/gallium/drivers/r300/r300_context.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  22
  23 #include "draw/draw_context.h"
  24
  25 #include "util/u_memory.h"
  26 #include "util/u_sampler.h"
  27 #include "util/u_simple_list.h"
  28 #include "util/u_upload_mgr.h"
  29 #include "os/os_time.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "r300_cb.h"
  34 #include "r300_context.h"
  35 #include "r300_emit.h"
  36 #include "r300_screen.h"
  37 #include "r300_screen_buffer.h"
  38 #include "compiler/radeon_regalloc.h"
  39
  40 static void r300_release_referenced_objects(struct r300_context *r300)
  41 {
  42     struct pipe_framebuffer_state *fb =
  43             (struct pipe_framebuffer_state*)r300->fb_state.state;
  44     struct r300_textures_state *textures =
  45             (struct r300_textures_state*)r300->textures_state.state;
  46     unsigned i;
  47
  48     /* Framebuffer state. */
  49     util_unreference_framebuffer_state(fb);
  50
  51     /* Textures. */
  52     for (i = 0; i < textures->sampler_view_count; i++)
  53         pipe_sampler_view_reference(
  54                 (struct pipe_sampler_view**)&textures->sampler_views[i], NULL);
  55
  56     /* The special dummy texture for texkill. */
  57     if (r300->texkill_sampler) {
  58         pipe_sampler_view_reference(
  59                 (struct pipe_sampler_view**)&r300->texkill_sampler,
  60                 NULL);
  61     }
  62
  63     /* Manually-created vertex buffers. */
  64     pipe_resource_reference(&r300->dummy_vb.buffer, NULL);
  65     pb_reference(&r300->vbo, NULL);
  66
  67     r300->context.delete_depth_stencil_alpha_state(&r300->context,
  68                                                    r300->dsa_decompress_zmask);
  69 }
  70
  71 static void r300_destroy_context(struct pipe_context* context)
  72 {
  73     struct r300_context* r300 = r300_context(context);
  74
  75     if (r300->cs && r300->hyperz_enabled) {
  76         r300->rws->cs_request_feature(r300->cs, RADEON_FID_R300_HYPERZ_ACCESS, FALSE);
  77     }
  78
  79     if (r300->blitter)
  80         util_blitter_destroy(r300->blitter);
  81     if (r300->draw)
  82         draw_destroy(r300->draw);
  83
  84     if (r300->uploader)
  85         u_upload_destroy(r300->uploader);
  86
  87     /* XXX: This function assumes r300->query_list was initialized */
  88     r300_release_referenced_objects(r300);
  89
  90     if (r300->cs)
  91         r300->rws->cs_destroy(r300->cs);
  92
  93     rc_destroy_regalloc_state(&r300->fs_regalloc_state);
  94
  95     /* XXX: No way to tell if this was initialized or not? */
  96     util_slab_destroy(&r300->pool_transfers);
  97
  98     /* Free the structs allocated in r300_setup_atoms() */
  99     if (r300->aa_state.state) {
 100         FREE(r300->aa_state.state);
 101         FREE(r300->blend_color_state.state);
 102         FREE(r300->clip_state.state);
 103         FREE(r300->fb_state.state);
 104         FREE(r300->gpu_flush.state);
 105         FREE(r300->hyperz_state.state);
 106         FREE(r300->invariant_state.state);
 107         FREE(r300->rs_block_state.state);
 108         FREE(r300->sample_mask.state);
 109         FREE(r300->scissor_state.state);
 110         FREE(r300->textures_state.state);
 111         FREE(r300->vap_invariant_state.state);
 112         FREE(r300->viewport_state.state);
 113         FREE(r300->ztop_state.state);
 114         FREE(r300->fs_constants.state);
 115         FREE(r300->vs_constants.state);
 116         if (!r300->screen->caps.has_tcl) {
 117             FREE(r300->vertex_stream_state.state);
 118         }
 119     }
 120     FREE(r300);
 121 }
 122
 123 static void r300_flush_callback(void *data, unsigned flags)
 124 {
 125     struct r300_context* const cs_context_copy = data;
 126
 127     r300_flush(&cs_context_copy->context, flags, NULL);
 128 }
 129
 130 #define R300_INIT_ATOM(atomname, atomsize) \
 131  do { \
 132     r300->atomname.name = #atomname; \
 133     r300->atomname.state = NULL; \
 134     r300->atomname.size = atomsize; \
 135     r300->atomname.emit = r300_emit_##atomname; \
 136     r300->atomname.dirty = FALSE; \
 137  } while (0)
 138
 139 #define R300_ALLOC_ATOM(atomname, statetype) \
 140 do { \
 141     r300->atomname.state = CALLOC_STRUCT(statetype); \
 142     if (r300->atomname.state == NULL) \
 143         return FALSE; \
 144 } while (0)
 145
 146 static boolean r300_setup_atoms(struct r300_context* r300)
 147 {
 148     boolean is_rv350 = r300->screen->caps.is_rv350;
 149     boolean is_r500 = r300->screen->caps.is_r500;
 150     boolean has_tcl = r300->screen->caps.has_tcl;
 151     boolean drm_2_6_0 = r300->screen->info.drm_minor >= 6;
 152
 153     /* Create the actual atom list.
 154      *
 155      * Some atoms never change size, others change every emit - those have
 156      * the size of 0 here.
 157      *
 158      * NOTE: The framebuffer state is split into these atoms:
 159      * - gpu_flush          (unpipelined regs)
 160      * - aa_state           (unpipelined regs)
 161      * - fb_state           (unpipelined regs)
 162      * - hyperz_state       (unpipelined regs followed by pipelined ones)
 163      * - fb_state_pipelined (pipelined regs)
 164      * The motivation behind this is to be able to emit a strict
 165      * subset of the regs, and to have reasonable register ordering. */
 166     /* SC, GB (unpipelined), RB3D (unpipelined), ZB (unpipelined). */
 167     R300_INIT_ATOM(gpu_flush, 9);
 168     R300_INIT_ATOM(aa_state, 4);
 169     R300_INIT_ATOM(fb_state, 0);
 170     R300_INIT_ATOM(hyperz_state, is_r500 || (is_rv350 && drm_2_6_0) ? 10 : 8);
 171     /* ZB (unpipelined), SC. */
 172     R300_INIT_ATOM(ztop_state, 2);
 173     /* ZB, FG. */
 174     R300_INIT_ATOM(dsa_state, is_r500 ? (drm_2_6_0 ? 10 : 8) : 6);
 175     /* RB3D. */
 176     R300_INIT_ATOM(blend_state, 8);
 177     R300_INIT_ATOM(blend_color_state, is_r500 ? 3 : 2);
 178     /* SC. */
 179     R300_INIT_ATOM(sample_mask, 2);
 180     R300_INIT_ATOM(scissor_state, 3);
 181     /* GB, FG, GA, SU, SC, RB3D. */
 182     R300_INIT_ATOM(invariant_state, 14 + (is_rv350 ? 4 : 0) + (is_r500 ? 4 : 0));
 183     /* VAP. */
 184     R300_INIT_ATOM(viewport_state, 9);
 185     R300_INIT_ATOM(pvs_flush, 2);
 186     R300_INIT_ATOM(vap_invariant_state, is_r500 ? 11 : 9);
 187     R300_INIT_ATOM(vertex_stream_state, 0);
 188     R300_INIT_ATOM(vs_state, 0);
 189     R300_INIT_ATOM(vs_constants, 0);
 190     R300_INIT_ATOM(clip_state, has_tcl ? 3 + (6 * 4) : 0);
 191     /* VAP, RS, GA, GB, SU, SC. */
 192     R300_INIT_ATOM(rs_block_state, 0);
 193     R300_INIT_ATOM(rs_state, 0);
 194     /* SC, US. */
 195     R300_INIT_ATOM(fb_state_pipelined, 8);
 196     /* US. */
 197     R300_INIT_ATOM(fs, 0);
 198     R300_INIT_ATOM(fs_rc_constant_state, 0);
 199     R300_INIT_ATOM(fs_constants, 0);
 200     /* TX. */
 201     R300_INIT_ATOM(texture_cache_inval, 2);
 202     R300_INIT_ATOM(textures_state, 0);
 203     /* Clear commands */
 204     R300_INIT_ATOM(hiz_clear, r300->screen->caps.hiz_ram > 0 ? 6 : 0);
 205     R300_INIT_ATOM(zmask_clear, r300->screen->caps.zmask_ram > 0 ? 6 : 0);
 206     /* ZB (unpipelined), SU. */
 207     R300_INIT_ATOM(query_start, 4);
 208
 209     /* Replace emission functions for r500. */
 210     if (is_r500) {
 211         r300->fs.emit = r500_emit_fs;
 212         r300->fs_rc_constant_state.emit = r500_emit_fs_rc_constant_state;
 213         r300->fs_constants.emit = r500_emit_fs_constants;
 214     }
 215
 216     /* Some non-CSO atoms need explicit space to store the state locally. */
 217     R300_ALLOC_ATOM(aa_state, r300_aa_state);
 218     R300_ALLOC_ATOM(blend_color_state, r300_blend_color_state);
 219     R300_ALLOC_ATOM(clip_state, r300_clip_state);
 220     R300_ALLOC_ATOM(hyperz_state, r300_hyperz_state);
 221     R300_ALLOC_ATOM(invariant_state, r300_invariant_state);
 222     R300_ALLOC_ATOM(textures_state, r300_textures_state);
 223     R300_ALLOC_ATOM(vap_invariant_state, r300_vap_invariant_state);
 224     R300_ALLOC_ATOM(viewport_state, r300_viewport_state);
 225     R300_ALLOC_ATOM(ztop_state, r300_ztop_state);
 226     R300_ALLOC_ATOM(fb_state, pipe_framebuffer_state);
 227     R300_ALLOC_ATOM(gpu_flush, pipe_framebuffer_state);
 228     r300->sample_mask.state = malloc(4);
 229     R300_ALLOC_ATOM(scissor_state, pipe_scissor_state);
 230     R300_ALLOC_ATOM(rs_block_state, r300_rs_block);
 231     R300_ALLOC_ATOM(fs_constants, r300_constant_buffer);
 232     R300_ALLOC_ATOM(vs_constants, r300_constant_buffer);
 233     if (!r300->screen->caps.has_tcl) {
 234         R300_ALLOC_ATOM(vertex_stream_state, r300_vertex_stream_state);
 235     }
 236
 237     /* Some non-CSO atoms don't use the state pointer. */
 238     r300->fb_state_pipelined.allow_null_state = TRUE;
 239     r300->fs_rc_constant_state.allow_null_state = TRUE;
 240     r300->pvs_flush.allow_null_state = TRUE;
 241     r300->query_start.allow_null_state = TRUE;
 242     r300->texture_cache_inval.allow_null_state = TRUE;
 243
 244     /* Some states must be marked as dirty here to properly set up
 245      * hardware in the first command stream. */
 246     r300_mark_atom_dirty(r300, &r300->invariant_state);
 247     r300_mark_atom_dirty(r300, &r300->pvs_flush);
 248     r300_mark_atom_dirty(r300, &r300->vap_invariant_state);
 249     r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
 250     r300_mark_atom_dirty(r300, &r300->textures_state);
 251
 252     return TRUE;
 253 }
 254
 255 /* Not every state tracker calls every driver function before the first draw
 256  * call and we must initialize the command buffers somehow. */
 257 static void r300_init_states(struct pipe_context *pipe)
 258 {
 259     struct r300_context *r300 = r300_context(pipe);
 260     struct pipe_blend_color bc = {{0}};
 261     struct pipe_clip_state cs = {{{0}}};
 262     struct pipe_scissor_state ss = {0};
 263     struct r300_gpu_flush *gpuflush =
 264             (struct r300_gpu_flush*)r300->gpu_flush.state;
 265     struct r300_vap_invariant_state *vap_invariant =
 266             (struct r300_vap_invariant_state*)r300->vap_invariant_state.state;
 267     struct r300_invariant_state *invariant =
 268             (struct r300_invariant_state*)r300->invariant_state.state;
 269
 270     CB_LOCALS;
 271
 272     pipe->set_blend_color(pipe, &bc);
 273     pipe->set_clip_state(pipe, &cs);
 274     pipe->set_scissor_state(pipe, &ss);
 275     pipe->set_sample_mask(pipe, ~0);
 276
 277     /* Initialize the GPU flush. */
 278     {
 279         BEGIN_CB(gpuflush->cb_flush_clean, 6);
 280
 281         /* Flush and free renderbuffer caches. */
 282         OUT_CB_REG(R300_RB3D_DSTCACHE_CTLSTAT,
 283             R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
 284             R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 285         OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
 286             R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 287             R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
 288
 289         /* Wait until the GPU is idle.
 290          * This fixes random pixels sometimes appearing probably caused
 291          * by incomplete rendering. */
 292         OUT_CB_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
 293         END_CB;
 294     }
 295
 296     /* Initialize the VAP invariant state. */
 297     {
 298         BEGIN_CB(vap_invariant->cb, r300->vap_invariant_state.size);
 299         OUT_CB_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
 300         OUT_CB_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
 301         OUT_CB_32F(1.0);
 302         OUT_CB_32F(1.0);
 303         OUT_CB_32F(1.0);
 304         OUT_CB_32F(1.0);
 305         OUT_CB_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
 306
 307         if (r300->screen->caps.is_r500) {
 308             OUT_CB_REG(R500_VAP_TEX_TO_COLOR_CNTL, 0);
 309         }
 310         END_CB;
 311     }
 312
 313     /* Initialize the invariant state. */
 314     {
 315         BEGIN_CB(invariant->cb, r300->invariant_state.size);
 316         OUT_CB_REG(R300_GB_SELECT, 0);
 317         OUT_CB_REG(R300_FG_FOG_BLEND, 0);
 318         OUT_CB_REG(R300_GA_OFFSET, 0);
 319         OUT_CB_REG(R300_SU_TEX_WRAP, 0);
 320         OUT_CB_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
 321         OUT_CB_REG(R300_SU_DEPTH_OFFSET, 0);
 322         OUT_CB_REG(R300_SC_EDGERULE, 0x2DA49525);
 323
 324         if (r300->screen->caps.is_rv350) {
 325             OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x01010101);
 326             OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFEFEFEFE);
 327         }
 328
 329         if (r300->screen->caps.is_r500) {
 330             OUT_CB_REG(R500_GA_COLOR_CONTROL_PS3, 0);
 331             OUT_CB_REG(R500_SU_TEX_WRAP_PS3, 0);
 332         }
 333         END_CB;
 334     }
 335
 336     /* Initialize the hyperz state. */
 337     {
 338         struct r300_hyperz_state *hyperz =
 339             (struct r300_hyperz_state*)r300->hyperz_state.state;
 340         BEGIN_CB(&hyperz->cb_flush_begin, r300->hyperz_state.size);
 341         OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
 342                    R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 343         OUT_CB_REG(R300_ZB_BW_CNTL, 0);
 344         OUT_CB_REG(R300_ZB_DEPTHCLEARVALUE, 0);
 345         OUT_CB_REG(R300_SC_HYPERZ, R300_SC_HYPERZ_ADJ_2);
 346
 347         if (r300->screen->caps.is_r500 ||
 348             (r300->screen->caps.is_rv350 &&
 349              r300->screen->info.drm_minor >= 6)) {
 350             OUT_CB_REG(R300_GB_Z_PEQ_CONFIG, 0);
 351         }
 352         END_CB;
 353     }
 354 }
 355
 356 struct pipe_context* r300_create_context(struct pipe_screen* screen,
 357                                          void *priv)
 358 {
 359     struct r300_context* r300 = CALLOC_STRUCT(r300_context);
 360     struct r300_screen* r300screen = r300_screen(screen);
 361     struct radeon_winsys *rws = r300screen->rws;
 362
 363     if (!r300)
 364         return NULL;
 365
 366     r300->rws = rws;
 367     r300->screen = r300screen;
 368
 369     r300->context.screen = screen;
 370     r300->context.priv = priv;
 371
 372     r300->context.destroy = r300_destroy_context;
 373
 374     util_slab_create(&r300->pool_transfers,
 375                      sizeof(struct pipe_transfer), 64,
 376                      UTIL_SLAB_SINGLETHREADED);
 377
 378     r300->cs = rws->cs_create(rws);
 379     if (r300->cs == NULL)
 380         goto fail;
 381
 382     if (!r300screen->caps.has_tcl) {
 383         /* Create a Draw. This is used for SW TCL. */
 384         r300->draw = draw_create(&r300->context);
 385         if (r300->draw == NULL)
 386             goto fail;
 387         /* Enable our renderer. */
 388         draw_set_rasterize_stage(r300->draw, r300_draw_stage(r300));
 389         /* Disable converting points/lines to triangles. */
 390         draw_wide_line_threshold(r300->draw, 10000000.f);
 391         draw_wide_point_threshold(r300->draw, 10000000.f);
 392         draw_wide_point_sprites(r300->draw, FALSE);
 393         draw_enable_line_stipple(r300->draw, TRUE);
 394         draw_enable_point_sprites(r300->draw, FALSE);
 395     }
 396
 397     if (!r300_setup_atoms(r300))
 398         goto fail;
 399
 400     r300_init_blit_functions(r300);
 401     r300_init_flush_functions(r300);
 402     r300_init_query_functions(r300);
 403     r300_init_state_functions(r300);
 404     r300_init_resource_functions(r300);
 405     r300_init_render_functions(r300);
 406     r300_init_states(&r300->context);
 407
 408     r300->context.create_video_decoder = vl_create_decoder;
 409     r300->context.create_video_buffer = vl_video_buffer_create;
 410
 411     if (r300screen->caps.has_tcl) {
 412         r300->uploader = u_upload_create(&r300->context, 256 * 1024, 4,
 413                                          PIPE_BIND_INDEX_BUFFER);
 414     }
 415
 416     r300->blitter = util_blitter_create(&r300->context);
 417     if (r300->blitter == NULL)
 418         goto fail;
 419     r300->blitter->draw_rectangle = r300_blitter_draw_rectangle;
 420
 421     rws->cs_set_flush_callback(r300->cs, r300_flush_callback, r300);
 422
 423     /* The KIL opcode needs the first texture unit to be enabled
 424      * on r3xx-r4xx. In order to calm down the CS checker, we bind this
 425      * dummy texture there. */
 426     if (!r300->screen->caps.is_r500) {
 427         struct pipe_resource *tex;
 428         struct pipe_resource rtempl = {{0}};
 429         struct pipe_sampler_view vtempl = {{0}};
 430
 431         rtempl.target = PIPE_TEXTURE_2D;
 432         rtempl.format = PIPE_FORMAT_I8_UNORM;
 433         rtempl.usage = PIPE_USAGE_IMMUTABLE;
 434         rtempl.width0 = 1;
 435         rtempl.height0 = 1;
 436         rtempl.depth0 = 1;
 437         tex = screen->resource_create(screen, &rtempl);
 438
 439         u_sampler_view_default_template(&vtempl, tex, tex->format);
 440
 441         r300->texkill_sampler = (struct r300_sampler_view*)
 442             r300->context.create_sampler_view(&r300->context, tex, &vtempl);
 443
 444         pipe_resource_reference(&tex, NULL);
 445     }
 446
 447     if (r300screen->caps.has_tcl) {
 448         struct pipe_resource vb;
 449         memset(&vb, 0, sizeof(vb));
 450         vb.target = PIPE_BUFFER;
 451         vb.format = PIPE_FORMAT_R8_UNORM;
 452         vb.usage = PIPE_USAGE_STATIC;
 453         vb.width0 = sizeof(float) * 16;
 454         vb.height0 = 1;
 455         vb.depth0 = 1;
 456
 457         r300->dummy_vb.buffer = screen->resource_create(screen, &vb);
 458     }
 459
 460     {
 461         struct pipe_depth_stencil_alpha_state dsa;
 462         memset(&dsa, 0, sizeof(dsa));
 463         dsa.depth.writemask = 1;
 464
 465         r300->dsa_decompress_zmask =
 466             r300->context.create_depth_stencil_alpha_state(&r300->context,
 467                                                            &dsa);
 468     }
 469
 470     r300->hyperz_time_of_last_flush = os_time_get();
 471
 472     /* Register allocator state */
 473     rc_init_regalloc_state(&r300->fs_regalloc_state);
 474
 475     /* Print driver info. */
 476 #ifdef DEBUG
 477     {
 478 #else
 479     if (DBG_ON(r300, DBG_INFO)) {
 480 #endif
 481         fprintf(stderr,
 482                 "r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
 483                 "r300: GART size: %d MB, VRAM size: %d MB\n"
 484                 "r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
 485                 r300->screen->info.drm_major,
 486                 r300->screen->info.drm_minor,
 487                 r300->screen->info.drm_patchlevel,
 488                 screen->get_name(screen),
 489                 r300->screen->info.pci_id,
 490                 r300->screen->info.r300_num_gb_pipes,
 491                 r300->screen->info.r300_num_z_pipes,
 492                 r300->screen->info.gart_size >> 20,
 493                 r300->screen->info.vram_size >> 20,
 494                 "YES", /* XXX really? */
 495                 r300->screen->caps.zmask_ram ? "YES" : "NO",
 496                 r300->screen->caps.hiz_ram ? "YES" : "NO");
 497     }
 498
 499     return &r300->context;
 500
 501 fail:
 502     r300_destroy_context(&r300->context);
 503     return NULL;
 504 }