src/gallium/drivers/r300/r300_context.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  22
  23 #include "draw/draw_context.h"
  24
  25 #include "util/u_memory.h"
  26 #include "util/u_sampler.h"
  27 #include "util/u_simple_list.h"
  28 #include "util/u_upload_mgr.h"
  29 #include "os/os_time.h"
  30 #include "vl/vl_video_buffer.h"
  31
  32 #include "r300_cb.h"
  33 #include "r300_context.h"
  34 #include "r300_emit.h"
  35 #include "r300_screen.h"
  36 #include "r300_screen_buffer.h"
  37
  38 static void r300_update_num_contexts(struct r300_screen *r300screen,
  39                                      int diff)
  40 {
  41     pipe_mutex_lock(r300screen->num_contexts_mutex);
  42     if (diff > 0) {
  43         r300screen->num_contexts++;
  44
  45         if (r300screen->num_contexts > 1)
  46             util_slab_set_thread_safety(&r300screen->pool_buffers,
  47                                         UTIL_SLAB_MULTITHREADED);
  48     } else {
  49         r300screen->num_contexts--;
  50
  51         if (r300screen->num_contexts <= 1)
  52             util_slab_set_thread_safety(&r300screen->pool_buffers,
  53                                         UTIL_SLAB_SINGLETHREADED);
  54     }
  55     pipe_mutex_unlock(r300screen->num_contexts_mutex);
  56 }
  57
  58 static void r300_release_referenced_objects(struct r300_context *r300)
  59 {
  60     struct pipe_framebuffer_state *fb =
  61             (struct pipe_framebuffer_state*)r300->fb_state.state;
  62     struct r300_textures_state *textures =
  63             (struct r300_textures_state*)r300->textures_state.state;
  64     struct r300_query *query, *temp;
  65     unsigned i;
  66
  67     /* Framebuffer state. */
  68     util_unreference_framebuffer_state(fb);
  69
  70     /* Textures. */
  71     for (i = 0; i < textures->sampler_view_count; i++)
  72         pipe_sampler_view_reference(
  73                 (struct pipe_sampler_view**)&textures->sampler_views[i], NULL);
  74
  75     /* The special dummy texture for texkill. */
  76     if (r300->texkill_sampler) {
  77         pipe_sampler_view_reference(
  78                 (struct pipe_sampler_view**)&r300->texkill_sampler,
  79                 NULL);
  80     }
  81
  82     /* Manually-created vertex buffers. */
  83     pipe_resource_reference(&r300->dummy_vb, NULL);
  84     pipe_resource_reference(&r300->vbo, NULL);
  85
  86     /* If there are any queries pending or not destroyed, remove them now. */
  87     foreach_s(query, temp, &r300->query_list) {
  88         remove_from_list(query);
  89         FREE(query);
  90     }
  91
  92     r300->context.delete_depth_stencil_alpha_state(&r300->context,
  93                                                    r300->dsa_decompress_zmask);
  94 }
  95
  96 static void r300_destroy_context(struct pipe_context* context)
  97 {
  98     struct r300_context* r300 = r300_context(context);
  99
 100     if (r300->cs && r300->hyperz_enabled) {
 101         r300->rws->cs_request_feature(r300->cs, RADEON_FID_HYPERZ_RAM_ACCESS, FALSE);
 102     }
 103
 104     if (r300->blitter)
 105         util_blitter_destroy(r300->blitter);
 106     if (r300->draw)
 107         draw_destroy(r300->draw);
 108
 109     if (r300->vbuf_mgr)
 110         u_vbuf_mgr_destroy(r300->vbuf_mgr);
 111
 112     /* XXX: This function assumes r300->query_list was initialized */
 113     r300_release_referenced_objects(r300);
 114
 115     if (r300->cs)
 116         r300->rws->cs_destroy(r300->cs);
 117
 118     /* XXX: No way to tell if this was initialized or not? */
 119     util_slab_destroy(&r300->pool_transfers);
 120
 121     r300_update_num_contexts(r300->screen, -1);
 122
 123     /* Free the structs allocated in r300_setup_atoms() */
 124     if (r300->aa_state.state) {
 125         FREE(r300->aa_state.state);
 126         FREE(r300->blend_color_state.state);
 127         FREE(r300->clip_state.state);
 128         FREE(r300->fb_state.state);
 129         FREE(r300->gpu_flush.state);
 130         FREE(r300->hyperz_state.state);
 131         FREE(r300->invariant_state.state);
 132         FREE(r300->rs_block_state.state);
 133         FREE(r300->scissor_state.state);
 134         FREE(r300->textures_state.state);
 135         FREE(r300->vap_invariant_state.state);
 136         FREE(r300->viewport_state.state);
 137         FREE(r300->ztop_state.state);
 138         FREE(r300->fs_constants.state);
 139         FREE(r300->vs_constants.state);
 140         if (!r300->screen->caps.has_tcl) {
 141             FREE(r300->vertex_stream_state.state);
 142         }
 143     }
 144     FREE(r300);
 145 }
 146
 147 static void r300_flush_callback(void *data, unsigned flags)
 148 {
 149     struct r300_context* const cs_context_copy = data;
 150
 151     r300_flush(&cs_context_copy->context, flags, NULL);
 152 }
 153
 154 #define R300_INIT_ATOM(atomname, atomsize) \
 155  do { \
 156     r300->atomname.name = #atomname; \
 157     r300->atomname.state = NULL; \
 158     r300->atomname.size = atomsize; \
 159     r300->atomname.emit = r300_emit_##atomname; \
 160     r300->atomname.dirty = FALSE; \
 161  } while (0)
 162
 163 #define R300_ALLOC_ATOM(atomname, statetype) \
 164 do { \
 165     r300->atomname.state = CALLOC_STRUCT(statetype); \
 166     if (r300->atomname.state == NULL) \
 167         return FALSE; \
 168 } while (0)
 169
 170 static boolean r300_setup_atoms(struct r300_context* r300)
 171 {
 172     boolean is_rv350 = r300->screen->caps.is_rv350;
 173     boolean is_r500 = r300->screen->caps.is_r500;
 174     boolean has_tcl = r300->screen->caps.has_tcl;
 175     boolean drm_2_6_0 = r300->rws->get_value(r300->rws, RADEON_VID_DRM_2_6_0);
 176
 177     /* Create the actual atom list.
 178      *
 179      * Some atoms never change size, others change every emit - those have
 180      * the size of 0 here.
 181      *
 182      * NOTE: The framebuffer state is split into these atoms:
 183      * - gpu_flush          (unpipelined regs)
 184      * - aa_state           (unpipelined regs)
 185      * - fb_state           (unpipelined regs)
 186      * - hyperz_state       (unpipelined regs followed by pipelined ones)
 187      * - fb_state_pipelined (pipelined regs)
 188      * The motivation behind this is to be able to emit a strict
 189      * subset of the regs, and to have reasonable register ordering. */
 190     /* SC, GB (unpipelined), RB3D (unpipelined), ZB (unpipelined). */
 191     R300_INIT_ATOM(gpu_flush, 9);
 192     R300_INIT_ATOM(aa_state, 4);
 193     R300_INIT_ATOM(fb_state, 0);
 194     R300_INIT_ATOM(hyperz_state, is_r500 || (is_rv350 && drm_2_6_0) ? 10 : 8);
 195     /* ZB (unpipelined), SC. */
 196     R300_INIT_ATOM(ztop_state, 2);
 197     /* ZB, FG. */
 198     R300_INIT_ATOM(dsa_state, is_r500 ? (drm_2_6_0 ? 10 : 8) : 6);
 199     /* RB3D. */
 200     R300_INIT_ATOM(blend_state, 8);
 201     R300_INIT_ATOM(blend_color_state, is_r500 ? 3 : 2);
 202     /* SC. */
 203     R300_INIT_ATOM(scissor_state, 3);
 204     /* GB, FG, GA, SU, SC, RB3D. */
 205     R300_INIT_ATOM(invariant_state, 16 + (is_rv350 ? 4 : 0) + (is_r500 ? 4 : 0));
 206     /* VAP. */
 207     R300_INIT_ATOM(viewport_state, 9);
 208     R300_INIT_ATOM(pvs_flush, 2);
 209     R300_INIT_ATOM(vap_invariant_state, is_r500 ? 11 : 9);
 210     R300_INIT_ATOM(vertex_stream_state, 0);
 211     R300_INIT_ATOM(vs_state, 0);
 212     R300_INIT_ATOM(vs_constants, 0);
 213     R300_INIT_ATOM(clip_state, has_tcl ? 5 + (6 * 4) : 2);
 214     /* VAP, RS, GA, GB, SU, SC. */
 215     R300_INIT_ATOM(rs_block_state, 0);
 216     R300_INIT_ATOM(rs_state, 0);
 217     /* SC, US. */
 218     R300_INIT_ATOM(fb_state_pipelined, 8);
 219     /* US. */
 220     R300_INIT_ATOM(fs, 0);
 221     R300_INIT_ATOM(fs_rc_constant_state, 0);
 222     R300_INIT_ATOM(fs_constants, 0);
 223     /* TX. */
 224     R300_INIT_ATOM(texture_cache_inval, 2);
 225     R300_INIT_ATOM(textures_state, 0);
 226     /* HiZ Clear */
 227     R300_INIT_ATOM(hiz_clear, r300->screen->caps.hiz_ram > 0 ? 4 : 0);
 228     /* zmask clear */
 229     R300_INIT_ATOM(zmask_clear, r300->screen->caps.zmask_ram > 0 ? 4 : 0);
 230     /* ZB (unpipelined), SU. */
 231     R300_INIT_ATOM(query_start, 4);
 232
 233     /* Replace emission functions for r500. */
 234     if (is_r500) {
 235         r300->fs.emit = r500_emit_fs;
 236         r300->fs_rc_constant_state.emit = r500_emit_fs_rc_constant_state;
 237         r300->fs_constants.emit = r500_emit_fs_constants;
 238     }
 239
 240     /* Some non-CSO atoms need explicit space to store the state locally. */
 241     R300_ALLOC_ATOM(aa_state, r300_aa_state);
 242     R300_ALLOC_ATOM(blend_color_state, r300_blend_color_state);
 243     R300_ALLOC_ATOM(clip_state, r300_clip_state);
 244     R300_ALLOC_ATOM(hyperz_state, r300_hyperz_state);
 245     R300_ALLOC_ATOM(invariant_state, r300_invariant_state);
 246     R300_ALLOC_ATOM(textures_state, r300_textures_state);
 247     R300_ALLOC_ATOM(vap_invariant_state, r300_vap_invariant_state);
 248     R300_ALLOC_ATOM(viewport_state, r300_viewport_state);
 249     R300_ALLOC_ATOM(ztop_state, r300_ztop_state);
 250     R300_ALLOC_ATOM(fb_state, pipe_framebuffer_state);
 251     R300_ALLOC_ATOM(gpu_flush, pipe_framebuffer_state);
 252     R300_ALLOC_ATOM(scissor_state, pipe_scissor_state);
 253     R300_ALLOC_ATOM(rs_block_state, r300_rs_block);
 254     R300_ALLOC_ATOM(fs_constants, r300_constant_buffer);
 255     R300_ALLOC_ATOM(vs_constants, r300_constant_buffer);
 256     if (!r300->screen->caps.has_tcl) {
 257         R300_ALLOC_ATOM(vertex_stream_state, r300_vertex_stream_state);
 258     }
 259
 260     /* Some non-CSO atoms don't use the state pointer. */
 261     r300->fb_state_pipelined.allow_null_state = TRUE;
 262     r300->fs_rc_constant_state.allow_null_state = TRUE;
 263     r300->pvs_flush.allow_null_state = TRUE;
 264     r300->query_start.allow_null_state = TRUE;
 265     r300->texture_cache_inval.allow_null_state = TRUE;
 266
 267     /* Some states must be marked as dirty here to properly set up
 268      * hardware in the first command stream. */
 269     r300_mark_atom_dirty(r300, &r300->invariant_state);
 270     r300_mark_atom_dirty(r300, &r300->pvs_flush);
 271     r300_mark_atom_dirty(r300, &r300->vap_invariant_state);
 272     r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
 273     r300_mark_atom_dirty(r300, &r300->textures_state);
 274
 275     return TRUE;
 276 }
 277
 278 /* Not every state tracker calls every driver function before the first draw
 279  * call and we must initialize the command buffers somehow. */
 280 static void r300_init_states(struct pipe_context *pipe)
 281 {
 282     struct r300_context *r300 = r300_context(pipe);
 283     struct pipe_blend_color bc = {{0}};
 284     struct pipe_clip_state cs = {{{0}}};
 285     struct pipe_scissor_state ss = {0};
 286     struct r300_clip_state *clip =
 287             (struct r300_clip_state*)r300->clip_state.state;
 288     struct r300_gpu_flush *gpuflush =
 289             (struct r300_gpu_flush*)r300->gpu_flush.state;
 290     struct r300_vap_invariant_state *vap_invariant =
 291             (struct r300_vap_invariant_state*)r300->vap_invariant_state.state;
 292     struct r300_invariant_state *invariant =
 293             (struct r300_invariant_state*)r300->invariant_state.state;
 294
 295     CB_LOCALS;
 296
 297     pipe->set_blend_color(pipe, &bc);
 298     pipe->set_scissor_state(pipe, &ss);
 299
 300     /* Initialize the clip state. */
 301     if (r300->screen->caps.has_tcl) {
 302         pipe->set_clip_state(pipe, &cs);
 303     } else {
 304         BEGIN_CB(clip->cb, 2);
 305         OUT_CB_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
 306         END_CB;
 307     }
 308
 309     /* Initialize the GPU flush. */
 310     {
 311         BEGIN_CB(gpuflush->cb_flush_clean, 6);
 312
 313         /* Flush and free renderbuffer caches. */
 314         OUT_CB_REG(R300_RB3D_DSTCACHE_CTLSTAT,
 315             R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
 316             R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 317         OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
 318             R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 319             R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
 320
 321         /* Wait until the GPU is idle.
 322          * This fixes random pixels sometimes appearing probably caused
 323          * by incomplete rendering. */
 324         OUT_CB_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
 325         END_CB;
 326     }
 327
 328     /* Initialize the VAP invariant state. */
 329     {
 330         BEGIN_CB(vap_invariant->cb, r300->vap_invariant_state.size);
 331         OUT_CB_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
 332         OUT_CB_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
 333         OUT_CB_32F(1.0);
 334         OUT_CB_32F(1.0);
 335         OUT_CB_32F(1.0);
 336         OUT_CB_32F(1.0);
 337         OUT_CB_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
 338
 339         if (r300->screen->caps.is_r500) {
 340             OUT_CB_REG(R500_VAP_TEX_TO_COLOR_CNTL, 0);
 341         }
 342         END_CB;
 343     }
 344
 345     /* Initialize the invariant state. */
 346     {
 347         BEGIN_CB(invariant->cb, r300->invariant_state.size);
 348         OUT_CB_REG(R300_GB_SELECT, 0);
 349         OUT_CB_REG(R300_FG_FOG_BLEND, 0);
 350         OUT_CB_REG(R300_GA_OFFSET, 0);
 351         OUT_CB_REG(R300_SU_TEX_WRAP, 0);
 352         OUT_CB_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
 353         OUT_CB_REG(R300_SU_DEPTH_OFFSET, 0);
 354         OUT_CB_REG(R300_SC_EDGERULE, 0x2DA49525);
 355         OUT_CB_REG(R300_SC_SCREENDOOR, 0xffffff);
 356
 357         if (r300->screen->caps.is_rv350) {
 358             OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x01010101);
 359             OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFEFEFEFE);
 360         }
 361
 362         if (r300->screen->caps.is_r500) {
 363             OUT_CB_REG(R500_GA_COLOR_CONTROL_PS3, 0);
 364             OUT_CB_REG(R500_SU_TEX_WRAP_PS3, 0);
 365         }
 366         END_CB;
 367     }
 368
 369     /* Initialize the hyperz state. */
 370     {
 371         struct r300_hyperz_state *hyperz =
 372             (struct r300_hyperz_state*)r300->hyperz_state.state;
 373         BEGIN_CB(&hyperz->cb_flush_begin, r300->hyperz_state.size);
 374         OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
 375                    R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 376         OUT_CB_REG(R300_ZB_BW_CNTL, 0);
 377         OUT_CB_REG(R300_ZB_DEPTHCLEARVALUE, 0);
 378         OUT_CB_REG(R300_SC_HYPERZ, R300_SC_HYPERZ_ADJ_2);
 379
 380         if (r300->screen->caps.is_r500 ||
 381             (r300->screen->caps.is_rv350 &&
 382              r300->rws->get_value(r300->rws, RADEON_VID_DRM_2_6_0))) {
 383             OUT_CB_REG(R300_GB_Z_PEQ_CONFIG, 0);
 384         }
 385         END_CB;
 386     }
 387 }
 388
 389 struct pipe_context* r300_create_context(struct pipe_screen* screen,
 390                                          void *priv)
 391 {
 392     struct r300_context* r300 = CALLOC_STRUCT(r300_context);
 393     struct r300_screen* r300screen = r300_screen(screen);
 394     struct radeon_winsys *rws = r300screen->rws;
 395
 396     if (!r300)
 397         return NULL;
 398
 399     r300_update_num_contexts(r300screen, 1);
 400
 401     r300->rws = rws;
 402     r300->screen = r300screen;
 403
 404     r300->context.winsys = (struct pipe_winsys*)rws;
 405     r300->context.screen = screen;
 406     r300->context.priv = priv;
 407
 408     r300->context.destroy = r300_destroy_context;
 409
 410     make_empty_list(&r300->query_list);
 411
 412     util_slab_create(&r300->pool_transfers,
 413                      sizeof(struct pipe_transfer), 64,
 414                      UTIL_SLAB_SINGLETHREADED);
 415
 416     r300->cs = rws->cs_create(rws);
 417     if (r300->cs == NULL)
 418         goto fail;
 419
 420     if (!r300screen->caps.has_tcl) {
 421         /* Create a Draw. This is used for SW TCL. */
 422         r300->draw = draw_create(&r300->context);
 423         if (r300->draw == NULL)
 424             goto fail;
 425         /* Enable our renderer. */
 426         draw_set_rasterize_stage(r300->draw, r300_draw_stage(r300));
 427         /* Disable converting points/lines to triangles. */
 428         draw_wide_line_threshold(r300->draw, 10000000.f);
 429         draw_wide_point_threshold(r300->draw, 10000000.f);
 430     }
 431
 432     if (!r300_setup_atoms(r300))
 433         goto fail;
 434
 435     r300_init_blit_functions(r300);
 436     r300_init_flush_functions(r300);
 437     r300_init_query_functions(r300);
 438     r300_init_state_functions(r300);
 439     r300_init_resource_functions(r300);
 440
 441     r300->context.create_video_buffer = vl_video_buffer_create;
 442
 443     r300->vbuf_mgr = u_vbuf_mgr_create(&r300->context, 1024 * 1024, 16,
 444                                        PIPE_BIND_VERTEX_BUFFER |
 445                                        PIPE_BIND_INDEX_BUFFER,
 446                                        U_VERTEX_FETCH_DWORD_ALIGNED);
 447     if (!r300->vbuf_mgr)
 448         goto fail;
 449
 450     r300->blitter = util_blitter_create(&r300->context);
 451     if (r300->blitter == NULL)
 452         goto fail;
 453
 454     /* Render functions must be initialized after blitter. */
 455     r300_init_render_functions(r300);
 456     r300_init_states(&r300->context);
 457
 458     rws->cs_set_flush(r300->cs, r300_flush_callback, r300);
 459
 460     /* The KIL opcode needs the first texture unit to be enabled
 461      * on r3xx-r4xx. In order to calm down the CS checker, we bind this
 462      * dummy texture there. */
 463     if (!r300->screen->caps.is_r500) {
 464         struct pipe_resource *tex;
 465         struct pipe_resource rtempl = {{0}};
 466         struct pipe_sampler_view vtempl = {{0}};
 467
 468         rtempl.target = PIPE_TEXTURE_2D;
 469         rtempl.format = PIPE_FORMAT_I8_UNORM;
 470         rtempl.bind = PIPE_BIND_SAMPLER_VIEW;
 471         rtempl.usage = PIPE_USAGE_IMMUTABLE;
 472         rtempl.width0 = 1;
 473         rtempl.height0 = 1;
 474         rtempl.depth0 = 1;
 475         tex = screen->resource_create(screen, &rtempl);
 476
 477         u_sampler_view_default_template(&vtempl, tex, tex->format);
 478
 479         r300->texkill_sampler = (struct r300_sampler_view*)
 480             r300->context.create_sampler_view(&r300->context, tex, &vtempl);
 481
 482         pipe_resource_reference(&tex, NULL);
 483     }
 484
 485     {
 486         struct pipe_resource vb;
 487         memset(&vb, 0, sizeof(vb));
 488         vb.target = PIPE_BUFFER;
 489         vb.format = PIPE_FORMAT_R8_UNORM;
 490         vb.bind = PIPE_BIND_VERTEX_BUFFER;
 491         vb.usage = PIPE_USAGE_IMMUTABLE;
 492         vb.width0 = sizeof(float) * 16;
 493         vb.height0 = 1;
 494         vb.depth0 = 1;
 495
 496         r300->dummy_vb = screen->resource_create(screen, &vb);
 497     }
 498
 499     {
 500         struct pipe_depth_stencil_alpha_state dsa;
 501         memset(&dsa, 0, sizeof(dsa));
 502         dsa.depth.writemask = 1;
 503
 504         r300->dsa_decompress_zmask =
 505             r300->context.create_depth_stencil_alpha_state(&r300->context,
 506                                                            &dsa);
 507     }
 508
 509     r300->hyperz_time_of_last_flush = os_time_get();
 510
 511     /* Print driver info. */
 512 #ifdef DEBUG
 513     {
 514 #else
 515     if (DBG_ON(r300, DBG_INFO)) {
 516 #endif
 517         fprintf(stderr,
 518                 "r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
 519                 "r300: GART size: %d MB, VRAM size: %d MB\n"
 520                 "r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
 521                 rws->get_value(rws, RADEON_VID_DRM_MAJOR),
 522                 rws->get_value(rws, RADEON_VID_DRM_MINOR),
 523                 rws->get_value(rws, RADEON_VID_DRM_PATCHLEVEL),
 524                 screen->get_name(screen),
 525                 rws->get_value(rws, RADEON_VID_PCI_ID),
 526                 rws->get_value(rws, RADEON_VID_R300_GB_PIPES),
 527                 rws->get_value(rws, RADEON_VID_R300_Z_PIPES),
 528                 rws->get_value(rws, RADEON_VID_GART_SIZE) >> 20,
 529                 rws->get_value(rws, RADEON_VID_VRAM_SIZE) >> 20,
 530                 "YES", /* XXX really? */
 531                 r300->screen->caps.zmask_ram ? "YES" : "NO",
 532                 r300->screen->caps.hiz_ram ? "YES" : "NO");
 533     }
 534
 535     return &r300->context;
 536
 537 fail:
 538     r300_destroy_context(&r300->context);
 539     return NULL;
 540 }