src/gallium/drivers/r300/r300_context.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  22
  23 #include "draw/draw_context.h"
  24
  25 #include "util/u_memory.h"
  26 #include "util/u_sampler.h"
  27 #include "util/u_simple_list.h"
  28 #include "util/u_upload_mgr.h"
  29 #include "os/os_time.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "r300_cb.h"
  34 #include "r300_context.h"
  35 #include "r300_emit.h"
  36 #include "r300_screen.h"
  37 #include "r300_screen_buffer.h"
  38
  39 static void r300_update_num_contexts(struct r300_screen *r300screen,
  40                                      int diff)
  41 {
  42     pipe_mutex_lock(r300screen->num_contexts_mutex);
  43     if (diff > 0) {
  44         r300screen->num_contexts++;
  45
  46         if (r300screen->num_contexts > 1)
  47             util_slab_set_thread_safety(&r300screen->pool_buffers,
  48                                         UTIL_SLAB_MULTITHREADED);
  49     } else {
  50         r300screen->num_contexts--;
  51
  52         if (r300screen->num_contexts <= 1)
  53             util_slab_set_thread_safety(&r300screen->pool_buffers,
  54                                         UTIL_SLAB_SINGLETHREADED);
  55     }
  56     pipe_mutex_unlock(r300screen->num_contexts_mutex);
  57 }
  58
  59 static void r300_release_referenced_objects(struct r300_context *r300)
  60 {
  61     struct pipe_framebuffer_state *fb =
  62             (struct pipe_framebuffer_state*)r300->fb_state.state;
  63     struct r300_textures_state *textures =
  64             (struct r300_textures_state*)r300->textures_state.state;
  65     struct r300_query *query, *temp;
  66     unsigned i;
  67
  68     /* Framebuffer state. */
  69     util_unreference_framebuffer_state(fb);
  70
  71     /* Textures. */
  72     for (i = 0; i < textures->sampler_view_count; i++)
  73         pipe_sampler_view_reference(
  74                 (struct pipe_sampler_view**)&textures->sampler_views[i], NULL);
  75
  76     /* The special dummy texture for texkill. */
  77     if (r300->texkill_sampler) {
  78         pipe_sampler_view_reference(
  79                 (struct pipe_sampler_view**)&r300->texkill_sampler,
  80                 NULL);
  81     }
  82
  83     /* Manually-created vertex buffers. */
  84     pipe_resource_reference(&r300->dummy_vb, NULL);
  85     pipe_resource_reference(&r300->vbo, NULL);
  86
  87     /* If there are any queries pending or not destroyed, remove them now. */
  88     foreach_s(query, temp, &r300->query_list) {
  89         remove_from_list(query);
  90         FREE(query);
  91     }
  92
  93     r300->context.delete_depth_stencil_alpha_state(&r300->context,
  94                                                    r300->dsa_decompress_zmask);
  95 }
  96
  97 static void r300_destroy_context(struct pipe_context* context)
  98 {
  99     struct r300_context* r300 = r300_context(context);
 100
 101     if (r300->cs && r300->hyperz_enabled) {
 102         r300->rws->cs_request_feature(r300->cs, RADEON_FID_R300_HYPERZ_ACCESS, FALSE);
 103     }
 104
 105     if (r300->blitter)
 106         util_blitter_destroy(r300->blitter);
 107     if (r300->draw)
 108         draw_destroy(r300->draw);
 109
 110     if (r300->vbuf_mgr)
 111         u_vbuf_mgr_destroy(r300->vbuf_mgr);
 112
 113     /* XXX: This function assumes r300->query_list was initialized */
 114     r300_release_referenced_objects(r300);
 115
 116     if (r300->cs)
 117         r300->rws->cs_destroy(r300->cs);
 118
 119     /* XXX: No way to tell if this was initialized or not? */
 120     util_slab_destroy(&r300->pool_transfers);
 121
 122     r300_update_num_contexts(r300->screen, -1);
 123
 124     /* Free the structs allocated in r300_setup_atoms() */
 125     if (r300->aa_state.state) {
 126         FREE(r300->aa_state.state);
 127         FREE(r300->blend_color_state.state);
 128         FREE(r300->clip_state.state);
 129         FREE(r300->fb_state.state);
 130         FREE(r300->gpu_flush.state);
 131         FREE(r300->hyperz_state.state);
 132         FREE(r300->invariant_state.state);
 133         FREE(r300->rs_block_state.state);
 134         FREE(r300->scissor_state.state);
 135         FREE(r300->textures_state.state);
 136         FREE(r300->vap_invariant_state.state);
 137         FREE(r300->viewport_state.state);
 138         FREE(r300->ztop_state.state);
 139         FREE(r300->fs_constants.state);
 140         FREE(r300->vs_constants.state);
 141         if (!r300->screen->caps.has_tcl) {
 142             FREE(r300->vertex_stream_state.state);
 143         }
 144     }
 145     FREE(r300);
 146 }
 147
 148 static void r300_flush_callback(void *data, unsigned flags)
 149 {
 150     struct r300_context* const cs_context_copy = data;
 151
 152     r300_flush(&cs_context_copy->context, flags, NULL);
 153 }
 154
 155 #define R300_INIT_ATOM(atomname, atomsize) \
 156  do { \
 157     r300->atomname.name = #atomname; \
 158     r300->atomname.state = NULL; \
 159     r300->atomname.size = atomsize; \
 160     r300->atomname.emit = r300_emit_##atomname; \
 161     r300->atomname.dirty = FALSE; \
 162  } while (0)
 163
 164 #define R300_ALLOC_ATOM(atomname, statetype) \
 165 do { \
 166     r300->atomname.state = CALLOC_STRUCT(statetype); \
 167     if (r300->atomname.state == NULL) \
 168         return FALSE; \
 169 } while (0)
 170
 171 static boolean r300_setup_atoms(struct r300_context* r300)
 172 {
 173     boolean is_rv350 = r300->screen->caps.is_rv350;
 174     boolean is_r500 = r300->screen->caps.is_r500;
 175     boolean has_tcl = r300->screen->caps.has_tcl;
 176     boolean drm_2_6_0 = r300->screen->info.drm_minor >= 6;
 177
 178     /* Create the actual atom list.
 179      *
 180      * Some atoms never change size, others change every emit - those have
 181      * the size of 0 here.
 182      *
 183      * NOTE: The framebuffer state is split into these atoms:
 184      * - gpu_flush          (unpipelined regs)
 185      * - aa_state           (unpipelined regs)
 186      * - fb_state           (unpipelined regs)
 187      * - hyperz_state       (unpipelined regs followed by pipelined ones)
 188      * - fb_state_pipelined (pipelined regs)
 189      * The motivation behind this is to be able to emit a strict
 190      * subset of the regs, and to have reasonable register ordering. */
 191     /* SC, GB (unpipelined), RB3D (unpipelined), ZB (unpipelined). */
 192     R300_INIT_ATOM(gpu_flush, 9);
 193     R300_INIT_ATOM(aa_state, 4);
 194     R300_INIT_ATOM(fb_state, 0);
 195     R300_INIT_ATOM(hyperz_state, is_r500 || (is_rv350 && drm_2_6_0) ? 10 : 8);
 196     /* ZB (unpipelined), SC. */
 197     R300_INIT_ATOM(ztop_state, 2);
 198     /* ZB, FG. */
 199     R300_INIT_ATOM(dsa_state, is_r500 ? (drm_2_6_0 ? 10 : 8) : 6);
 200     /* RB3D. */
 201     R300_INIT_ATOM(blend_state, 8);
 202     R300_INIT_ATOM(blend_color_state, is_r500 ? 3 : 2);
 203     /* SC. */
 204     R300_INIT_ATOM(scissor_state, 3);
 205     /* GB, FG, GA, SU, SC, RB3D. */
 206     R300_INIT_ATOM(invariant_state, 16 + (is_rv350 ? 4 : 0) + (is_r500 ? 4 : 0));
 207     /* VAP. */
 208     R300_INIT_ATOM(viewport_state, 9);
 209     R300_INIT_ATOM(pvs_flush, 2);
 210     R300_INIT_ATOM(vap_invariant_state, is_r500 ? 11 : 9);
 211     R300_INIT_ATOM(vertex_stream_state, 0);
 212     R300_INIT_ATOM(vs_state, 0);
 213     R300_INIT_ATOM(vs_constants, 0);
 214     R300_INIT_ATOM(clip_state, has_tcl ? 5 + (6 * 4) : 2);
 215     /* VAP, RS, GA, GB, SU, SC. */
 216     R300_INIT_ATOM(rs_block_state, 0);
 217     R300_INIT_ATOM(rs_state, 0);
 218     /* SC, US. */
 219     R300_INIT_ATOM(fb_state_pipelined, 8);
 220     /* US. */
 221     R300_INIT_ATOM(fs, 0);
 222     R300_INIT_ATOM(fs_rc_constant_state, 0);
 223     R300_INIT_ATOM(fs_constants, 0);
 224     /* TX. */
 225     R300_INIT_ATOM(texture_cache_inval, 2);
 226     R300_INIT_ATOM(textures_state, 0);
 227     /* HiZ Clear */
 228     R300_INIT_ATOM(hiz_clear, r300->screen->caps.hiz_ram > 0 ? 4 : 0);
 229     /* zmask clear */
 230     R300_INIT_ATOM(zmask_clear, r300->screen->caps.zmask_ram > 0 ? 4 : 0);
 231     /* ZB (unpipelined), SU. */
 232     R300_INIT_ATOM(query_start, 4);
 233
 234     /* Replace emission functions for r500. */
 235     if (is_r500) {
 236         r300->fs.emit = r500_emit_fs;
 237         r300->fs_rc_constant_state.emit = r500_emit_fs_rc_constant_state;
 238         r300->fs_constants.emit = r500_emit_fs_constants;
 239     }
 240
 241     /* Some non-CSO atoms need explicit space to store the state locally. */
 242     R300_ALLOC_ATOM(aa_state, r300_aa_state);
 243     R300_ALLOC_ATOM(blend_color_state, r300_blend_color_state);
 244     R300_ALLOC_ATOM(clip_state, r300_clip_state);
 245     R300_ALLOC_ATOM(hyperz_state, r300_hyperz_state);
 246     R300_ALLOC_ATOM(invariant_state, r300_invariant_state);
 247     R300_ALLOC_ATOM(textures_state, r300_textures_state);
 248     R300_ALLOC_ATOM(vap_invariant_state, r300_vap_invariant_state);
 249     R300_ALLOC_ATOM(viewport_state, r300_viewport_state);
 250     R300_ALLOC_ATOM(ztop_state, r300_ztop_state);
 251     R300_ALLOC_ATOM(fb_state, pipe_framebuffer_state);
 252     R300_ALLOC_ATOM(gpu_flush, pipe_framebuffer_state);
 253     R300_ALLOC_ATOM(scissor_state, pipe_scissor_state);
 254     R300_ALLOC_ATOM(rs_block_state, r300_rs_block);
 255     R300_ALLOC_ATOM(fs_constants, r300_constant_buffer);
 256     R300_ALLOC_ATOM(vs_constants, r300_constant_buffer);
 257     if (!r300->screen->caps.has_tcl) {
 258         R300_ALLOC_ATOM(vertex_stream_state, r300_vertex_stream_state);
 259     }
 260
 261     /* Some non-CSO atoms don't use the state pointer. */
 262     r300->fb_state_pipelined.allow_null_state = TRUE;
 263     r300->fs_rc_constant_state.allow_null_state = TRUE;
 264     r300->pvs_flush.allow_null_state = TRUE;
 265     r300->query_start.allow_null_state = TRUE;
 266     r300->texture_cache_inval.allow_null_state = TRUE;
 267
 268     /* Some states must be marked as dirty here to properly set up
 269      * hardware in the first command stream. */
 270     r300_mark_atom_dirty(r300, &r300->invariant_state);
 271     r300_mark_atom_dirty(r300, &r300->pvs_flush);
 272     r300_mark_atom_dirty(r300, &r300->vap_invariant_state);
 273     r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
 274     r300_mark_atom_dirty(r300, &r300->textures_state);
 275
 276     return TRUE;
 277 }
 278
 279 /* Not every state tracker calls every driver function before the first draw
 280  * call and we must initialize the command buffers somehow. */
 281 static void r300_init_states(struct pipe_context *pipe)
 282 {
 283     struct r300_context *r300 = r300_context(pipe);
 284     struct pipe_blend_color bc = {{0}};
 285     struct pipe_clip_state cs = {{{0}}};
 286     struct pipe_scissor_state ss = {0};
 287     struct r300_clip_state *clip =
 288             (struct r300_clip_state*)r300->clip_state.state;
 289     struct r300_gpu_flush *gpuflush =
 290             (struct r300_gpu_flush*)r300->gpu_flush.state;
 291     struct r300_vap_invariant_state *vap_invariant =
 292             (struct r300_vap_invariant_state*)r300->vap_invariant_state.state;
 293     struct r300_invariant_state *invariant =
 294             (struct r300_invariant_state*)r300->invariant_state.state;
 295
 296     CB_LOCALS;
 297
 298     pipe->set_blend_color(pipe, &bc);
 299     pipe->set_scissor_state(pipe, &ss);
 300
 301     /* Initialize the clip state. */
 302     if (r300->screen->caps.has_tcl) {
 303         pipe->set_clip_state(pipe, &cs);
 304     } else {
 305         BEGIN_CB(clip->cb, 2);
 306         OUT_CB_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
 307         END_CB;
 308     }
 309
 310     /* Initialize the GPU flush. */
 311     {
 312         BEGIN_CB(gpuflush->cb_flush_clean, 6);
 313
 314         /* Flush and free renderbuffer caches. */
 315         OUT_CB_REG(R300_RB3D_DSTCACHE_CTLSTAT,
 316             R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
 317             R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 318         OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
 319             R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 320             R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
 321
 322         /* Wait until the GPU is idle.
 323          * This fixes random pixels sometimes appearing probably caused
 324          * by incomplete rendering. */
 325         OUT_CB_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
 326         END_CB;
 327     }
 328
 329     /* Initialize the VAP invariant state. */
 330     {
 331         BEGIN_CB(vap_invariant->cb, r300->vap_invariant_state.size);
 332         OUT_CB_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
 333         OUT_CB_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
 334         OUT_CB_32F(1.0);
 335         OUT_CB_32F(1.0);
 336         OUT_CB_32F(1.0);
 337         OUT_CB_32F(1.0);
 338         OUT_CB_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
 339
 340         if (r300->screen->caps.is_r500) {
 341             OUT_CB_REG(R500_VAP_TEX_TO_COLOR_CNTL, 0);
 342         }
 343         END_CB;
 344     }
 345
 346     /* Initialize the invariant state. */
 347     {
 348         BEGIN_CB(invariant->cb, r300->invariant_state.size);
 349         OUT_CB_REG(R300_GB_SELECT, 0);
 350         OUT_CB_REG(R300_FG_FOG_BLEND, 0);
 351         OUT_CB_REG(R300_GA_OFFSET, 0);
 352         OUT_CB_REG(R300_SU_TEX_WRAP, 0);
 353         OUT_CB_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
 354         OUT_CB_REG(R300_SU_DEPTH_OFFSET, 0);
 355         OUT_CB_REG(R300_SC_EDGERULE, 0x2DA49525);
 356         OUT_CB_REG(R300_SC_SCREENDOOR, 0xffffff);
 357
 358         if (r300->screen->caps.is_rv350) {
 359             OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x01010101);
 360             OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFEFEFEFE);
 361         }
 362
 363         if (r300->screen->caps.is_r500) {
 364             OUT_CB_REG(R500_GA_COLOR_CONTROL_PS3, 0);
 365             OUT_CB_REG(R500_SU_TEX_WRAP_PS3, 0);
 366         }
 367         END_CB;
 368     }
 369
 370     /* Initialize the hyperz state. */
 371     {
 372         struct r300_hyperz_state *hyperz =
 373             (struct r300_hyperz_state*)r300->hyperz_state.state;
 374         BEGIN_CB(&hyperz->cb_flush_begin, r300->hyperz_state.size);
 375         OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
 376                    R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 377         OUT_CB_REG(R300_ZB_BW_CNTL, 0);
 378         OUT_CB_REG(R300_ZB_DEPTHCLEARVALUE, 0);
 379         OUT_CB_REG(R300_SC_HYPERZ, R300_SC_HYPERZ_ADJ_2);
 380
 381         if (r300->screen->caps.is_r500 ||
 382             (r300->screen->caps.is_rv350 &&
 383              r300->screen->info.drm_minor >= 6)) {
 384             OUT_CB_REG(R300_GB_Z_PEQ_CONFIG, 0);
 385         }
 386         END_CB;
 387     }
 388 }
 389
 390 struct pipe_context* r300_create_context(struct pipe_screen* screen,
 391                                          void *priv)
 392 {
 393     struct r300_context* r300 = CALLOC_STRUCT(r300_context);
 394     struct r300_screen* r300screen = r300_screen(screen);
 395     struct radeon_winsys *rws = r300screen->rws;
 396
 397     if (!r300)
 398         return NULL;
 399
 400     r300_update_num_contexts(r300screen, 1);
 401
 402     r300->rws = rws;
 403     r300->screen = r300screen;
 404
 405     r300->context.winsys = (struct pipe_winsys*)rws;
 406     r300->context.screen = screen;
 407     r300->context.priv = priv;
 408
 409     r300->context.destroy = r300_destroy_context;
 410
 411     make_empty_list(&r300->query_list);
 412
 413     util_slab_create(&r300->pool_transfers,
 414                      sizeof(struct pipe_transfer), 64,
 415                      UTIL_SLAB_SINGLETHREADED);
 416
 417     r300->cs = rws->cs_create(rws);
 418     if (r300->cs == NULL)
 419         goto fail;
 420
 421     if (!r300screen->caps.has_tcl) {
 422         /* Create a Draw. This is used for SW TCL. */
 423         r300->draw = draw_create(&r300->context);
 424         if (r300->draw == NULL)
 425             goto fail;
 426         /* Enable our renderer. */
 427         draw_set_rasterize_stage(r300->draw, r300_draw_stage(r300));
 428         /* Disable converting points/lines to triangles. */
 429         draw_wide_line_threshold(r300->draw, 10000000.f);
 430         draw_wide_point_threshold(r300->draw, 10000000.f);
 431     }
 432
 433     if (!r300_setup_atoms(r300))
 434         goto fail;
 435
 436     r300_init_blit_functions(r300);
 437     r300_init_flush_functions(r300);
 438     r300_init_query_functions(r300);
 439     r300_init_state_functions(r300);
 440     r300_init_resource_functions(r300);
 441
 442     r300->context.create_video_decoder = vl_create_decoder;
 443     r300->context.create_video_buffer = vl_video_buffer_create;
 444
 445     r300->vbuf_mgr = u_vbuf_mgr_create(&r300->context, 1024 * 1024, 16,
 446                                        PIPE_BIND_VERTEX_BUFFER |
 447                                        PIPE_BIND_INDEX_BUFFER,
 448                                        U_VERTEX_FETCH_DWORD_ALIGNED);
 449     if (!r300->vbuf_mgr)
 450         goto fail;
 451
 452     r300->blitter = util_blitter_create(&r300->context);
 453     if (r300->blitter == NULL)
 454         goto fail;
 455
 456     /* Render functions must be initialized after blitter. */
 457     r300_init_render_functions(r300);
 458     r300_init_states(&r300->context);
 459
 460     rws->cs_set_flush_callback(r300->cs, r300_flush_callback, r300);
 461
 462     /* The KIL opcode needs the first texture unit to be enabled
 463      * on r3xx-r4xx. In order to calm down the CS checker, we bind this
 464      * dummy texture there. */
 465     if (!r300->screen->caps.is_r500) {
 466         struct pipe_resource *tex;
 467         struct pipe_resource rtempl = {{0}};
 468         struct pipe_sampler_view vtempl = {{0}};
 469
 470         rtempl.target = PIPE_TEXTURE_2D;
 471         rtempl.format = PIPE_FORMAT_I8_UNORM;
 472         rtempl.bind = PIPE_BIND_SAMPLER_VIEW;
 473         rtempl.usage = PIPE_USAGE_IMMUTABLE;
 474         rtempl.width0 = 1;
 475         rtempl.height0 = 1;
 476         rtempl.depth0 = 1;
 477         tex = screen->resource_create(screen, &rtempl);
 478
 479         u_sampler_view_default_template(&vtempl, tex, tex->format);
 480
 481         r300->texkill_sampler = (struct r300_sampler_view*)
 482             r300->context.create_sampler_view(&r300->context, tex, &vtempl);
 483
 484         pipe_resource_reference(&tex, NULL);
 485     }
 486
 487     {
 488         struct pipe_resource vb;
 489         memset(&vb, 0, sizeof(vb));
 490         vb.target = PIPE_BUFFER;
 491         vb.format = PIPE_FORMAT_R8_UNORM;
 492         vb.bind = PIPE_BIND_VERTEX_BUFFER;
 493         vb.usage = PIPE_USAGE_IMMUTABLE;
 494         vb.width0 = sizeof(float) * 16;
 495         vb.height0 = 1;
 496         vb.depth0 = 1;
 497
 498         r300->dummy_vb = screen->resource_create(screen, &vb);
 499     }
 500
 501     {
 502         struct pipe_depth_stencil_alpha_state dsa;
 503         memset(&dsa, 0, sizeof(dsa));
 504         dsa.depth.writemask = 1;
 505
 506         r300->dsa_decompress_zmask =
 507             r300->context.create_depth_stencil_alpha_state(&r300->context,
 508                                                            &dsa);
 509     }
 510
 511     r300->hyperz_time_of_last_flush = os_time_get();
 512
 513     /* Print driver info. */
 514 #ifdef DEBUG
 515     {
 516 #else
 517     if (DBG_ON(r300, DBG_INFO)) {
 518 #endif
 519         fprintf(stderr,
 520                 "r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
 521                 "r300: GART size: %d MB, VRAM size: %d MB\n"
 522                 "r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
 523                 r300->screen->info.drm_major,
 524                 r300->screen->info.drm_minor,
 525                 r300->screen->info.drm_patchlevel,
 526                 screen->get_name(screen),
 527                 r300->screen->info.pci_id,
 528                 r300->screen->info.r300_num_gb_pipes,
 529                 r300->screen->info.r300_num_z_pipes,
 530                 r300->screen->info.gart_size >> 20,
 531                 r300->screen->info.vram_size >> 20,
 532                 "YES", /* XXX really? */
 533                 r300->screen->caps.zmask_ram ? "YES" : "NO",
 534                 r300->screen->caps.hiz_ram ? "YES" : "NO");
 535     }
 536
 537     return &r300->context;
 538
 539 fail:
 540     r300_destroy_context(&r300->context);
 541     return NULL;
 542 }