src/gallium/drivers/r300/r300_context.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  22
  23 #ifndef R300_CONTEXT_H
  24 #define R300_CONTEXT_H
  25
  26 #include "draw/draw_vertex.h"
  27
  28 #include "util/u_blitter.h"
  29
  30 #include "pipe/p_context.h"
  31 #include "util/u_inlines.h"
  32 #include "util/u_transfer.h"
  33 #include "util/u_vbuf_mgr.h"
  34
  35 #include "r300_defines.h"
  36 #include "r300_screen.h"
  37 #include "../../winsys/radeon/drm/radeon_winsys.h"
  38
  39 struct u_upload_mgr;
  40 struct r300_context;
  41 struct r300_fragment_shader;
  42 struct r300_vertex_shader;
  43 struct r300_stencilref_context;
  44
  45 struct r300_atom {
  46     /* Name, for debugging. */
  47     const char* name;
  48     /* Opaque state. */
  49     void* state;
  50     /* Emit the state to the context. */
  51     void (*emit)(struct r300_context*, unsigned, void*);
  52     /* Upper bound on number of dwords to emit. */
  53     unsigned size;
  54     /* Whether this atom should be emitted. */
  55     boolean dirty;
  56     /* Whether this atom may be emitted with state == NULL. */
  57     boolean allow_null_state;
  58 };
  59
  60 struct r300_aa_state {
  61     struct r300_surface *dest;
  62
  63     uint32_t aa_config;
  64     uint32_t aaresolve_ctl;
  65 };
  66
  67 struct r300_blend_state {
  68     struct pipe_blend_state state;
  69
  70     uint32_t cb_clamp[8];
  71     uint32_t cb_noclamp[8];
  72     uint32_t cb_no_readwrite[8];
  73 };
  74
  75 struct r300_blend_color_state {
  76     struct pipe_blend_color state;
  77     uint32_t cb[3];
  78 };
  79
  80 struct r300_clip_state {
  81     struct pipe_clip_state clip;
  82
  83     uint32_t cb[29];
  84 };
  85
  86 struct r300_dsa_state {
  87     struct pipe_depth_stencil_alpha_state dsa;
  88
  89     /* This is actually a command buffer with named dwords. */
  90     uint32_t cb_begin;
  91     uint32_t alpha_function;    /* R300_FG_ALPHA_FUNC: 0x4bd4 */
  92     uint32_t cb_reg_seq;
  93     uint32_t z_buffer_control;  /* R300_ZB_CNTL: 0x4f00 */
  94     uint32_t z_stencil_control; /* R300_ZB_ZSTENCILCNTL: 0x4f04 */
  95     uint32_t stencil_ref_mask;  /* R300_ZB_STENCILREFMASK: 0x4f08 */
  96     uint32_t cb_reg;
  97     uint32_t stencil_ref_bf;    /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */
  98     uint32_t cb_reg1;
  99     uint32_t alpha_value;       /* R500_FG_ALPHA_VALUE: 0x4be0 */
 100
 101     /* The same, but for FP16 alpha test. */
 102     uint32_t cb_begin_fp16;
 103     uint32_t alpha_function_fp16;    /* R300_FG_ALPHA_FUNC: 0x4bd4 */
 104     uint32_t cb_reg_seq_fp16;
 105     uint32_t z_buffer_control_fp16;  /* R300_ZB_CNTL: 0x4f00 */
 106     uint32_t z_stencil_control_fp16; /* R300_ZB_ZSTENCILCNTL: 0x4f04 */
 107     uint32_t stencil_ref_mask_fp16;  /* R300_ZB_STENCILREFMASK: 0x4f08 */
 108     uint32_t cb_reg_fp16;
 109     uint32_t stencil_ref_bf_fp16;    /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */
 110     uint32_t cb_reg1_fp16;
 111     uint32_t alpha_value_fp16;       /* R500_FG_ALPHA_VALUE: 0x4be0 */
 112
 113     /* The second command buffer disables zbuffer reads and writes. */
 114     uint32_t cb_zb_no_readwrite[10];
 115     uint32_t cb_fp16_zb_no_readwrite[10];
 116
 117     /* Whether a two-sided stencil is enabled. */
 118     boolean two_sided;
 119     /* Whether a fallback should be used for a two-sided stencil ref value. */
 120     boolean two_sided_stencil_ref;
 121 };
 122
 123 struct r300_hyperz_state {
 124     int flush;
 125     /* This is actually a command buffer with named dwords. */
 126     uint32_t cb_flush_begin;
 127     uint32_t zb_zcache_ctlstat;     /* R300_ZB_CACHE_CNTL */
 128     uint32_t cb_begin;
 129     uint32_t zb_bw_cntl;            /* R300_ZB_BW_CNTL */
 130     uint32_t cb_reg1;
 131     uint32_t zb_depthclearvalue;    /* R300_ZB_DEPTHCLEARVALUE */
 132     uint32_t cb_reg2;
 133     uint32_t sc_hyperz;             /* R300_SC_HYPERZ */
 134     uint32_t cb_reg3;
 135     uint32_t gb_z_peq_config;       /* R300_GB_Z_PEQ_CONFIG: 0x4028 */
 136 };
 137
 138 struct r300_gpu_flush {
 139     uint32_t cb_flush_clean[6];
 140 };
 141
 142 #define RS_STATE_MAIN_SIZE 25
 143
 144 struct r300_rs_state {
 145     /* Original rasterizer state. */
 146     struct pipe_rasterizer_state rs;
 147     /* Draw-specific rasterizer state. */
 148     struct pipe_rasterizer_state rs_draw;
 149
 150     /* Command buffers. */
 151     uint32_t cb_main[RS_STATE_MAIN_SIZE];
 152     uint32_t cb_poly_offset_zb16[5];
 153     uint32_t cb_poly_offset_zb24[5];
 154
 155     /* The index to cb_main where the cull_mode register value resides. */
 156     unsigned cull_mode_index;
 157
 158     /* Whether polygon offset is enabled. */
 159     boolean polygon_offset_enable;
 160
 161     /* This is emitted in the draw function. */
 162     uint32_t color_control;         /* R300_GA_COLOR_CONTROL: 0x4278 */
 163 };
 164
 165 struct r300_rs_block {
 166     uint32_t vap_vtx_state_cntl;  /* R300_VAP_VTX_STATE_CNTL: 0x2180 */
 167     uint32_t vap_vsm_vtx_assm;    /* R300_VAP_VSM_VTX_ASSM: 0x2184 */
 168     uint32_t vap_out_vtx_fmt[2];  /* R300_VAP_OUTPUT_VTX_FMT_[0-1]: 0x2090 */
 169     uint32_t gb_enable;
 170
 171     uint32_t ip[8]; /* R300_RS_IP_[0-7], R500_RS_IP_[0-7] */
 172     uint32_t count; /* R300_RS_COUNT */
 173     uint32_t inst_count; /* R300_RS_INST_COUNT */
 174     uint32_t inst[8]; /* R300_RS_INST_[0-7] */
 175 };
 176
 177 struct r300_sampler_state {
 178     struct pipe_sampler_state state;
 179
 180     uint32_t filter0;      /* R300_TX_FILTER0: 0x4400 */
 181     uint32_t filter1;      /* R300_TX_FILTER1: 0x4440 */
 182
 183     /* Min/max LOD must be clamped to [0, last_level], thus
 184      * it's dependent on a currently bound texture */
 185     unsigned min_lod, max_lod;
 186 };
 187
 188 struct r300_texture_format_state {
 189     uint32_t format0; /* R300_TX_FORMAT0: 0x4480 */
 190     uint32_t format1; /* R300_TX_FORMAT1: 0x44c0 */
 191     uint32_t format2; /* R300_TX_FORMAT2: 0x4500 */
 192     uint32_t tile_config; /* R300_TX_OFFSET (subset thereof) */
 193     uint32_t us_format0;   /* R500_US_FORMAT0_0: 0x4640 (through 15) */
 194 };
 195
 196 struct r300_sampler_view {
 197     struct pipe_sampler_view base;
 198
 199     /* Swizzles in the UTIL_FORMAT_SWIZZLE_* representation,
 200      * derived from base. */
 201     unsigned char swizzle[4];
 202
 203     /* Copy of r300_texture::texture_format_state with format-specific bits
 204      * added. */
 205     struct r300_texture_format_state format;
 206
 207     /* The texture cache region for this texture. */
 208     uint32_t texcache_region;
 209 };
 210
 211 struct r300_texture_sampler_state {
 212     struct r300_texture_format_state format;
 213     uint32_t filter0;      /* R300_TX_FILTER0: 0x4400 */
 214     uint32_t filter1;      /* R300_TX_FILTER1: 0x4440 */
 215     uint32_t border_color; /* R300_TX_BORDER_COLOR: 0x45c0 */
 216 };
 217
 218 struct r300_textures_state {
 219     /* Textures. */
 220     struct r300_sampler_view *sampler_views[16];
 221     int sampler_view_count;
 222     /* Sampler states. */
 223     struct r300_sampler_state *sampler_states[16];
 224     int sampler_state_count;
 225
 226     /* This is the merge of the texture and sampler states. */
 227     unsigned count;
 228     uint32_t tx_enable;         /* R300_TX_ENABLE: 0x4101 */
 229     struct r300_texture_sampler_state regs[16];
 230 };
 231
 232 struct r300_vertex_stream_state {
 233     /* R300_VAP_PROG_STREAK_CNTL_[0-7] */
 234     uint32_t vap_prog_stream_cntl[8];
 235     /* R300_VAP_PROG_STREAK_CNTL_EXT_[0-7] */
 236     uint32_t vap_prog_stream_cntl_ext[8];
 237
 238     unsigned count;
 239 };
 240
 241 struct r300_invariant_state {
 242     uint32_t cb[24];
 243 };
 244
 245 struct r300_vap_invariant_state {
 246     uint32_t cb[11];
 247 };
 248
 249 struct r300_viewport_state {
 250     float xscale;         /* R300_VAP_VPORT_XSCALE:  0x2098 */
 251     float xoffset;        /* R300_VAP_VPORT_XOFFSET: 0x209c */
 252     float yscale;         /* R300_VAP_VPORT_YSCALE:  0x20a0 */
 253     float yoffset;        /* R300_VAP_VPORT_YOFFSET: 0x20a4 */
 254     float zscale;         /* R300_VAP_VPORT_ZSCALE:  0x20a8 */
 255     float zoffset;        /* R300_VAP_VPORT_ZOFFSET: 0x20ac */
 256     uint32_t vte_control; /* R300_VAP_VTE_CNTL:      0x20b0 */
 257 };
 258
 259 struct r300_ztop_state {
 260     uint32_t z_buffer_top;      /* R300_ZB_ZTOP: 0x4f14 */
 261 };
 262
 263 /* The next several objects are not pure Radeon state; they inherit from
 264  * various Gallium classes. */
 265
 266 struct r300_constant_buffer {
 267     /* Buffer of constants */
 268     uint32_t *ptr;
 269     /* Remapping table. */
 270     unsigned *remap_table;
 271     /* const buffer base */
 272     uint32_t buffer_base;
 273 };
 274
 275 /* Query object.
 276  *
 277  * This is not a subclass of pipe_query because pipe_query is never
 278  * actually fully defined. So, rather than have it as a member, and do
 279  * subclass-style casting, we treat pipe_query as an opaque, and just
 280  * trust that our state tracker does not ever mess up query objects.
 281  */
 282 struct r300_query {
 283     /* The kind of query. Currently only OQ is supported. */
 284     unsigned type;
 285     /* The number of pipes where query results are stored. */
 286     unsigned num_pipes;
 287     /* How many results have been written, in dwords. It's incremented
 288      * after end_query and flush. */
 289     unsigned num_results;
 290     /* if begin has been emitted */
 291     boolean begin_emitted;
 292
 293     /* The buffer where query results are stored. */
 294     struct pb_buffer *buf;
 295     struct radeon_winsys_cs_handle *cs_buf;
 296     /* The size of the buffer. */
 297     unsigned buffer_size;
 298     /* The domain of the buffer. */
 299     enum radeon_bo_domain domain;
 300
 301     /* Linked list members. */
 302     struct r300_query* prev;
 303     struct r300_query* next;
 304 };
 305
 306 struct r300_surface {
 307     struct pipe_surface base;
 308
 309     /* Winsys buffer backing the texture. */
 310     struct pb_buffer *buf;
 311     struct radeon_winsys_cs_handle *cs_buf;
 312
 313     enum radeon_bo_domain domain;
 314
 315     uint32_t offset;    /* COLOROFFSET or DEPTHOFFSET. */
 316     uint32_t pitch;     /* COLORPITCH or DEPTHPITCH. */
 317     uint32_t pitch_zmask; /* ZMASK_PITCH */
 318     uint32_t pitch_hiz;   /* HIZ_PITCH */
 319     uint32_t format;    /* US_OUT_FMT or ZB_FORMAT. */
 320
 321     /* Parameters dedicated to the CBZB clear. */
 322     uint32_t cbzb_width;            /* Aligned width. */
 323     uint32_t cbzb_height;           /* Half of the height. */
 324     uint32_t cbzb_midpoint_offset;  /* DEPTHOFFSET. */
 325     uint32_t cbzb_pitch;            /* DEPTHPITCH. */
 326     uint32_t cbzb_format;           /* ZB_FORMAT. */
 327
 328     /* Whether the CBZB clear is allowed on the surface. */
 329     boolean cbzb_allowed;
 330 };
 331
 332 struct r300_texture_desc {
 333     /* Width, height, and depth.
 334      * Most of the time, these are equal to pipe_texture::width0, height0,
 335      * and depth0. However, NPOT 3D textures must have dimensions aligned
 336      * to POT, and this is the only case when these variables differ from
 337      * pipe_texture. */
 338     unsigned width0, height0, depth0;
 339
 340     /* Buffer tiling.
 341      * Macrotiling is specified per-level because small mipmaps cannot
 342      * be macrotiled. */
 343     enum radeon_bo_layout microtile;
 344     enum radeon_bo_layout macrotile[R300_MAX_TEXTURE_LEVELS];
 345
 346     /* Offsets into the buffer. */
 347     unsigned offset_in_bytes[R300_MAX_TEXTURE_LEVELS];
 348
 349     /* Strides for each mip-level. */
 350     unsigned stride_in_pixels[R300_MAX_TEXTURE_LEVELS];
 351     unsigned stride_in_bytes[R300_MAX_TEXTURE_LEVELS];
 352
 353     /* Size of one zslice or face or 2D image based on the texture target. */
 354     unsigned layer_size_in_bytes[R300_MAX_TEXTURE_LEVELS];
 355
 356     /* Total size of this texture, in bytes,
 357      * derived from the texture properties. */
 358     unsigned size_in_bytes;
 359
 360     /* Total size of the buffer backing this texture, in bytes.
 361      * It must be >= size. */
 362     unsigned buffer_size_in_bytes;
 363
 364     /**
 365      * If non-zero, override the natural texture layout with
 366      * a custom stride (in bytes).
 367      *
 368      * \note Mipmapping fails for textures with a non-natural layout!
 369      *
 370      * \sa r300_texture_get_stride
 371      */
 372     unsigned stride_in_bytes_override;
 373
 374     /* Whether this texture has non-power-of-two dimensions.
 375      * It can be either a regular texture or a rectangle one. */
 376     boolean is_npot;
 377
 378     /* This flag says that hardware must use the stride for addressing
 379      * instead of the width. */
 380     boolean uses_stride_addressing;
 381
 382     /* Whether CBZB fast color clear is allowed on the miplevel. */
 383     boolean cbzb_allowed[R300_MAX_TEXTURE_LEVELS];
 384
 385     /* Zbuffer compression info for each miplevel. */
 386     boolean zcomp8x8[R300_MAX_TEXTURE_LEVELS];
 387     /* If zero, then disable Z compression/HiZ. */
 388     unsigned zmask_dwords[R300_MAX_TEXTURE_LEVELS];
 389     unsigned hiz_dwords[R300_MAX_TEXTURE_LEVELS];
 390     /* Zmask/HiZ strides for each miplevel. */
 391     unsigned zmask_stride_in_pixels[R300_MAX_TEXTURE_LEVELS];
 392     unsigned hiz_stride_in_pixels[R300_MAX_TEXTURE_LEVELS];
 393 };
 394
 395 struct r300_resource
 396 {
 397     struct u_vbuf_resource b;
 398
 399     /* Winsys buffer backing this resource. */
 400     struct pb_buffer *buf;
 401     struct radeon_winsys_cs_handle *cs_buf;
 402     enum radeon_bo_domain domain;
 403     unsigned buf_size;
 404
 405     /* Constant buffers are in user memory. */
 406     uint8_t *constant_buffer;
 407
 408     /* Texture description (addressing, layout, special features). */
 409     struct r300_texture_desc tex;
 410
 411     /* Registers carrying texture format data. */
 412     /* Only format-independent bits should be filled in. */
 413     struct r300_texture_format_state tx_format;
 414
 415     /* Where the texture starts in the buffer. */
 416     unsigned tex_offset;
 417
 418     /* This is the level tiling flags were last time set for.
 419      * It's used to prevent redundant tiling-flags changes from happening.*/
 420     unsigned surface_level;
 421 };
 422
 423 struct r300_vertex_element_state {
 424     unsigned count;
 425     struct pipe_vertex_element velem[PIPE_MAX_ATTRIBS];
 426     unsigned format_size[PIPE_MAX_ATTRIBS];
 427
 428     struct u_vbuf_mgr_elements *vmgr_elements;
 429
 430     /* The size of the vertex, in dwords. */
 431     unsigned vertex_size_dwords;
 432
 433     struct r300_vertex_stream_state vertex_stream;
 434     struct r300_vertex_stream_state vertex_stream_instanced;
 435 };
 436
 437 enum r300_hiz_func {
 438     HIZ_FUNC_NONE,
 439
 440     /* The function, when determined, is set in stone
 441      * until the next HiZ clear. */
 442
 443     /* MAX is written to the HiZ buffer.
 444      * Used for LESS, LEQUAL. */
 445     HIZ_FUNC_MAX,
 446
 447     /* MIN is written to the HiZ buffer.
 448      * Used for GREATER, GEQUAL. */
 449     HIZ_FUNC_MIN,
 450 };
 451
 452 /* For deferred fragment shader state validation. */
 453 enum r300_fs_validity_status {
 454     FRAGMENT_SHADER_VALID,      /* No need to change/validate the FS. */
 455     FRAGMENT_SHADER_MAYBE_DIRTY,/* Validate the FS if external state was changed. */
 456     FRAGMENT_SHADER_DIRTY       /* Always validate the FS (if the FS was changed) */
 457 };
 458
 459 struct r300_context {
 460     /* Parent class */
 461     struct pipe_context context;
 462
 463     /* The interface to the windowing system, etc. */
 464     struct radeon_winsys *rws;
 465     /* The command stream. */
 466     struct radeon_winsys_cs *cs;
 467     /* Screen. */
 468     struct r300_screen *screen;
 469
 470     /* Draw module. Used mostly for SW TCL. */
 471     struct draw_context* draw;
 472     /* Vertex buffer for SW TCL. */
 473     struct pipe_resource* vbo;
 474     /* Offset and size into the SW TCL VBO. */
 475     size_t draw_vbo_offset;
 476     size_t draw_vbo_size;
 477     /* Whether the VBO must not be flushed. */
 478     boolean draw_vbo_locked;
 479     boolean draw_first_emitted;
 480
 481     /* Accelerated blit support. */
 482     struct blitter_context* blitter;
 483     /* Stencil two-sided reference value fallback. */
 484     struct r300_stencilref_context *stencilref_fallback;
 485
 486     /* The KIL opcode needs the first texture unit to be enabled
 487      * on r3xx-r4xx. In order to calm down the CS checker, we bind this
 488      * dummy texture there. */
 489     struct r300_sampler_view *texkill_sampler;
 490
 491     /* When no vertex buffer is set, this one is used instead to prevent
 492      * hardlocks. */
 493     struct pipe_resource *dummy_vb;
 494     /* Vertex buffer for InstanceID. */
 495     struct r300_resource *vb_instanceid;
 496
 497     /* The currently active query. */
 498     struct r300_query *query_current;
 499     /* The saved query for blitter operations. */
 500     struct r300_query *blitter_saved_query;
 501     /* Query list. */
 502     struct r300_query query_list;
 503
 504     /* Various CSO state objects. */
 505
 506     /* Each atom is emitted in the order it appears here, which can affect
 507      * performance and stability if not handled with care. */
 508     /* GPU flush. */
 509     struct r300_atom gpu_flush;
 510     /* Anti-aliasing (MSAA) state. */
 511     struct r300_atom aa_state;
 512     /* Framebuffer state. */
 513     struct r300_atom fb_state;
 514     /* HyperZ state (various SC/ZB bits). */
 515     struct r300_atom hyperz_state;
 516     /* ZTOP state. */
 517     struct r300_atom ztop_state;
 518     /* Depth, stencil, and alpha state. */
 519     struct r300_atom dsa_state;
 520     /* Blend state. */
 521     struct r300_atom blend_state;
 522     /* Blend color state. */
 523     struct r300_atom blend_color_state;
 524     /* Scissor state. */
 525     struct r300_atom scissor_state;
 526     /* Invariant state. This must be emitted to get the engine started. */
 527     struct r300_atom invariant_state;
 528     /* Viewport state. */
 529     struct r300_atom viewport_state;
 530     /* PVS flush. */
 531     struct r300_atom pvs_flush;
 532     /* VAP invariant state. */
 533     struct r300_atom vap_invariant_state;
 534     /* Vertex stream formatting state. */
 535     struct r300_atom vertex_stream_state;
 536     /* Vertex shader. */
 537     struct r300_atom vs_state;
 538     /* User clip planes. */
 539     struct r300_atom clip_state;
 540     /* RS block state + VAP (vertex shader) output mapping state. */
 541     struct r300_atom rs_block_state;
 542     /* Rasterizer state. */
 543     struct r300_atom rs_state;
 544     /* Framebuffer state (pipelined regs). */
 545     struct r300_atom fb_state_pipelined;
 546     /* Fragment shader. */
 547     struct r300_atom fs;
 548     /* Fragment shader RC_CONSTANT_STATE variables. */
 549     struct r300_atom fs_rc_constant_state;
 550     /* Fragment shader constant buffer. */
 551     struct r300_atom fs_constants;
 552     /* Vertex shader constant buffer. */
 553     struct r300_atom vs_constants;
 554     /* Texture cache invalidate. */
 555     struct r300_atom texture_cache_inval;
 556     /* Textures state. */
 557     struct r300_atom textures_state;
 558     /* HiZ clear */
 559     struct r300_atom hiz_clear;
 560     /* zmask clear */
 561     struct r300_atom zmask_clear;
 562     /* Occlusion query. */
 563     struct r300_atom query_start;
 564
 565     /* The pointers to the first and the last atom. */
 566     struct r300_atom *first_dirty, *last_dirty;
 567
 568     /* Vertex elements for Gallium. */
 569     struct r300_vertex_element_state *velems;
 570
 571     struct pipe_index_buffer index_buffer;
 572
 573     /* Vertex info for Draw. */
 574     struct vertex_info vertex_info;
 575
 576     struct pipe_stencil_ref stencil_ref;
 577     struct pipe_viewport_state viewport;
 578
 579     /* Stream locations for SWTCL. */
 580     int stream_loc_notcl[16];
 581
 582     /* Flag indicating whether or not the HW is dirty. */
 583     uint32_t dirty_hw;
 584     /* Whether polygon offset is enabled. */
 585     boolean polygon_offset_enabled;
 586     /* Z buffer bit depth. */
 587     uint32_t zbuffer_bpp;
 588     /* Whether rendering is conditional and should be skipped. */
 589     boolean skip_rendering;
 590     /* Point sprites texcoord index,  1 bit per texcoord */
 591     int sprite_coord_enable;
 592     /* Whether two-sided color selection is enabled (AKA light_twoside). */
 593     boolean two_sided_color;
 594     /* Whether fragment color clamping is enabled. */
 595     boolean frag_clamp;
 596     /* Whether fast color clear is enabled. */
 597     boolean cbzb_clear;
 598     /* Whether fragment shader needs to be validated. */
 599     enum r300_fs_validity_status fs_status;
 600     /* Framebuffer multi-write. */
 601     boolean fb_multiwrite;
 602
 603     void *dsa_decompress_zmask;
 604
 605     struct u_vbuf_mgr *vbuf_mgr;
 606
 607     struct util_slab_mempool pool_transfers;
 608
 609     /* Stat counter. */
 610     uint64_t flush_counter;
 611
 612     /* const tracking for VS */
 613     int vs_const_base;
 614
 615     /* Vertex array state info */
 616     boolean vertex_arrays_dirty;
 617     boolean vertex_arrays_indexed;
 618     int vertex_arrays_offset;
 619     int vertex_arrays_instance_id;
 620     boolean instancing_enabled;
 621
 622     /* Hyper-Z stats. */
 623     boolean hyperz_enabled;     /* Whether it owns Hyper-Z access. */
 624     int64_t hyperz_time_of_last_flush; /* Time of the last flush with Z clear. */
 625     unsigned num_z_clears;      /* Since the last flush. */
 626
 627     /* ZMask state. */
 628     boolean zmask_in_use;       /* Whether ZMASK is enabled. */
 629     boolean zmask_decompress;   /* Whether ZMASK is being decompressed. */
 630     struct pipe_surface *locked_zbuffer; /* Unbound zbuffer which still has data in ZMASK. */
 631
 632     /* HiZ state. */
 633     boolean hiz_in_use;         /* Whether HIZ is enabled. */
 634     enum r300_hiz_func hiz_func; /* HiZ function. Can be either MIN or MAX. */
 635     uint32_t hiz_clear_value;   /* HiZ clear value. */
 636 };
 637
 638 #define foreach_atom(r300, atom) \
 639     for (atom = &r300->gpu_flush; atom != (&r300->query_start)+1; atom++)
 640
 641 #define foreach_dirty_atom(r300, atom) \
 642     for (atom = r300->first_dirty; atom != r300->last_dirty; atom++)
 643
 644 /* Convenience cast wrappers. */
 645 static INLINE struct r300_query* r300_query(struct pipe_query* q)
 646 {
 647     return (struct r300_query*)q;
 648 }
 649
 650 static INLINE struct r300_surface* r300_surface(struct pipe_surface* surf)
 651 {
 652     return (struct r300_surface*)surf;
 653 }
 654
 655 static INLINE struct r300_resource* r300_resource(struct pipe_resource* tex)
 656 {
 657     return (struct r300_resource*)tex;
 658 }
 659
 660 static INLINE struct r300_context* r300_context(struct pipe_context* context)
 661 {
 662     return (struct r300_context*)context;
 663 }
 664
 665 static INLINE struct r300_fragment_shader *r300_fs(struct r300_context *r300)
 666 {
 667     return (struct r300_fragment_shader*)r300->fs.state;
 668 }
 669
 670 static INLINE void r300_mark_atom_dirty(struct r300_context *r300,
 671                                         struct r300_atom *atom)
 672 {
 673     atom->dirty = TRUE;
 674
 675     if (!r300->first_dirty) {
 676         r300->first_dirty = atom;
 677         r300->last_dirty = atom+1;
 678     } else {
 679         if (atom < r300->first_dirty)
 680             r300->first_dirty = atom;
 681         else if (atom+1 > r300->last_dirty)
 682             r300->last_dirty = atom+1;
 683     }
 684 }
 685
 686 struct pipe_context* r300_create_context(struct pipe_screen* screen,
 687                                          void *priv);
 688
 689 /* Context initialization. */
 690 struct draw_stage* r300_draw_stage(struct r300_context* r300);
 691 void r300_init_blit_functions(struct r300_context *r300);
 692 void r300_init_flush_functions(struct r300_context* r300);
 693 void r300_init_query_functions(struct r300_context* r300);
 694 void r300_init_render_functions(struct r300_context *r300);
 695 void r300_init_state_functions(struct r300_context* r300);
 696 void r300_init_resource_functions(struct r300_context* r300);
 697
 698 /* r300_blit.c */
 699 void r300_decompress_zmask(struct r300_context *r300);
 700 void r300_decompress_zmask_locked_unsafe(struct r300_context *r300);
 701 void r300_decompress_zmask_locked(struct r300_context *r300);
 702
 703 /* r300_flush.c */
 704 void r300_flush(struct pipe_context *pipe,
 705                 unsigned flags,
 706                 struct pipe_fence_handle **fence);
 707
 708 /* r300_hyperz.c */
 709 void r300_update_hyperz_state(struct r300_context* r300);
 710
 711 /* r300_query.c */
 712 void r300_resume_query(struct r300_context *r300,
 713                        struct r300_query *query);
 714 void r300_stop_query(struct r300_context *r300);
 715
 716 /* r300_render_translate.c */
 717 void r300_translate_index_buffer(struct r300_context *r300,
 718                                  struct pipe_resource **index_buffer,
 719                                  unsigned *index_size, unsigned index_offset,
 720                                  unsigned *start, unsigned count);
 721
 722 /* r300_render_stencilref.c */
 723 void r300_plug_in_stencil_ref_fallback(struct r300_context *r300);
 724
 725 /* r300_render.c */
 726 void r300_draw_flush_vbuf(struct r300_context *r300);
 727 void r500_emit_index_bias(struct r300_context *r300, int index_bias);
 728
 729 /* r300_state.c */
 730 enum r300_fb_state_change {
 731     R300_CHANGED_FB_STATE = 0,
 732     R300_CHANGED_HYPERZ_FLAG,
 733     R300_CHANGED_MULTIWRITE
 734 };
 735
 736 void r300_mark_fb_state_dirty(struct r300_context *r300,
 737                               enum r300_fb_state_change change);
 738 void r300_mark_fs_code_dirty(struct r300_context *r300);
 739
 740 /* r300_state_derived.c */
 741 void r300_update_derived_state(struct r300_context* r300);
 742
 743 /* r300_debug.c */
 744 void r500_dump_rs_block(struct r300_rs_block *rs);
 745
 746
 747 static INLINE boolean CTX_DBG_ON(struct r300_context * ctx, unsigned flags)
 748 {
 749     return SCREEN_DBG_ON(ctx->screen, flags);
 750 }
 751
 752 static INLINE void CTX_DBG(struct r300_context * ctx, unsigned flags,
 753                        const char * fmt, ...)
 754 {
 755     if (CTX_DBG_ON(ctx, flags)) {
 756         va_list va;
 757         va_start(va, fmt);
 758         vfprintf(stderr, fmt, va);
 759         va_end(va);
 760     }
 761 }
 762
 763 #define DBG_ON  CTX_DBG_ON
 764 #define DBG     CTX_DBG
 765
 766 #endif /* R300_CONTEXT_H */