src/gallium/drivers/r300/r300_context.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  22
  23 #ifndef R300_CONTEXT_H
  24 #define R300_CONTEXT_H
  25
  26 #define R300_BUFFER_ALIGNMENT 64
  27
  28 #include "draw/draw_vertex.h"
  29
  30 #include "util/u_blitter.h"
  31
  32 #include "pipe/p_context.h"
  33 #include "util/u_inlines.h"
  34 #include "util/u_transfer.h"
  35
  36 #include "r300_defines.h"
  37 #include "r300_screen.h"
  38 #include "compiler/radeon_regalloc.h"
  39 #include "../../winsys/radeon/drm/radeon_winsys.h"
  40
  41 struct u_upload_mgr;
  42 struct r300_context;
  43 struct r300_fragment_shader;
  44 struct r300_vertex_shader;
  45 struct r300_stencilref_context;
  46
  47 enum colormask_swizzle {
  48     COLORMASK_BGRA,
  49     COLORMASK_RGBA,
  50     COLORMASK_RRRR,
  51     COLORMASK_AAAA,
  52     COLORMASK_GRRG,
  53     COLORMASK_ARRA,
  54     COLORMASK_NUM_SWIZZLES
  55 };
  56
  57 struct r300_atom {
  58     /* Name, for debugging. */
  59     const char* name;
  60     /* Opaque state. */
  61     void* state;
  62     /* Emit the state to the context. */
  63     void (*emit)(struct r300_context*, unsigned, void*);
  64     /* Upper bound on number of dwords to emit. */
  65     unsigned size;
  66     /* Whether this atom should be emitted. */
  67     boolean dirty;
  68     /* Whether this atom may be emitted with state == NULL. */
  69     boolean allow_null_state;
  70 };
  71
  72 struct r300_aa_state {
  73     struct r300_surface *dest;
  74
  75     uint32_t aa_config;
  76     uint32_t aaresolve_ctl;
  77 };
  78
  79 struct r300_blend_state {
  80     struct pipe_blend_state state;
  81
  82     uint32_t cb_clamp[COLORMASK_NUM_SWIZZLES][8];
  83     uint32_t cb_noclamp[8];
  84     uint32_t cb_no_readwrite[8];
  85 };
  86
  87 struct r300_blend_color_state {
  88     struct pipe_blend_color state;
  89     uint32_t cb[3];
  90 };
  91
  92 struct r300_clip_state {
  93     uint32_t cb[29];
  94 };
  95
  96 struct r300_dsa_state {
  97     struct pipe_depth_stencil_alpha_state dsa;
  98
  99     /* This is actually a command buffer with named dwords. */
 100     uint32_t cb_begin;
 101     uint32_t z_buffer_control;  /* R300_ZB_CNTL: 0x4f00 */
 102     uint32_t z_stencil_control; /* R300_ZB_ZSTENCILCNTL: 0x4f04 */
 103     uint32_t stencil_ref_mask;  /* R300_ZB_STENCILREFMASK: 0x4f08 */
 104     uint32_t cb_reg;
 105     uint32_t stencil_ref_bf;    /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */
 106     uint32_t cb_reg1;
 107     uint32_t alpha_value;       /* R500_FG_ALPHA_VALUE: 0x4be0 */
 108
 109     /* Same, but without ZB reads and writes. */
 110     uint32_t cb_zb_no_readwrite[8]; /* ZB not bound */
 111
 112     /* Emitted separately: */
 113     uint32_t alpha_function;
 114
 115     /* Whether a two-sided stencil is enabled. */
 116     boolean two_sided;
 117     /* Whether a fallback should be used for a two-sided stencil ref value. */
 118     boolean two_sided_stencil_ref;
 119 };
 120
 121 struct r300_hyperz_state {
 122     int flush;
 123     /* This is actually a command buffer with named dwords. */
 124     uint32_t cb_flush_begin;
 125     uint32_t zb_zcache_ctlstat;     /* R300_ZB_CACHE_CNTL */
 126     uint32_t cb_begin;
 127     uint32_t zb_bw_cntl;            /* R300_ZB_BW_CNTL */
 128     uint32_t cb_reg1;
 129     uint32_t zb_depthclearvalue;    /* R300_ZB_DEPTHCLEARVALUE */
 130     uint32_t cb_reg2;
 131     uint32_t sc_hyperz;             /* R300_SC_HYPERZ */
 132     uint32_t cb_reg3;
 133     uint32_t gb_z_peq_config;       /* R300_GB_Z_PEQ_CONFIG: 0x4028 */
 134 };
 135
 136 struct r300_gpu_flush {
 137     uint32_t cb_flush_clean[6];
 138 };
 139
 140 #define RS_STATE_MAIN_SIZE 27
 141
 142 struct r300_rs_state {
 143     /* Original rasterizer state. */
 144     struct pipe_rasterizer_state rs;
 145     /* Draw-specific rasterizer state. */
 146     struct pipe_rasterizer_state rs_draw;
 147
 148     /* Command buffers. */
 149     uint32_t cb_main[RS_STATE_MAIN_SIZE];
 150     uint32_t cb_poly_offset_zb16[5];
 151     uint32_t cb_poly_offset_zb24[5];
 152
 153     /* The index to cb_main where the cull_mode register value resides. */
 154     unsigned cull_mode_index;
 155
 156     /* Whether polygon offset is enabled. */
 157     boolean polygon_offset_enable;
 158
 159     /* This is emitted in the draw function. */
 160     uint32_t color_control;         /* R300_GA_COLOR_CONTROL: 0x4278 */
 161 };
 162
 163 struct r300_rs_block {
 164     uint32_t vap_vtx_state_cntl;  /* R300_VAP_VTX_STATE_CNTL: 0x2180 */
 165     uint32_t vap_vsm_vtx_assm;    /* R300_VAP_VSM_VTX_ASSM: 0x2184 */
 166     uint32_t vap_out_vtx_fmt[2];  /* R300_VAP_OUTPUT_VTX_FMT_[0-1]: 0x2090 */
 167     uint32_t gb_enable;
 168
 169     uint32_t ip[8]; /* R300_RS_IP_[0-7], R500_RS_IP_[0-7] */
 170     uint32_t count; /* R300_RS_COUNT */
 171     uint32_t inst_count; /* R300_RS_INST_COUNT */
 172     uint32_t inst[8]; /* R300_RS_INST_[0-7] */
 173 };
 174
 175 struct r300_sampler_state {
 176     struct pipe_sampler_state state;
 177
 178     uint32_t filter0;      /* R300_TX_FILTER0: 0x4400 */
 179     uint32_t filter1;      /* R300_TX_FILTER1: 0x4440 */
 180
 181     /* Min/max LOD must be clamped to [0, last_level], thus
 182      * it's dependent on a currently bound texture */
 183     unsigned min_lod, max_lod;
 184 };
 185
 186 struct r300_texture_format_state {
 187     uint32_t format0; /* R300_TX_FORMAT0: 0x4480 */
 188     uint32_t format1; /* R300_TX_FORMAT1: 0x44c0 */
 189     uint32_t format2; /* R300_TX_FORMAT2: 0x4500 */
 190     uint32_t tile_config; /* R300_TX_OFFSET (subset thereof) */
 191     uint32_t us_format0;   /* R500_US_FORMAT0_0: 0x4640 (through 15) */
 192 };
 193
 194 struct r300_sampler_view {
 195     struct pipe_sampler_view base;
 196
 197     /* For resource_copy_region. */
 198     unsigned width0_override;
 199     unsigned height0_override;
 200
 201     /* Swizzles in the UTIL_FORMAT_SWIZZLE_* representation,
 202      * derived from base. */
 203     unsigned char swizzle[4];
 204
 205     /* Copy of r300_texture::texture_format_state with format-specific bits
 206      * added. */
 207     struct r300_texture_format_state format;
 208
 209     /* The texture cache region for this texture. */
 210     uint32_t texcache_region;
 211 };
 212
 213 struct r300_texture_sampler_state {
 214     struct r300_texture_format_state format;
 215     uint32_t filter0;      /* R300_TX_FILTER0: 0x4400 */
 216     uint32_t filter1;      /* R300_TX_FILTER1: 0x4440 */
 217     uint32_t border_color; /* R300_TX_BORDER_COLOR: 0x45c0 */
 218 };
 219
 220 struct r300_textures_state {
 221     /* Textures. */
 222     struct r300_sampler_view *sampler_views[16];
 223     int sampler_view_count;
 224     /* Sampler states. */
 225     struct r300_sampler_state *sampler_states[16];
 226     int sampler_state_count;
 227
 228     /* This is the merge of the texture and sampler states. */
 229     unsigned count;
 230     uint32_t tx_enable;         /* R300_TX_ENABLE: 0x4101 */
 231     struct r300_texture_sampler_state regs[16];
 232 };
 233
 234 struct r300_vertex_stream_state {
 235     /* R300_VAP_PROG_STREAK_CNTL_[0-7] */
 236     uint32_t vap_prog_stream_cntl[8];
 237     /* R300_VAP_PROG_STREAK_CNTL_EXT_[0-7] */
 238     uint32_t vap_prog_stream_cntl_ext[8];
 239
 240     unsigned count;
 241 };
 242
 243 struct r300_invariant_state {
 244     uint32_t cb[24];
 245 };
 246
 247 struct r300_vap_invariant_state {
 248     uint32_t cb[11];
 249 };
 250
 251 struct r300_viewport_state {
 252     float xscale;         /* R300_VAP_VPORT_XSCALE:  0x2098 */
 253     float xoffset;        /* R300_VAP_VPORT_XOFFSET: 0x209c */
 254     float yscale;         /* R300_VAP_VPORT_YSCALE:  0x20a0 */
 255     float yoffset;        /* R300_VAP_VPORT_YOFFSET: 0x20a4 */
 256     float zscale;         /* R300_VAP_VPORT_ZSCALE:  0x20a8 */
 257     float zoffset;        /* R300_VAP_VPORT_ZOFFSET: 0x20ac */
 258     uint32_t vte_control; /* R300_VAP_VTE_CNTL:      0x20b0 */
 259 };
 260
 261 struct r300_ztop_state {
 262     uint32_t z_buffer_top;      /* R300_ZB_ZTOP: 0x4f14 */
 263 };
 264
 265 /* The next several objects are not pure Radeon state; they inherit from
 266  * various Gallium classes. */
 267
 268 struct r300_constant_buffer {
 269     /* Buffer of constants */
 270     uint32_t *ptr;
 271     /* Remapping table. */
 272     unsigned *remap_table;
 273     /* const buffer base */
 274     uint32_t buffer_base;
 275 };
 276
 277 /* Query object.
 278  *
 279  * This is not a subclass of pipe_query because pipe_query is never
 280  * actually fully defined. So, rather than have it as a member, and do
 281  * subclass-style casting, we treat pipe_query as an opaque, and just
 282  * trust that our state tracker does not ever mess up query objects.
 283  */
 284 struct r300_query {
 285     /* The kind of query. Currently only OQ is supported. */
 286     unsigned type;
 287     /* The number of pipes where query results are stored. */
 288     unsigned num_pipes;
 289     /* How many results have been written, in dwords. It's incremented
 290      * after end_query and flush. */
 291     unsigned num_results;
 292     /* if begin has been emitted */
 293     boolean begin_emitted;
 294
 295     /* The buffer where query results are stored. */
 296     struct pb_buffer *buf;
 297     struct radeon_winsys_cs_handle *cs_buf;
 298 };
 299
 300 struct r300_surface {
 301     struct pipe_surface base;
 302
 303     /* Winsys buffer backing the texture. */
 304     struct pb_buffer *buf;
 305     struct radeon_winsys_cs_handle *cs_buf;
 306
 307     enum radeon_bo_domain domain;
 308
 309     uint32_t offset;    /* COLOROFFSET or DEPTHOFFSET. */
 310     uint32_t pitch;     /* COLORPITCH or DEPTHPITCH. */
 311     uint32_t pitch_zmask; /* ZMASK_PITCH */
 312     uint32_t pitch_hiz;   /* HIZ_PITCH */
 313     uint32_t format;    /* US_OUT_FMT or ZB_FORMAT. */
 314
 315     /* Parameters dedicated to the CBZB clear. */
 316     uint32_t cbzb_width;            /* Aligned width. */
 317     uint32_t cbzb_height;           /* Half of the height. */
 318     uint32_t cbzb_midpoint_offset;  /* DEPTHOFFSET. */
 319     uint32_t cbzb_pitch;            /* DEPTHPITCH. */
 320     uint32_t cbzb_format;           /* ZB_FORMAT. */
 321
 322     /* Whether the CBZB clear is allowed on the surface. */
 323     boolean cbzb_allowed;
 324
 325     unsigned colormask_swizzle;
 326 };
 327
 328 struct r300_texture_desc {
 329     /* Width, height, and depth.
 330      * Most of the time, these are equal to pipe_texture::width0, height0,
 331      * and depth0. However, NPOT 3D textures must have dimensions aligned
 332      * to POT, and this is the only case when these variables differ from
 333      * pipe_texture. */
 334     unsigned width0, height0, depth0;
 335
 336     /* Buffer tiling.
 337      * Macrotiling is specified per-level because small mipmaps cannot
 338      * be macrotiled. */
 339     enum radeon_bo_layout microtile;
 340     enum radeon_bo_layout macrotile[R300_MAX_TEXTURE_LEVELS];
 341
 342     /* Offsets into the buffer. */
 343     unsigned offset_in_bytes[R300_MAX_TEXTURE_LEVELS];
 344
 345     /* Strides for each mip-level. */
 346     unsigned stride_in_bytes[R300_MAX_TEXTURE_LEVELS];
 347
 348     /* Size of one zslice or face or 2D image based on the texture target. */
 349     unsigned layer_size_in_bytes[R300_MAX_TEXTURE_LEVELS];
 350
 351     /* Total size of this texture, in bytes,
 352      * derived from the texture properties. */
 353     unsigned size_in_bytes;
 354
 355     /**
 356      * If non-zero, override the natural texture layout with
 357      * a custom stride (in bytes).
 358      *
 359      * \note Mipmapping fails for textures with a non-natural layout!
 360      *
 361      * \sa r300_texture_get_stride
 362      */
 363     unsigned stride_in_bytes_override;
 364
 365     /* Whether this texture has non-power-of-two dimensions.
 366      * It can be either a regular texture or a rectangle one. */
 367     boolean is_npot;
 368
 369     /* This flag says that hardware must use the stride for addressing
 370      * instead of the width. */
 371     boolean uses_stride_addressing;
 372
 373     /* Whether CBZB fast color clear is allowed on the miplevel. */
 374     boolean cbzb_allowed[R300_MAX_TEXTURE_LEVELS];
 375
 376     /* Zbuffer compression info for each miplevel. */
 377     boolean zcomp8x8[R300_MAX_TEXTURE_LEVELS];
 378     /* If zero, then disable Z compression/HiZ. */
 379     unsigned zmask_dwords[R300_MAX_TEXTURE_LEVELS];
 380     unsigned hiz_dwords[R300_MAX_TEXTURE_LEVELS];
 381     /* Zmask/HiZ strides for each miplevel. */
 382     unsigned zmask_stride_in_pixels[R300_MAX_TEXTURE_LEVELS];
 383     unsigned hiz_stride_in_pixels[R300_MAX_TEXTURE_LEVELS];
 384 };
 385
 386 struct r300_resource
 387 {
 388     struct u_resource b;
 389
 390     /* Winsys buffer backing this resource. */
 391     struct pb_buffer *buf;
 392     struct radeon_winsys_cs_handle *cs_buf;
 393     enum radeon_bo_domain domain;
 394
 395     /* Constant buffers and SWTCL vertex and index buffers are in user
 396      * memory. */
 397     uint8_t *malloced_buffer;
 398
 399     /* Texture description (addressing, layout, special features). */
 400     struct r300_texture_desc tex;
 401
 402     /* This is the level tiling flags were last time set for.
 403      * It's used to prevent redundant tiling-flags changes from happening.*/
 404     unsigned surface_level;
 405 };
 406
 407 struct r300_vertex_element_state {
 408     unsigned count;
 409     struct pipe_vertex_element velem[PIPE_MAX_ATTRIBS];
 410     unsigned format_size[PIPE_MAX_ATTRIBS];
 411
 412     /* The size of the vertex, in dwords. */
 413     unsigned vertex_size_dwords;
 414
 415     struct r300_vertex_stream_state vertex_stream;
 416 };
 417
 418 enum r300_hiz_func {
 419     HIZ_FUNC_NONE,
 420
 421     /* The function, when determined, is set in stone
 422      * until the next HiZ clear. */
 423
 424     /* MAX is written to the HiZ buffer.
 425      * Used for LESS, LEQUAL. */
 426     HIZ_FUNC_MAX,
 427
 428     /* MIN is written to the HiZ buffer.
 429      * Used for GREATER, GEQUAL. */
 430     HIZ_FUNC_MIN,
 431 };
 432
 433 /* For deferred fragment shader state validation. */
 434 enum r300_fs_validity_status {
 435     FRAGMENT_SHADER_VALID,      /* No need to change/validate the FS. */
 436     FRAGMENT_SHADER_MAYBE_DIRTY,/* Validate the FS if external state was changed. */
 437     FRAGMENT_SHADER_DIRTY       /* Always validate the FS (if the FS was changed) */
 438 };
 439
 440 struct r300_context {
 441     /* Parent class */
 442     struct pipe_context context;
 443
 444     /* The interface to the windowing system, etc. */
 445     struct radeon_winsys *rws;
 446     /* The command stream. */
 447     struct radeon_winsys_cs *cs;
 448     /* Screen. */
 449     struct r300_screen *screen;
 450
 451     /* Draw module. Used mostly for SW TCL. */
 452     struct draw_context* draw;
 453     /* Vertex buffer for SW TCL. */
 454     struct pb_buffer *vbo;
 455     struct radeon_winsys_cs_handle *vbo_cs;
 456     /* Offset and size into the SW TCL VBO. */
 457     size_t draw_vbo_offset;
 458
 459     /* Accelerated blit support. */
 460     struct blitter_context* blitter;
 461     /* Stencil two-sided reference value fallback. */
 462     struct r300_stencilref_context *stencilref_fallback;
 463
 464     /* The KIL opcode needs the first texture unit to be enabled
 465      * on r3xx-r4xx. In order to calm down the CS checker, we bind this
 466      * dummy texture there. */
 467     struct r300_sampler_view *texkill_sampler;
 468
 469     /* When no vertex buffer is set, this one is used instead to prevent
 470      * hardlocks. */
 471     struct pipe_vertex_buffer dummy_vb;
 472
 473     /* The currently active query. */
 474     struct r300_query *query_current;
 475     /* The saved query for blitter operations. */
 476     struct r300_query *blitter_saved_query;
 477     /* Query list. */
 478     struct r300_query query_list;
 479
 480     /* Various CSO state objects. */
 481
 482     /* Each atom is emitted in the order it appears here, which can affect
 483      * performance and stability if not handled with care. */
 484     /* GPU flush. */
 485     struct r300_atom gpu_flush;
 486     /* Anti-aliasing (MSAA) state. */
 487     struct r300_atom aa_state;
 488     /* Framebuffer state. */
 489     struct r300_atom fb_state;
 490     /* HyperZ state (various SC/ZB bits). */
 491     struct r300_atom hyperz_state;
 492     /* ZTOP state. */
 493     struct r300_atom ztop_state;
 494     /* Depth, stencil, and alpha state. */
 495     struct r300_atom dsa_state;
 496     /* Blend state. */
 497     struct r300_atom blend_state;
 498     /* Blend color state. */
 499     struct r300_atom blend_color_state;
 500     /* Scissor state. */
 501     struct r300_atom scissor_state;
 502     /* Invariant state. This must be emitted to get the engine started. */
 503     struct r300_atom invariant_state;
 504     /* Viewport state. */
 505     struct r300_atom viewport_state;
 506     /* PVS flush. */
 507     struct r300_atom pvs_flush;
 508     /* VAP invariant state. */
 509     struct r300_atom vap_invariant_state;
 510     /* Vertex stream formatting state. */
 511     struct r300_atom vertex_stream_state;
 512     /* Vertex shader. */
 513     struct r300_atom vs_state;
 514     /* User clip planes. */
 515     struct r300_atom clip_state;
 516     /* RS block state + VAP (vertex shader) output mapping state. */
 517     struct r300_atom rs_block_state;
 518     /* Rasterizer state. */
 519     struct r300_atom rs_state;
 520     /* Framebuffer state (pipelined regs). */
 521     struct r300_atom fb_state_pipelined;
 522     /* Fragment shader. */
 523     struct r300_atom fs;
 524     /* Fragment shader RC_CONSTANT_STATE variables. */
 525     struct r300_atom fs_rc_constant_state;
 526     /* Fragment shader constant buffer. */
 527     struct r300_atom fs_constants;
 528     /* Vertex shader constant buffer. */
 529     struct r300_atom vs_constants;
 530     /* Texture cache invalidate. */
 531     struct r300_atom texture_cache_inval;
 532     /* Textures state. */
 533     struct r300_atom textures_state;
 534     /* HiZ clear */
 535     struct r300_atom hiz_clear;
 536     /* zmask clear */
 537     struct r300_atom zmask_clear;
 538     /* Occlusion query. */
 539     struct r300_atom query_start;
 540
 541     /* The pointers to the first and the last atom. */
 542     struct r300_atom *first_dirty, *last_dirty;
 543
 544     /* Vertex elements for Gallium. */
 545     struct r300_vertex_element_state *velems;
 546
 547     /* Vertex info for Draw. */
 548     struct vertex_info vertex_info;
 549
 550     struct pipe_stencil_ref stencil_ref;
 551     struct pipe_viewport_state viewport;
 552
 553     /* Stream locations for SWTCL. */
 554     int stream_loc_notcl[16];
 555
 556     /* Flag indicating whether or not the HW is dirty. */
 557     uint32_t dirty_hw;
 558     /* Whether polygon offset is enabled. */
 559     boolean polygon_offset_enabled;
 560     /* Z buffer bit depth. */
 561     uint32_t zbuffer_bpp;
 562     /* Whether rendering is conditional and should be skipped. */
 563     boolean skip_rendering;
 564     /* The flag above saved by blitter. */
 565     unsigned char blitter_saved_skip_rendering;
 566     /* Point sprites texcoord index,  1 bit per texcoord */
 567     int sprite_coord_enable;
 568     /* Whether two-sided color selection is enabled (AKA light_twoside). */
 569     boolean two_sided_color;
 570     /* Whether fast color clear is enabled. */
 571     boolean cbzb_clear;
 572     /* Whether fragment shader needs to be validated. */
 573     enum r300_fs_validity_status fs_status;
 574     /* Framebuffer multi-write. */
 575     boolean fb_multiwrite;
 576
 577     void *dsa_decompress_zmask;
 578
 579     struct pipe_index_buffer index_buffer;
 580     struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 581     unsigned nr_vertex_buffers;
 582     struct u_upload_mgr *uploader;
 583
 584     struct util_slab_mempool pool_transfers;
 585
 586     /* Stat counter. */
 587     uint64_t flush_counter;
 588
 589     /* const tracking for VS */
 590     int vs_const_base;
 591
 592     /* Vertex array state info */
 593     boolean vertex_arrays_dirty;
 594     boolean vertex_arrays_indexed;
 595     int vertex_arrays_offset;
 596     int vertex_arrays_instance_id;
 597     boolean instancing_enabled;
 598
 599     /* Hyper-Z stats. */
 600     boolean hyperz_enabled;     /* Whether it owns Hyper-Z access. */
 601     int64_t hyperz_time_of_last_flush; /* Time of the last flush with Z clear. */
 602     unsigned num_z_clears;      /* Since the last flush. */
 603
 604     /* ZMask state. */
 605     boolean zmask_in_use;       /* Whether ZMASK is enabled. */
 606     boolean zmask_decompress;   /* Whether ZMASK is being decompressed. */
 607     struct pipe_surface *locked_zbuffer; /* Unbound zbuffer which still has data in ZMASK. */
 608
 609     /* HiZ state. */
 610     boolean hiz_in_use;         /* Whether HIZ is enabled. */
 611     enum r300_hiz_func hiz_func; /* HiZ function. Can be either MIN or MAX. */
 612     uint32_t hiz_clear_value;   /* HiZ clear value. */
 613
 614     /* Compiler state. */
 615     struct rc_regalloc_state fs_regalloc_state; /* Register allocator info for
 616                                                  * fragment shaders. */
 617 };
 618
 619 #define foreach_atom(r300, atom) \
 620     for (atom = &r300->gpu_flush; atom != (&r300->query_start)+1; atom++)
 621
 622 #define foreach_dirty_atom(r300, atom) \
 623     for (atom = r300->first_dirty; atom != r300->last_dirty; atom++)
 624
 625 /* Convenience cast wrappers. */
 626 static INLINE struct r300_query* r300_query(struct pipe_query* q)
 627 {
 628     return (struct r300_query*)q;
 629 }
 630
 631 static INLINE struct r300_surface* r300_surface(struct pipe_surface* surf)
 632 {
 633     return (struct r300_surface*)surf;
 634 }
 635
 636 static INLINE struct r300_resource* r300_resource(struct pipe_resource* tex)
 637 {
 638     return (struct r300_resource*)tex;
 639 }
 640
 641 static INLINE struct r300_context* r300_context(struct pipe_context* context)
 642 {
 643     return (struct r300_context*)context;
 644 }
 645
 646 static INLINE struct r300_fragment_shader *r300_fs(struct r300_context *r300)
 647 {
 648     return (struct r300_fragment_shader*)r300->fs.state;
 649 }
 650
 651 static INLINE void r300_mark_atom_dirty(struct r300_context *r300,
 652                                         struct r300_atom *atom)
 653 {
 654     atom->dirty = TRUE;
 655
 656     if (!r300->first_dirty) {
 657         r300->first_dirty = atom;
 658         r300->last_dirty = atom+1;
 659     } else {
 660         if (atom < r300->first_dirty)
 661             r300->first_dirty = atom;
 662         else if (atom+1 > r300->last_dirty)
 663             r300->last_dirty = atom+1;
 664     }
 665 }
 666
 667 struct pipe_context* r300_create_context(struct pipe_screen* screen,
 668                                          void *priv);
 669
 670 /* Context initialization. */
 671 struct draw_stage* r300_draw_stage(struct r300_context* r300);
 672 void r300_init_blit_functions(struct r300_context *r300);
 673 void r300_init_flush_functions(struct r300_context* r300);
 674 void r300_init_query_functions(struct r300_context* r300);
 675 void r300_init_render_functions(struct r300_context *r300);
 676 void r300_init_state_functions(struct r300_context* r300);
 677 void r300_init_resource_functions(struct r300_context* r300);
 678
 679 /* r300_blit.c */
 680 void r300_decompress_zmask(struct r300_context *r300);
 681 void r300_decompress_zmask_locked_unsafe(struct r300_context *r300);
 682 void r300_decompress_zmask_locked(struct r300_context *r300);
 683 bool r300_is_blit_supported(enum pipe_format format);
 684
 685 /* r300_flush.c */
 686 void r300_flush(struct pipe_context *pipe,
 687                 unsigned flags,
 688                 struct pipe_fence_handle **fence);
 689
 690 /* r300_hyperz.c */
 691 void r300_update_hyperz_state(struct r300_context* r300);
 692
 693 /* r300_query.c */
 694 void r300_resume_query(struct r300_context *r300,
 695                        struct r300_query *query);
 696 void r300_stop_query(struct r300_context *r300);
 697
 698 /* r300_render_translate.c */
 699 void r300_translate_index_buffer(struct r300_context *r300,
 700                                  struct pipe_index_buffer *ib,
 701                                  struct pipe_resource **out_index_buffer,
 702                                  unsigned *index_size, unsigned index_offset,
 703                                  unsigned *start, unsigned count);
 704
 705 /* r300_render_stencilref.c */
 706 void r300_plug_in_stencil_ref_fallback(struct r300_context *r300);
 707
 708 /* r300_render.c */
 709 void r500_emit_index_bias(struct r300_context *r300, int index_bias);
 710 void r300_blitter_draw_rectangle(struct blitter_context *blitter,
 711                                  int x1, int y1, int x2, int y2,
 712                                  float depth,
 713                                  enum blitter_attrib_type type,
 714                                  const union pipe_color_union *attrib);
 715
 716 /* r300_state.c */
 717 enum r300_fb_state_change {
 718     R300_CHANGED_FB_STATE = 0,
 719     R300_CHANGED_HYPERZ_FLAG,
 720     R300_CHANGED_MULTIWRITE
 721 };
 722
 723 void r300_mark_fb_state_dirty(struct r300_context *r300,
 724                               enum r300_fb_state_change change);
 725 void r300_mark_fs_code_dirty(struct r300_context *r300);
 726
 727 struct pipe_sampler_view *
 728 r300_create_sampler_view_custom(struct pipe_context *pipe,
 729                          struct pipe_resource *texture,
 730                          const struct pipe_sampler_view *templ,
 731                          unsigned width0_override,
 732                          unsigned height0_override);
 733
 734 /* r300_state_derived.c */
 735 void r300_update_derived_state(struct r300_context* r300);
 736
 737 /* r300_debug.c */
 738 void r500_dump_rs_block(struct r300_rs_block *rs);
 739
 740
 741 static INLINE boolean CTX_DBG_ON(struct r300_context * ctx, unsigned flags)
 742 {
 743     return SCREEN_DBG_ON(ctx->screen, flags);
 744 }
 745
 746 static INLINE void CTX_DBG(struct r300_context * ctx, unsigned flags,
 747                        const char * fmt, ...)
 748 {
 749     if (CTX_DBG_ON(ctx, flags)) {
 750         va_list va;
 751         va_start(va, fmt);
 752         vfprintf(stderr, fmt, va);
 753         va_end(va);
 754     }
 755 }
 756
 757 #define DBG_ON  CTX_DBG_ON
 758 #define DBG     CTX_DBG
 759
 760 #endif /* R300_CONTEXT_H */