src/gallium/drivers/r300/r300_context.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  22
  23 #ifndef R300_CONTEXT_H
  24 #define R300_CONTEXT_H
  25
  26 #include "draw/draw_vertex.h"
  27
  28 #include "util/u_blitter.h"
  29
  30 #include "pipe/p_context.h"
  31 #include "util/u_inlines.h"
  32 #include "util/u_transfer.h"
  33
  34 #include "r300_defines.h"
  35 #include "r300_screen.h"
  36 #include "compiler/radeon_regalloc.h"
  37 #include "../../winsys/radeon/drm/radeon_winsys.h"
  38
  39 struct u_upload_mgr;
  40 struct r300_context;
  41 struct r300_fragment_shader;
  42 struct r300_vertex_shader;
  43 struct r300_stencilref_context;
  44
  45 enum colormask_swizzle {
  46     COLORMASK_BGRA,
  47     COLORMASK_RGBA,
  48     COLORMASK_RRRR,
  49     COLORMASK_AAAA,
  50     COLORMASK_GRRG,
  51     COLORMASK_ARRA,
  52     COLORMASK_NUM_SWIZZLES
  53 };
  54
  55 struct r300_atom {
  56     /* Name, for debugging. */
  57     const char* name;
  58     /* Opaque state. */
  59     void* state;
  60     /* Emit the state to the context. */
  61     void (*emit)(struct r300_context*, unsigned, void*);
  62     /* Upper bound on number of dwords to emit. */
  63     unsigned size;
  64     /* Whether this atom should be emitted. */
  65     boolean dirty;
  66     /* Whether this atom may be emitted with state == NULL. */
  67     boolean allow_null_state;
  68 };
  69
  70 struct r300_aa_state {
  71     struct r300_surface *dest;
  72
  73     uint32_t aa_config;
  74     uint32_t aaresolve_ctl;
  75 };
  76
  77 struct r300_blend_state {
  78     struct pipe_blend_state state;
  79
  80     uint32_t cb_clamp[COLORMASK_NUM_SWIZZLES][8];
  81     uint32_t cb_noclamp[8];
  82     uint32_t cb_no_readwrite[8];
  83 };
  84
  85 struct r300_blend_color_state {
  86     struct pipe_blend_color state;
  87     uint32_t cb[3];
  88 };
  89
  90 struct r300_clip_state {
  91     uint32_t cb[29];
  92 };
  93
  94 struct r300_dsa_state {
  95     struct pipe_depth_stencil_alpha_state dsa;
  96
  97     /* This is actually a command buffer with named dwords. */
  98     uint32_t cb_begin;
  99     uint32_t alpha_function;    /* R300_FG_ALPHA_FUNC: 0x4bd4 */
 100     uint32_t cb_reg_seq;
 101     uint32_t z_buffer_control;  /* R300_ZB_CNTL: 0x4f00 */
 102     uint32_t z_stencil_control; /* R300_ZB_ZSTENCILCNTL: 0x4f04 */
 103     uint32_t stencil_ref_mask;  /* R300_ZB_STENCILREFMASK: 0x4f08 */
 104     uint32_t cb_reg;
 105     uint32_t stencil_ref_bf;    /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */
 106     uint32_t cb_reg1;
 107     uint32_t alpha_value;       /* R500_FG_ALPHA_VALUE: 0x4be0 */
 108
 109     /* The same, but for FP16 alpha test. */
 110     uint32_t cb_begin_fp16;
 111     uint32_t alpha_function_fp16;    /* R300_FG_ALPHA_FUNC: 0x4bd4 */
 112     uint32_t cb_reg_seq_fp16;
 113     uint32_t z_buffer_control_fp16;  /* R300_ZB_CNTL: 0x4f00 */
 114     uint32_t z_stencil_control_fp16; /* R300_ZB_ZSTENCILCNTL: 0x4f04 */
 115     uint32_t stencil_ref_mask_fp16;  /* R300_ZB_STENCILREFMASK: 0x4f08 */
 116     uint32_t cb_reg_fp16;
 117     uint32_t stencil_ref_bf_fp16;    /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */
 118     uint32_t cb_reg1_fp16;
 119     uint32_t alpha_value_fp16;       /* R500_FG_ALPHA_VALUE: 0x4be0 */
 120
 121     /* The second command buffer disables zbuffer reads and writes. */
 122     uint32_t cb_zb_no_readwrite[10];
 123     uint32_t cb_fp16_zb_no_readwrite[10];
 124
 125     /* Whether a two-sided stencil is enabled. */
 126     boolean two_sided;
 127     /* Whether a fallback should be used for a two-sided stencil ref value. */
 128     boolean two_sided_stencil_ref;
 129 };
 130
 131 struct r300_hyperz_state {
 132     int flush;
 133     /* This is actually a command buffer with named dwords. */
 134     uint32_t cb_flush_begin;
 135     uint32_t zb_zcache_ctlstat;     /* R300_ZB_CACHE_CNTL */
 136     uint32_t cb_begin;
 137     uint32_t zb_bw_cntl;            /* R300_ZB_BW_CNTL */
 138     uint32_t cb_reg1;
 139     uint32_t zb_depthclearvalue;    /* R300_ZB_DEPTHCLEARVALUE */
 140     uint32_t cb_reg2;
 141     uint32_t sc_hyperz;             /* R300_SC_HYPERZ */
 142     uint32_t cb_reg3;
 143     uint32_t gb_z_peq_config;       /* R300_GB_Z_PEQ_CONFIG: 0x4028 */
 144 };
 145
 146 struct r300_gpu_flush {
 147     uint32_t cb_flush_clean[6];
 148 };
 149
 150 #define RS_STATE_MAIN_SIZE 27
 151
 152 struct r300_rs_state {
 153     /* Original rasterizer state. */
 154     struct pipe_rasterizer_state rs;
 155     /* Draw-specific rasterizer state. */
 156     struct pipe_rasterizer_state rs_draw;
 157
 158     /* Command buffers. */
 159     uint32_t cb_main[RS_STATE_MAIN_SIZE];
 160     uint32_t cb_poly_offset_zb16[5];
 161     uint32_t cb_poly_offset_zb24[5];
 162
 163     /* The index to cb_main where the cull_mode register value resides. */
 164     unsigned cull_mode_index;
 165
 166     /* Whether polygon offset is enabled. */
 167     boolean polygon_offset_enable;
 168
 169     /* This is emitted in the draw function. */
 170     uint32_t color_control;         /* R300_GA_COLOR_CONTROL: 0x4278 */
 171 };
 172
 173 struct r300_rs_block {
 174     uint32_t vap_vtx_state_cntl;  /* R300_VAP_VTX_STATE_CNTL: 0x2180 */
 175     uint32_t vap_vsm_vtx_assm;    /* R300_VAP_VSM_VTX_ASSM: 0x2184 */
 176     uint32_t vap_out_vtx_fmt[2];  /* R300_VAP_OUTPUT_VTX_FMT_[0-1]: 0x2090 */
 177     uint32_t gb_enable;
 178
 179     uint32_t ip[8]; /* R300_RS_IP_[0-7], R500_RS_IP_[0-7] */
 180     uint32_t count; /* R300_RS_COUNT */
 181     uint32_t inst_count; /* R300_RS_INST_COUNT */
 182     uint32_t inst[8]; /* R300_RS_INST_[0-7] */
 183 };
 184
 185 struct r300_sampler_state {
 186     struct pipe_sampler_state state;
 187
 188     uint32_t filter0;      /* R300_TX_FILTER0: 0x4400 */
 189     uint32_t filter1;      /* R300_TX_FILTER1: 0x4440 */
 190
 191     /* Min/max LOD must be clamped to [0, last_level], thus
 192      * it's dependent on a currently bound texture */
 193     unsigned min_lod, max_lod;
 194 };
 195
 196 struct r300_texture_format_state {
 197     uint32_t format0; /* R300_TX_FORMAT0: 0x4480 */
 198     uint32_t format1; /* R300_TX_FORMAT1: 0x44c0 */
 199     uint32_t format2; /* R300_TX_FORMAT2: 0x4500 */
 200     uint32_t tile_config; /* R300_TX_OFFSET (subset thereof) */
 201     uint32_t us_format0;   /* R500_US_FORMAT0_0: 0x4640 (through 15) */
 202 };
 203
 204 struct r300_sampler_view {
 205     struct pipe_sampler_view base;
 206
 207     /* For resource_copy_region. */
 208     unsigned width0_override;
 209     unsigned height0_override;
 210
 211     /* Swizzles in the UTIL_FORMAT_SWIZZLE_* representation,
 212      * derived from base. */
 213     unsigned char swizzle[4];
 214
 215     /* Copy of r300_texture::texture_format_state with format-specific bits
 216      * added. */
 217     struct r300_texture_format_state format;
 218
 219     /* The texture cache region for this texture. */
 220     uint32_t texcache_region;
 221 };
 222
 223 struct r300_texture_sampler_state {
 224     struct r300_texture_format_state format;
 225     uint32_t filter0;      /* R300_TX_FILTER0: 0x4400 */
 226     uint32_t filter1;      /* R300_TX_FILTER1: 0x4440 */
 227     uint32_t border_color; /* R300_TX_BORDER_COLOR: 0x45c0 */
 228 };
 229
 230 struct r300_textures_state {
 231     /* Textures. */
 232     struct r300_sampler_view *sampler_views[16];
 233     int sampler_view_count;
 234     /* Sampler states. */
 235     struct r300_sampler_state *sampler_states[16];
 236     int sampler_state_count;
 237
 238     /* This is the merge of the texture and sampler states. */
 239     unsigned count;
 240     uint32_t tx_enable;         /* R300_TX_ENABLE: 0x4101 */
 241     struct r300_texture_sampler_state regs[16];
 242 };
 243
 244 struct r300_vertex_stream_state {
 245     /* R300_VAP_PROG_STREAK_CNTL_[0-7] */
 246     uint32_t vap_prog_stream_cntl[8];
 247     /* R300_VAP_PROG_STREAK_CNTL_EXT_[0-7] */
 248     uint32_t vap_prog_stream_cntl_ext[8];
 249
 250     unsigned count;
 251 };
 252
 253 struct r300_invariant_state {
 254     uint32_t cb[24];
 255 };
 256
 257 struct r300_vap_invariant_state {
 258     uint32_t cb[11];
 259 };
 260
 261 struct r300_viewport_state {
 262     float xscale;         /* R300_VAP_VPORT_XSCALE:  0x2098 */
 263     float xoffset;        /* R300_VAP_VPORT_XOFFSET: 0x209c */
 264     float yscale;         /* R300_VAP_VPORT_YSCALE:  0x20a0 */
 265     float yoffset;        /* R300_VAP_VPORT_YOFFSET: 0x20a4 */
 266     float zscale;         /* R300_VAP_VPORT_ZSCALE:  0x20a8 */
 267     float zoffset;        /* R300_VAP_VPORT_ZOFFSET: 0x20ac */
 268     uint32_t vte_control; /* R300_VAP_VTE_CNTL:      0x20b0 */
 269 };
 270
 271 struct r300_ztop_state {
 272     uint32_t z_buffer_top;      /* R300_ZB_ZTOP: 0x4f14 */
 273 };
 274
 275 /* The next several objects are not pure Radeon state; they inherit from
 276  * various Gallium classes. */
 277
 278 struct r300_constant_buffer {
 279     /* Buffer of constants */
 280     uint32_t *ptr;
 281     /* Remapping table. */
 282     unsigned *remap_table;
 283     /* const buffer base */
 284     uint32_t buffer_base;
 285 };
 286
 287 /* Query object.
 288  *
 289  * This is not a subclass of pipe_query because pipe_query is never
 290  * actually fully defined. So, rather than have it as a member, and do
 291  * subclass-style casting, we treat pipe_query as an opaque, and just
 292  * trust that our state tracker does not ever mess up query objects.
 293  */
 294 struct r300_query {
 295     /* The kind of query. Currently only OQ is supported. */
 296     unsigned type;
 297     /* The number of pipes where query results are stored. */
 298     unsigned num_pipes;
 299     /* How many results have been written, in dwords. It's incremented
 300      * after end_query and flush. */
 301     unsigned num_results;
 302     /* if begin has been emitted */
 303     boolean begin_emitted;
 304
 305     /* The buffer where query results are stored. */
 306     struct pb_buffer *buf;
 307     struct radeon_winsys_cs_handle *cs_buf;
 308 };
 309
 310 struct r300_surface {
 311     struct pipe_surface base;
 312
 313     /* Winsys buffer backing the texture. */
 314     struct pb_buffer *buf;
 315     struct radeon_winsys_cs_handle *cs_buf;
 316
 317     enum radeon_bo_domain domain;
 318
 319     uint32_t offset;    /* COLOROFFSET or DEPTHOFFSET. */
 320     uint32_t pitch;     /* COLORPITCH or DEPTHPITCH. */
 321     uint32_t pitch_zmask; /* ZMASK_PITCH */
 322     uint32_t pitch_hiz;   /* HIZ_PITCH */
 323     uint32_t format;    /* US_OUT_FMT or ZB_FORMAT. */
 324
 325     /* Parameters dedicated to the CBZB clear. */
 326     uint32_t cbzb_width;            /* Aligned width. */
 327     uint32_t cbzb_height;           /* Half of the height. */
 328     uint32_t cbzb_midpoint_offset;  /* DEPTHOFFSET. */
 329     uint32_t cbzb_pitch;            /* DEPTHPITCH. */
 330     uint32_t cbzb_format;           /* ZB_FORMAT. */
 331
 332     /* Whether the CBZB clear is allowed on the surface. */
 333     boolean cbzb_allowed;
 334
 335     unsigned colormask_swizzle;
 336 };
 337
 338 struct r300_texture_desc {
 339     /* Width, height, and depth.
 340      * Most of the time, these are equal to pipe_texture::width0, height0,
 341      * and depth0. However, NPOT 3D textures must have dimensions aligned
 342      * to POT, and this is the only case when these variables differ from
 343      * pipe_texture. */
 344     unsigned width0, height0, depth0;
 345
 346     /* Buffer tiling.
 347      * Macrotiling is specified per-level because small mipmaps cannot
 348      * be macrotiled. */
 349     enum radeon_bo_layout microtile;
 350     enum radeon_bo_layout macrotile[R300_MAX_TEXTURE_LEVELS];
 351
 352     /* Offsets into the buffer. */
 353     unsigned offset_in_bytes[R300_MAX_TEXTURE_LEVELS];
 354
 355     /* Strides for each mip-level. */
 356     unsigned stride_in_bytes[R300_MAX_TEXTURE_LEVELS];
 357
 358     /* Size of one zslice or face or 2D image based on the texture target. */
 359     unsigned layer_size_in_bytes[R300_MAX_TEXTURE_LEVELS];
 360
 361     /* Total size of this texture, in bytes,
 362      * derived from the texture properties. */
 363     unsigned size_in_bytes;
 364
 365     /**
 366      * If non-zero, override the natural texture layout with
 367      * a custom stride (in bytes).
 368      *
 369      * \note Mipmapping fails for textures with a non-natural layout!
 370      *
 371      * \sa r300_texture_get_stride
 372      */
 373     unsigned stride_in_bytes_override;
 374
 375     /* Whether this texture has non-power-of-two dimensions.
 376      * It can be either a regular texture or a rectangle one. */
 377     boolean is_npot;
 378
 379     /* This flag says that hardware must use the stride for addressing
 380      * instead of the width. */
 381     boolean uses_stride_addressing;
 382
 383     /* Whether CBZB fast color clear is allowed on the miplevel. */
 384     boolean cbzb_allowed[R300_MAX_TEXTURE_LEVELS];
 385
 386     /* Zbuffer compression info for each miplevel. */
 387     boolean zcomp8x8[R300_MAX_TEXTURE_LEVELS];
 388     /* If zero, then disable Z compression/HiZ. */
 389     unsigned zmask_dwords[R300_MAX_TEXTURE_LEVELS];
 390     unsigned hiz_dwords[R300_MAX_TEXTURE_LEVELS];
 391     /* Zmask/HiZ strides for each miplevel. */
 392     unsigned zmask_stride_in_pixels[R300_MAX_TEXTURE_LEVELS];
 393     unsigned hiz_stride_in_pixels[R300_MAX_TEXTURE_LEVELS];
 394 };
 395
 396 struct r300_resource
 397 {
 398     struct u_resource b;
 399
 400     /* Winsys buffer backing this resource. */
 401     struct pb_buffer *buf;
 402     struct radeon_winsys_cs_handle *cs_buf;
 403     enum radeon_bo_domain domain;
 404
 405     /* Constant buffers and SWTCL vertex and index buffers are in user
 406      * memory. */
 407     uint8_t *malloced_buffer;
 408
 409     /* Texture description (addressing, layout, special features). */
 410     struct r300_texture_desc tex;
 411
 412     /* This is the level tiling flags were last time set for.
 413      * It's used to prevent redundant tiling-flags changes from happening.*/
 414     unsigned surface_level;
 415 };
 416
 417 struct r300_vertex_element_state {
 418     unsigned count;
 419     struct pipe_vertex_element velem[PIPE_MAX_ATTRIBS];
 420     unsigned format_size[PIPE_MAX_ATTRIBS];
 421
 422     /* The size of the vertex, in dwords. */
 423     unsigned vertex_size_dwords;
 424
 425     struct r300_vertex_stream_state vertex_stream;
 426 };
 427
 428 enum r300_hiz_func {
 429     HIZ_FUNC_NONE,
 430
 431     /* The function, when determined, is set in stone
 432      * until the next HiZ clear. */
 433
 434     /* MAX is written to the HiZ buffer.
 435      * Used for LESS, LEQUAL. */
 436     HIZ_FUNC_MAX,
 437
 438     /* MIN is written to the HiZ buffer.
 439      * Used for GREATER, GEQUAL. */
 440     HIZ_FUNC_MIN,
 441 };
 442
 443 /* For deferred fragment shader state validation. */
 444 enum r300_fs_validity_status {
 445     FRAGMENT_SHADER_VALID,      /* No need to change/validate the FS. */
 446     FRAGMENT_SHADER_MAYBE_DIRTY,/* Validate the FS if external state was changed. */
 447     FRAGMENT_SHADER_DIRTY       /* Always validate the FS (if the FS was changed) */
 448 };
 449
 450 struct r300_context {
 451     /* Parent class */
 452     struct pipe_context context;
 453
 454     /* The interface to the windowing system, etc. */
 455     struct radeon_winsys *rws;
 456     /* The command stream. */
 457     struct radeon_winsys_cs *cs;
 458     /* Screen. */
 459     struct r300_screen *screen;
 460
 461     /* Draw module. Used mostly for SW TCL. */
 462     struct draw_context* draw;
 463     /* Vertex buffer for SW TCL. */
 464     struct pipe_resource* vbo;
 465     /* Offset and size into the SW TCL VBO. */
 466     size_t draw_vbo_offset;
 467     size_t draw_vbo_size;
 468     /* Whether the VBO must not be flushed. */
 469     boolean draw_vbo_locked;
 470     boolean draw_first_emitted;
 471
 472     /* Accelerated blit support. */
 473     struct blitter_context* blitter;
 474     /* Stencil two-sided reference value fallback. */
 475     struct r300_stencilref_context *stencilref_fallback;
 476
 477     /* The KIL opcode needs the first texture unit to be enabled
 478      * on r3xx-r4xx. In order to calm down the CS checker, we bind this
 479      * dummy texture there. */
 480     struct r300_sampler_view *texkill_sampler;
 481
 482     /* When no vertex buffer is set, this one is used instead to prevent
 483      * hardlocks. */
 484     struct pipe_vertex_buffer dummy_vb;
 485
 486     /* The currently active query. */
 487     struct r300_query *query_current;
 488     /* The saved query for blitter operations. */
 489     struct r300_query *blitter_saved_query;
 490     /* Query list. */
 491     struct r300_query query_list;
 492
 493     /* Various CSO state objects. */
 494
 495     /* Each atom is emitted in the order it appears here, which can affect
 496      * performance and stability if not handled with care. */
 497     /* GPU flush. */
 498     struct r300_atom gpu_flush;
 499     /* Anti-aliasing (MSAA) state. */
 500     struct r300_atom aa_state;
 501     /* Framebuffer state. */
 502     struct r300_atom fb_state;
 503     /* HyperZ state (various SC/ZB bits). */
 504     struct r300_atom hyperz_state;
 505     /* ZTOP state. */
 506     struct r300_atom ztop_state;
 507     /* Depth, stencil, and alpha state. */
 508     struct r300_atom dsa_state;
 509     /* Blend state. */
 510     struct r300_atom blend_state;
 511     /* Blend color state. */
 512     struct r300_atom blend_color_state;
 513     /* Scissor state. */
 514     struct r300_atom scissor_state;
 515     /* Invariant state. This must be emitted to get the engine started. */
 516     struct r300_atom invariant_state;
 517     /* Viewport state. */
 518     struct r300_atom viewport_state;
 519     /* PVS flush. */
 520     struct r300_atom pvs_flush;
 521     /* VAP invariant state. */
 522     struct r300_atom vap_invariant_state;
 523     /* Vertex stream formatting state. */
 524     struct r300_atom vertex_stream_state;
 525     /* Vertex shader. */
 526     struct r300_atom vs_state;
 527     /* User clip planes. */
 528     struct r300_atom clip_state;
 529     /* RS block state + VAP (vertex shader) output mapping state. */
 530     struct r300_atom rs_block_state;
 531     /* Rasterizer state. */
 532     struct r300_atom rs_state;
 533     /* Framebuffer state (pipelined regs). */
 534     struct r300_atom fb_state_pipelined;
 535     /* Fragment shader. */
 536     struct r300_atom fs;
 537     /* Fragment shader RC_CONSTANT_STATE variables. */
 538     struct r300_atom fs_rc_constant_state;
 539     /* Fragment shader constant buffer. */
 540     struct r300_atom fs_constants;
 541     /* Vertex shader constant buffer. */
 542     struct r300_atom vs_constants;
 543     /* Texture cache invalidate. */
 544     struct r300_atom texture_cache_inval;
 545     /* Textures state. */
 546     struct r300_atom textures_state;
 547     /* HiZ clear */
 548     struct r300_atom hiz_clear;
 549     /* zmask clear */
 550     struct r300_atom zmask_clear;
 551     /* Occlusion query. */
 552     struct r300_atom query_start;
 553
 554     /* The pointers to the first and the last atom. */
 555     struct r300_atom *first_dirty, *last_dirty;
 556
 557     /* Vertex elements for Gallium. */
 558     struct r300_vertex_element_state *velems;
 559
 560     /* Vertex info for Draw. */
 561     struct vertex_info vertex_info;
 562
 563     struct pipe_stencil_ref stencil_ref;
 564     struct pipe_viewport_state viewport;
 565
 566     /* Stream locations for SWTCL. */
 567     int stream_loc_notcl[16];
 568
 569     /* Flag indicating whether or not the HW is dirty. */
 570     uint32_t dirty_hw;
 571     /* Whether polygon offset is enabled. */
 572     boolean polygon_offset_enabled;
 573     /* Z buffer bit depth. */
 574     uint32_t zbuffer_bpp;
 575     /* Whether rendering is conditional and should be skipped. */
 576     boolean skip_rendering;
 577     /* The flag above saved by blitter. */
 578     unsigned char blitter_saved_skip_rendering;
 579     /* Point sprites texcoord index,  1 bit per texcoord */
 580     int sprite_coord_enable;
 581     /* Whether two-sided color selection is enabled (AKA light_twoside). */
 582     boolean two_sided_color;
 583     /* Whether fast color clear is enabled. */
 584     boolean cbzb_clear;
 585     /* Whether fragment shader needs to be validated. */
 586     enum r300_fs_validity_status fs_status;
 587     /* Framebuffer multi-write. */
 588     boolean fb_multiwrite;
 589
 590     void *dsa_decompress_zmask;
 591
 592     struct pipe_index_buffer index_buffer;
 593     struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 594     unsigned nr_vertex_buffers;
 595     struct u_upload_mgr *uploader;
 596
 597     struct util_slab_mempool pool_transfers;
 598
 599     /* Stat counter. */
 600     uint64_t flush_counter;
 601
 602     /* const tracking for VS */
 603     int vs_const_base;
 604
 605     /* Vertex array state info */
 606     boolean vertex_arrays_dirty;
 607     boolean vertex_arrays_indexed;
 608     int vertex_arrays_offset;
 609     int vertex_arrays_instance_id;
 610     boolean instancing_enabled;
 611
 612     /* Hyper-Z stats. */
 613     boolean hyperz_enabled;     /* Whether it owns Hyper-Z access. */
 614     int64_t hyperz_time_of_last_flush; /* Time of the last flush with Z clear. */
 615     unsigned num_z_clears;      /* Since the last flush. */
 616
 617     /* ZMask state. */
 618     boolean zmask_in_use;       /* Whether ZMASK is enabled. */
 619     boolean zmask_decompress;   /* Whether ZMASK is being decompressed. */
 620     struct pipe_surface *locked_zbuffer; /* Unbound zbuffer which still has data in ZMASK. */
 621
 622     /* HiZ state. */
 623     boolean hiz_in_use;         /* Whether HIZ is enabled. */
 624     enum r300_hiz_func hiz_func; /* HiZ function. Can be either MIN or MAX. */
 625     uint32_t hiz_clear_value;   /* HiZ clear value. */
 626
 627     /* Compiler state. */
 628     struct rc_regalloc_state fs_regalloc_state; /* Register allocator info for
 629                                                  * fragment shaders. */
 630 };
 631
 632 #define foreach_atom(r300, atom) \
 633     for (atom = &r300->gpu_flush; atom != (&r300->query_start)+1; atom++)
 634
 635 #define foreach_dirty_atom(r300, atom) \
 636     for (atom = r300->first_dirty; atom != r300->last_dirty; atom++)
 637
 638 /* Convenience cast wrappers. */
 639 static INLINE struct r300_query* r300_query(struct pipe_query* q)
 640 {
 641     return (struct r300_query*)q;
 642 }
 643
 644 static INLINE struct r300_surface* r300_surface(struct pipe_surface* surf)
 645 {
 646     return (struct r300_surface*)surf;
 647 }
 648
 649 static INLINE struct r300_resource* r300_resource(struct pipe_resource* tex)
 650 {
 651     return (struct r300_resource*)tex;
 652 }
 653
 654 static INLINE struct r300_context* r300_context(struct pipe_context* context)
 655 {
 656     return (struct r300_context*)context;
 657 }
 658
 659 static INLINE struct r300_fragment_shader *r300_fs(struct r300_context *r300)
 660 {
 661     return (struct r300_fragment_shader*)r300->fs.state;
 662 }
 663
 664 static INLINE void r300_mark_atom_dirty(struct r300_context *r300,
 665                                         struct r300_atom *atom)
 666 {
 667     atom->dirty = TRUE;
 668
 669     if (!r300->first_dirty) {
 670         r300->first_dirty = atom;
 671         r300->last_dirty = atom+1;
 672     } else {
 673         if (atom < r300->first_dirty)
 674             r300->first_dirty = atom;
 675         else if (atom+1 > r300->last_dirty)
 676             r300->last_dirty = atom+1;
 677     }
 678 }
 679
 680 struct pipe_context* r300_create_context(struct pipe_screen* screen,
 681                                          void *priv);
 682
 683 /* Context initialization. */
 684 struct draw_stage* r300_draw_stage(struct r300_context* r300);
 685 void r300_init_blit_functions(struct r300_context *r300);
 686 void r300_init_flush_functions(struct r300_context* r300);
 687 void r300_init_query_functions(struct r300_context* r300);
 688 void r300_init_render_functions(struct r300_context *r300);
 689 void r300_init_state_functions(struct r300_context* r300);
 690 void r300_init_resource_functions(struct r300_context* r300);
 691
 692 /* r300_blit.c */
 693 void r300_decompress_zmask(struct r300_context *r300);
 694 void r300_decompress_zmask_locked_unsafe(struct r300_context *r300);
 695 void r300_decompress_zmask_locked(struct r300_context *r300);
 696 bool r300_is_blit_supported(enum pipe_format format);
 697
 698 /* r300_flush.c */
 699 void r300_flush(struct pipe_context *pipe,
 700                 unsigned flags,
 701                 struct pipe_fence_handle **fence);
 702
 703 /* r300_hyperz.c */
 704 void r300_update_hyperz_state(struct r300_context* r300);
 705
 706 /* r300_query.c */
 707 void r300_resume_query(struct r300_context *r300,
 708                        struct r300_query *query);
 709 void r300_stop_query(struct r300_context *r300);
 710
 711 /* r300_render_translate.c */
 712 void r300_translate_index_buffer(struct r300_context *r300,
 713                                  struct pipe_index_buffer *ib,
 714                                  struct pipe_resource **out_index_buffer,
 715                                  unsigned *index_size, unsigned index_offset,
 716                                  unsigned *start, unsigned count);
 717
 718 /* r300_render_stencilref.c */
 719 void r300_plug_in_stencil_ref_fallback(struct r300_context *r300);
 720
 721 /* r300_render.c */
 722 void r300_draw_flush_vbuf(struct r300_context *r300);
 723 void r500_emit_index_bias(struct r300_context *r300, int index_bias);
 724 void r300_blitter_draw_rectangle(struct blitter_context *blitter,
 725                                  unsigned x1, unsigned y1,
 726                                  unsigned x2, unsigned y2,
 727                                  float depth,
 728                                  enum blitter_attrib_type type,
 729                                  const union pipe_color_union *attrib);
 730
 731 /* r300_state.c */
 732 enum r300_fb_state_change {
 733     R300_CHANGED_FB_STATE = 0,
 734     R300_CHANGED_HYPERZ_FLAG,
 735     R300_CHANGED_MULTIWRITE
 736 };
 737
 738 void r300_mark_fb_state_dirty(struct r300_context *r300,
 739                               enum r300_fb_state_change change);
 740 void r300_mark_fs_code_dirty(struct r300_context *r300);
 741
 742 struct pipe_sampler_view *
 743 r300_create_sampler_view_custom(struct pipe_context *pipe,
 744                          struct pipe_resource *texture,
 745                          const struct pipe_sampler_view *templ,
 746                          unsigned width0_override,
 747                          unsigned height0_override);
 748
 749 /* r300_state_derived.c */
 750 void r300_update_derived_state(struct r300_context* r300);
 751
 752 /* r300_debug.c */
 753 void r500_dump_rs_block(struct r300_rs_block *rs);
 754
 755
 756 static INLINE boolean CTX_DBG_ON(struct r300_context * ctx, unsigned flags)
 757 {
 758     return SCREEN_DBG_ON(ctx->screen, flags);
 759 }
 760
 761 static INLINE void CTX_DBG(struct r300_context * ctx, unsigned flags,
 762                        const char * fmt, ...)
 763 {
 764     if (CTX_DBG_ON(ctx, flags)) {
 765         va_list va;
 766         va_start(va, fmt);
 767         vfprintf(stderr, fmt, va);
 768         va_end(va);
 769     }
 770 }
 771
 772 #define DBG_ON  CTX_DBG_ON
 773 #define DBG     CTX_DBG
 774
 775 #endif /* R300_CONTEXT_H */