r300g: separate the hyperz state and pipelined FB regs out of the FB state
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300,
39 unsigned size, void* state)
40 {
41 struct r300_blend_state* blend = (struct r300_blend_state*)state;
42 struct pipe_framebuffer_state* fb =
43 (struct pipe_framebuffer_state*)r300->fb_state.state;
44 CS_LOCALS(r300);
45
46 if (fb->nr_cbufs) {
47 WRITE_CS_TABLE(blend->cb, size);
48 } else {
49 WRITE_CS_TABLE(blend->cb_no_readwrite, size);
50 }
51 }
52
53 void r300_emit_blend_color_state(struct r300_context* r300,
54 unsigned size, void* state)
55 {
56 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
57 CS_LOCALS(r300);
58
59 WRITE_CS_TABLE(bc->cb, size);
60 }
61
62 void r300_emit_clip_state(struct r300_context* r300,
63 unsigned size, void* state)
64 {
65 struct r300_clip_state* clip = (struct r300_clip_state*)state;
66 CS_LOCALS(r300);
67
68 WRITE_CS_TABLE(clip->cb, size);
69 }
70
71 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
72 {
73 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
74 struct pipe_framebuffer_state* fb =
75 (struct pipe_framebuffer_state*)r300->fb_state.state;
76 CS_LOCALS(r300);
77
78 if (fb->zsbuf) {
79 WRITE_CS_TABLE(&dsa->cb_begin, size);
80 } else {
81 WRITE_CS_TABLE(dsa->cb_no_readwrite, size);
82 }
83 }
84
85 static const float * get_rc_constant_state(
86 struct r300_context * r300,
87 struct rc_constant * constant)
88 {
89 struct r300_textures_state* texstate = r300->textures_state.state;
90 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
91 struct pipe_resource *tex;
92
93 assert(constant->Type == RC_CONSTANT_STATE);
94
95 switch (constant->u.State[0]) {
96 /* Factor for converting rectangle coords to
97 * normalized coords. Should only show up on non-r500. */
98 case RC_STATE_R300_TEXRECT_FACTOR:
99 tex = texstate->sampler_views[constant->u.State[1]]->base.texture;
100 vec[0] = 1.0 / tex->width0;
101 vec[1] = 1.0 / tex->height0;
102 break;
103
104 case RC_STATE_R300_VIEWPORT_SCALE:
105 vec[0] = r300->viewport.scale[0];
106 vec[1] = r300->viewport.scale[1];
107 vec[2] = r300->viewport.scale[2];
108 break;
109
110 case RC_STATE_R300_VIEWPORT_OFFSET:
111 vec[0] = r300->viewport.translate[0];
112 vec[1] = r300->viewport.translate[1];
113 vec[2] = r300->viewport.translate[2];
114 break;
115
116 default:
117 fprintf(stderr, "r300: Implementation error: "
118 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
119 }
120
121 /* This should either be (0, 0, 0, 1), which should be a relatively safe
122 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
123 * state factors. */
124 return vec;
125 }
126
127 /* Convert a normal single-precision float into the 7.16 format
128 * used by the R300 fragment shader.
129 */
130 uint32_t pack_float24(float f)
131 {
132 union {
133 float fl;
134 uint32_t u;
135 } u;
136 float mantissa;
137 int exponent;
138 uint32_t float24 = 0;
139
140 if (f == 0.0)
141 return 0;
142
143 u.fl = f;
144
145 mantissa = frexpf(f, &exponent);
146
147 /* Handle -ve */
148 if (mantissa < 0) {
149 float24 |= (1 << 23);
150 mantissa = mantissa * -1.0;
151 }
152 /* Handle exponent, bias of 63 */
153 exponent += 62;
154 float24 |= (exponent << 16);
155 /* Kill 7 LSB of mantissa */
156 float24 |= (u.u & 0x7FFFFF) >> 7;
157
158 return float24;
159 }
160
161 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
162 {
163 struct r300_fragment_shader *fs = r300_fs(r300);
164 CS_LOCALS(r300);
165
166 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
167 }
168
169 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
170 {
171 struct r300_fragment_shader *fs = r300_fs(r300);
172 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
173 unsigned count = fs->shader->externals_count * 4;
174 CS_LOCALS(r300);
175
176 if (count == 0)
177 return;
178
179 BEGIN_CS(size);
180 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count);
181 OUT_CS_TABLE(buf->constants, count);
182 END_CS;
183 }
184
185 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
186 {
187 struct r300_fragment_shader *fs = r300_fs(r300);
188 struct rc_constant_list *constants = &fs->shader->code.constants;
189 unsigned i;
190 unsigned count = fs->shader->rc_state_count;
191 unsigned first = fs->shader->externals_count;
192 unsigned end = constants->Count;
193 uint32_t cdata[4];
194 unsigned j;
195 CS_LOCALS(r300);
196
197 if (count == 0)
198 return;
199
200 BEGIN_CS(size);
201 for(i = first; i < end; ++i) {
202 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
203 const float *data =
204 get_rc_constant_state(r300, &constants->Constants[i]);
205
206 for (j = 0; j < 4; j++)
207 cdata[j] = pack_float24(data[j]);
208
209 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
210 OUT_CS_TABLE(cdata, 4);
211 }
212 }
213 END_CS;
214 }
215
216 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
217 {
218 struct r300_fragment_shader *fs = r300_fs(r300);
219 CS_LOCALS(r300);
220
221 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
222 }
223
224 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
225 {
226 struct r300_fragment_shader *fs = r300_fs(r300);
227 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
228 unsigned count = fs->shader->externals_count * 4;
229 CS_LOCALS(r300);
230
231 if (count == 0)
232 return;
233
234 BEGIN_CS(size);
235 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
236 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count);
237 OUT_CS_TABLE(buf->constants, count);
238 END_CS;
239 }
240
241 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
242 {
243 struct r300_fragment_shader *fs = r300_fs(r300);
244 struct rc_constant_list *constants = &fs->shader->code.constants;
245 unsigned i;
246 unsigned count = fs->shader->rc_state_count;
247 unsigned first = fs->shader->externals_count;
248 unsigned end = constants->Count;
249 CS_LOCALS(r300);
250
251 if (count == 0)
252 return;
253
254 BEGIN_CS(size);
255 for(i = first; i < end; ++i) {
256 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
257 const float *data =
258 get_rc_constant_state(r300, &constants->Constants[i]);
259
260 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
261 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
262 (i & R500_GA_US_VECTOR_INDEX_MASK));
263 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
264 OUT_CS_TABLE(data, 4);
265 }
266 }
267 END_CS;
268 }
269
270 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
271 {
272 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
273 struct pipe_framebuffer_state* fb =
274 (struct pipe_framebuffer_state*)r300->fb_state.state;
275 CS_LOCALS(r300);
276
277 BEGIN_CS(size);
278
279 /* Set up scissors.
280 * By writing to the SC registers, SC & US assert idle. */
281 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
282 if (r300->screen->caps.is_r500) {
283 OUT_CS(0);
284 OUT_CS(((fb->width - 1) << R300_SCISSORS_X_SHIFT) |
285 ((fb->height - 1) << R300_SCISSORS_Y_SHIFT));
286 } else {
287 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
288 (1440 << R300_SCISSORS_Y_SHIFT));
289 OUT_CS(((fb->width + 1440-1) << R300_SCISSORS_X_SHIFT) |
290 ((fb->height + 1440-1) << R300_SCISSORS_Y_SHIFT));
291 }
292
293 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
294 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
295 END_CS;
296 }
297
298 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
299 {
300 struct r300_aa_state *aa = (struct r300_aa_state*)state;
301 CS_LOCALS(r300);
302
303 BEGIN_CS(size);
304 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
305
306 if (aa->dest) {
307 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 1);
308 OUT_CS_RELOC(aa->dest->buffer, aa->dest->offset, 0, aa->dest->domain, 0);
309
310 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_PITCH, 1);
311 OUT_CS_RELOC(aa->dest->buffer, aa->dest->pitch, 0, aa->dest->domain, 0);
312 }
313
314 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, aa->aaresolve_ctl);
315 END_CS;
316 }
317
318 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
319 {
320 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
321 struct r300_surface* surf;
322 unsigned i;
323 CS_LOCALS(r300);
324
325 BEGIN_CS(size);
326
327 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
328 * what we usually want. */
329 if (r300->screen->caps.is_r500) {
330 OUT_CS_REG(R300_RB3D_CCTL,
331 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
332 } else {
333 OUT_CS_REG(R300_RB3D_CCTL, 0);
334 }
335
336 /* Set up colorbuffers. */
337 for (i = 0; i < fb->nr_cbufs; i++) {
338 surf = r300_surface(fb->cbufs[i]);
339
340 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
341 OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain, 0);
342
343 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
344 OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain, 0);
345 }
346
347 /* Set up a zbuffer. */
348 if (fb->zsbuf) {
349 surf = r300_surface(fb->zsbuf);
350
351 OUT_CS_REG(R300_ZB_FORMAT, surf->format);
352
353 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
354 OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain, 0);
355
356 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
357 OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain, 0);
358
359 /* HiZ RAM. */
360 if (r300->screen->caps.has_hiz) {
361 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
362 OUT_CS_REG(R300_ZB_HIZ_PITCH, 0);
363 }
364
365 /* Z Mask RAM. (compressed zbuffer) */
366 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
367 OUT_CS_REG(R300_ZB_ZMASK_PITCH, 0);
368 }
369
370 END_CS;
371 }
372
373 void r300_emit_hyperz_state(struct r300_context *r300,
374 unsigned size, void *state)
375 {
376 CS_LOCALS(r300);
377 WRITE_CS_TABLE(state, size);
378 }
379
380 void r300_emit_fb_state_pipelined(struct r300_context *r300,
381 unsigned size, void *state)
382 {
383 struct pipe_framebuffer_state* fb =
384 (struct pipe_framebuffer_state*)r300->fb_state.state;
385 unsigned i;
386 CS_LOCALS(r300);
387
388 BEGIN_CS(size);
389
390 /* Colorbuffer format in the US block.
391 * (must be written after unpipelined regs) */
392 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
393 for (i = 0; i < fb->nr_cbufs; i++) {
394 OUT_CS(r300_surface(fb->cbufs[i])->format);
395 }
396 for (; i < 4; i++) {
397 OUT_CS(R300_US_OUT_FMT_UNUSED);
398 }
399
400 /* Multisampling. Depends on framebuffer sample count.
401 * These are pipelined regs and as such cannot be moved
402 * to the AA state. */
403 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
404 unsigned mspos0 = 0x66666666;
405 unsigned mspos1 = 0x6666666;
406
407 if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) {
408 /* Subsample placement. These may not be optimal. */
409 switch (fb->cbufs[0]->texture->nr_samples) {
410 case 2:
411 mspos0 = 0x33996633;
412 mspos1 = 0x6666663;
413 break;
414 case 3:
415 mspos0 = 0x33936933;
416 mspos1 = 0x6666663;
417 break;
418 case 4:
419 mspos0 = 0x33939933;
420 mspos1 = 0x3966663;
421 break;
422 case 6:
423 mspos0 = 0x22a2aa22;
424 mspos1 = 0x2a65672;
425 break;
426 default:
427 debug_printf("r300: Bad number of multisamples!\n");
428 }
429 }
430
431 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
432 OUT_CS(mspos0);
433 OUT_CS(mspos1);
434 }
435 END_CS;
436 }
437
438 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
439 {
440 struct r300_query *query = r300->query_current;
441 CS_LOCALS(r300);
442
443 if (!query)
444 return;
445
446 BEGIN_CS(size);
447 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
448 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
449 } else {
450 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
451 }
452 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
453 END_CS;
454 query->begin_emitted = TRUE;
455 query->flushed = FALSE;
456 }
457
458 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
459 struct r300_query *query)
460 {
461 struct r300_capabilities* caps = &r300->screen->caps;
462 struct r300_winsys_buffer *buf = r300->query_current->buffer;
463 CS_LOCALS(r300);
464
465 assert(caps->num_frag_pipes);
466
467 BEGIN_CS(6 * caps->num_frag_pipes + 2);
468 /* I'm not so sure I like this switch, but it's hard to be elegant
469 * when there's so many special cases...
470 *
471 * So here's the basic idea. For each pipe, enable writes to it only,
472 * then put out the relocation for ZPASS_ADDR, taking into account a
473 * 4-byte offset for each pipe. RV380 and older are special; they have
474 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
475 * so there's a chipset cap for that. */
476 switch (caps->num_frag_pipes) {
477 case 4:
478 /* pipe 3 only */
479 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
480 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
481 OUT_CS_RELOC(buf, (query->num_results + 3) * 4,
482 0, query->domain, 0);
483 case 3:
484 /* pipe 2 only */
485 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
486 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
487 OUT_CS_RELOC(buf, (query->num_results + 2) * 4,
488 0, query->domain, 0);
489 case 2:
490 /* pipe 1 only */
491 /* As mentioned above, accomodate RV380 and older. */
492 OUT_CS_REG(R300_SU_REG_DEST,
493 1 << (caps->high_second_pipe ? 3 : 1));
494 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
495 OUT_CS_RELOC(buf, (query->num_results + 1) * 4,
496 0, query->domain, 0);
497 case 1:
498 /* pipe 0 only */
499 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
500 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
501 OUT_CS_RELOC(buf, (query->num_results + 0) * 4,
502 0, query->domain, 0);
503 break;
504 default:
505 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
506 " pixel pipes!\n", caps->num_frag_pipes);
507 abort();
508 }
509
510 /* And, finally, reset it to normal... */
511 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
512 END_CS;
513 }
514
515 static void rv530_emit_query_end_single_z(struct r300_context *r300,
516 struct r300_query *query)
517 {
518 struct r300_winsys_buffer *buf = r300->query_current->buffer;
519 CS_LOCALS(r300);
520
521 BEGIN_CS(8);
522 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
523 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
524 OUT_CS_RELOC(buf, query->num_results * 4, 0, query->domain, 0);
525 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
526 END_CS;
527 }
528
529 static void rv530_emit_query_end_double_z(struct r300_context *r300,
530 struct r300_query *query)
531 {
532 struct r300_winsys_buffer *buf = r300->query_current->buffer;
533 CS_LOCALS(r300);
534
535 BEGIN_CS(14);
536 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
537 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
538 OUT_CS_RELOC(buf, (query->num_results + 0) * 4, 0, query->domain, 0);
539 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
540 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
541 OUT_CS_RELOC(buf, (query->num_results + 1) * 4, 0, query->domain, 0);
542 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
543 END_CS;
544 }
545
546 void r300_emit_query_end(struct r300_context* r300)
547 {
548 struct r300_capabilities *caps = &r300->screen->caps;
549 struct r300_query *query = r300->query_current;
550
551 if (!query)
552 return;
553
554 if (query->begin_emitted == FALSE)
555 return;
556
557 if (caps->family == CHIP_FAMILY_RV530) {
558 if (caps->num_z_pipes == 2)
559 rv530_emit_query_end_double_z(r300, query);
560 else
561 rv530_emit_query_end_single_z(r300, query);
562 } else
563 r300_emit_query_end_frag_pipes(r300, query);
564
565 query->begin_emitted = FALSE;
566 query->num_results += query->num_pipes;
567
568 /* XXX grab all the results and reset the counter. */
569 if (query->num_results >= query->buffer_size / 4 - 4) {
570 query->num_results = (query->buffer_size / 4) / 2;
571 fprintf(stderr, "r300: Rewinding OQBO...\n");
572 }
573 }
574
575 void r300_emit_invariant_state(struct r300_context *r300,
576 unsigned size, void *state)
577 {
578 CS_LOCALS(r300);
579 WRITE_CS_TABLE(state, size);
580 }
581
582 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
583 {
584 struct r300_rs_state* rs = state;
585 CS_LOCALS(r300);
586
587 BEGIN_CS(size);
588 OUT_CS_TABLE(rs->cb_main, 25);
589 if (rs->polygon_offset_enable) {
590 if (r300->zbuffer_bpp == 16) {
591 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
592 } else {
593 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
594 }
595 }
596 END_CS;
597 }
598
599 void r300_emit_rs_block_state(struct r300_context* r300,
600 unsigned size, void* state)
601 {
602 struct r300_rs_block* rs = (struct r300_rs_block*)state;
603 unsigned i;
604 /* It's the same for both INST and IP tables */
605 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
606 CS_LOCALS(r300);
607
608 if (SCREEN_DBG_ON(r300->screen, DBG_DRAW)) {
609 r500_dump_rs_block(rs);
610
611 fprintf(stderr, "r300: RS emit:\n");
612
613 for (i = 0; i < count; i++)
614 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]);
615
616 for (i = 0; i < count; i++)
617 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]);
618
619 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n",
620 rs->count, rs->inst_count);
621 }
622
623 BEGIN_CS(size);
624 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
625 OUT_CS(rs->vap_vtx_state_cntl);
626 OUT_CS(rs->vap_vsm_vtx_assm);
627 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
628 OUT_CS(rs->vap_out_vtx_fmt[0]);
629 OUT_CS(rs->vap_out_vtx_fmt[1]);
630
631 if (r300->screen->caps.is_r500) {
632 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
633 } else {
634 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
635 }
636 OUT_CS_TABLE(rs->ip, count);
637
638 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
639 OUT_CS(rs->count);
640 OUT_CS(rs->inst_count);
641
642 if (r300->screen->caps.is_r500) {
643 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
644 } else {
645 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
646 }
647 OUT_CS_TABLE(rs->inst, count);
648 END_CS;
649 }
650
651 void r300_emit_scissor_state(struct r300_context* r300,
652 unsigned size, void* state)
653 {
654 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
655 CS_LOCALS(r300);
656
657 BEGIN_CS(size);
658 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
659 if (r300->screen->caps.is_r500) {
660 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
661 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
662 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
663 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
664 } else {
665 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
666 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
667 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
668 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
669 }
670 END_CS;
671 }
672
673 void r300_emit_textures_state(struct r300_context *r300,
674 unsigned size, void *state)
675 {
676 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
677 struct r300_texture_sampler_state *texstate;
678 struct r300_texture *tex;
679 unsigned i;
680 CS_LOCALS(r300);
681
682 BEGIN_CS(size);
683 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
684
685 for (i = 0; i < allstate->count; i++) {
686 if ((1 << i) & allstate->tx_enable) {
687 texstate = &allstate->regs[i];
688 tex = r300_texture(allstate->sampler_views[i]->base.texture);
689
690 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
691 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
692 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
693 texstate->border_color);
694
695 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
696 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
697 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
698
699 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
700 OUT_CS_TEX_RELOC(tex, texstate->format.tile_config, tex->domain,
701 0, 0);
702 }
703 }
704 END_CS;
705 }
706
707 void r300_emit_aos(struct r300_context* r300, int offset, boolean indexed)
708 {
709 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
710 struct pipe_vertex_element *velem = r300->velems->velem;
711 struct r300_buffer *buf;
712 int i;
713 unsigned *hw_format_size = r300->velems->hw_format_size;
714 unsigned size1, size2, aos_count = r300->velems->count;
715 unsigned packet_size = (aos_count * 3 + 1) / 2;
716 CS_LOCALS(r300);
717
718 BEGIN_CS(2 + packet_size + aos_count * 2);
719 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
720 OUT_CS(aos_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
721
722 for (i = 0; i < aos_count - 1; i += 2) {
723 vb1 = &vbuf[velem[i].vertex_buffer_index];
724 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
725 size1 = hw_format_size[i];
726 size2 = hw_format_size[i+1];
727
728 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
729 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
730 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
731 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
732 }
733
734 if (aos_count & 1) {
735 vb1 = &vbuf[velem[i].vertex_buffer_index];
736 size1 = hw_format_size[i];
737
738 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
739 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
740 }
741
742 for (i = 0; i < aos_count; i++) {
743 buf = r300_buffer(vbuf[velem[i].vertex_buffer_index].buffer);
744 OUT_CS_BUF_RELOC_NO_OFFSET(&buf->b.b, buf->domain, 0, 0);
745 }
746 END_CS;
747 }
748
749 void r300_emit_aos_swtcl(struct r300_context *r300, boolean indexed)
750 {
751 CS_LOCALS(r300);
752
753 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
754 "vertex size %d\n", r300->vbo,
755 r300->vertex_info.size);
756 /* Set the pointer to our vertex buffer. The emitted values are this:
757 * PACKET3 [3D_LOAD_VBPNTR]
758 * COUNT [1]
759 * FORMAT [size | stride << 8]
760 * OFFSET [offset into BO]
761 * VBPNTR [relocated BO]
762 */
763 BEGIN_CS(7);
764 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
765 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
766 OUT_CS(r300->vertex_info.size |
767 (r300->vertex_info.size << 8));
768 OUT_CS(r300->vbo_offset);
769 OUT_CS_BUF_RELOC(r300->vbo, 0, r300_buffer(r300->vbo)->domain, 0, 0);
770 END_CS;
771 }
772
773 void r300_emit_vertex_stream_state(struct r300_context* r300,
774 unsigned size, void* state)
775 {
776 struct r300_vertex_stream_state *streams =
777 (struct r300_vertex_stream_state*)state;
778 unsigned i;
779 CS_LOCALS(r300);
780
781 if (DBG_ON(r300, DBG_DRAW)) {
782 fprintf(stderr, "r300: PSC emit:\n");
783
784 for (i = 0; i < streams->count; i++) {
785 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i,
786 streams->vap_prog_stream_cntl[i]);
787 }
788
789 for (i = 0; i < streams->count; i++) {
790 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
791 streams->vap_prog_stream_cntl_ext[i]);
792 }
793 }
794
795 BEGIN_CS(size);
796 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
797 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
798 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
799 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
800 END_CS;
801 }
802
803 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
804 {
805 CS_LOCALS(r300);
806
807 BEGIN_CS(size);
808 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
809 END_CS;
810 }
811
812 void r300_emit_vap_invariant_state(struct r300_context *r300,
813 unsigned size, void *state)
814 {
815 CS_LOCALS(r300);
816 WRITE_CS_TABLE(state, size);
817 }
818
819 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
820 {
821 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
822 struct r300_vertex_program_code* code = &vs->code;
823 struct r300_screen* r300screen = r300->screen;
824 unsigned instruction_count = code->length / 4;
825 unsigned i;
826
827 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
828 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
829 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
830 unsigned temp_count = MAX2(code->num_temporaries, 1);
831
832 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
833 vtx_mem_size / output_count, 10);
834 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
835
836 unsigned imm_first = vs->externals_count;
837 unsigned imm_end = vs->code.constants.Count;
838 unsigned imm_count = vs->immediates_count;
839
840 CS_LOCALS(r300);
841
842 BEGIN_CS(size);
843
844 /* R300_VAP_PVS_CODE_CNTL_0
845 * R300_VAP_PVS_CONST_CNTL
846 * R300_VAP_PVS_CODE_CNTL_1
847 * See the r5xx docs for instructions on how to use these. */
848 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
849 OUT_CS(R300_PVS_FIRST_INST(0) |
850 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
851 R300_PVS_LAST_INST(instruction_count - 1));
852 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
853 OUT_CS(instruction_count - 1);
854
855 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
856 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
857 OUT_CS_TABLE(code->body.d, code->length);
858
859 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
860 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
861 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
862 R300_PVS_VF_MAX_VTX_NUM(12) |
863 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
864
865 /* Emit immediates. */
866 if (imm_count) {
867 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
868 (r300->screen->caps.is_r500 ?
869 R500_PVS_CONST_START : R300_PVS_CONST_START) +
870 imm_first);
871 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
872 for (i = imm_first; i < imm_end; i++) {
873 const float *data = vs->code.constants.Constants[i].u.Immediate;
874 OUT_CS_TABLE(data, 4);
875 }
876 }
877 END_CS;
878 }
879
880 void r300_emit_vs_constants(struct r300_context* r300,
881 unsigned size, void *state)
882 {
883 unsigned count =
884 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
885 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
886 CS_LOCALS(r300);
887
888 if (!count)
889 return;
890
891 BEGIN_CS(size);
892 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
893 (r300->screen->caps.is_r500 ?
894 R500_PVS_CONST_START : R300_PVS_CONST_START));
895 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
896 OUT_CS_TABLE(buf->constants, count * 4);
897 END_CS;
898 }
899
900 void r300_emit_viewport_state(struct r300_context* r300,
901 unsigned size, void* state)
902 {
903 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
904 CS_LOCALS(r300);
905
906 BEGIN_CS(size);
907 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
908 OUT_CS_TABLE(&viewport->xscale, 6);
909 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
910 END_CS;
911 }
912
913 void r300_emit_ztop_state(struct r300_context* r300,
914 unsigned size, void* state)
915 {
916 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
917 CS_LOCALS(r300);
918
919 BEGIN_CS(size);
920 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
921 END_CS;
922 }
923
924 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
925 {
926 CS_LOCALS(r300);
927
928 BEGIN_CS(size);
929 OUT_CS_REG(R300_TX_INVALTAGS, 0);
930 END_CS;
931 }
932
933 void r300_emit_buffer_validate(struct r300_context *r300,
934 boolean do_validate_vertex_buffers,
935 struct pipe_resource *index_buffer)
936 {
937 struct pipe_framebuffer_state* fb =
938 (struct pipe_framebuffer_state*)r300->fb_state.state;
939 struct r300_textures_state *texstate =
940 (struct r300_textures_state*)r300->textures_state.state;
941 struct r300_texture* tex;
942 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
943 struct pipe_vertex_element *velem = r300->velems->velem;
944 struct pipe_resource *pbuf;
945 unsigned i;
946 boolean invalid = FALSE;
947
948 /* upload buffers first */
949 if (r300->screen->caps.has_tcl && r300->any_user_vbs) {
950 r300_upload_user_buffers(r300);
951 r300->any_user_vbs = false;
952 }
953
954 /* Clean out BOs. */
955 r300->rws->reset_bos(r300->rws);
956
957 validate:
958 /* Color buffers... */
959 for (i = 0; i < fb->nr_cbufs; i++) {
960 tex = r300_texture(fb->cbufs[i]->texture);
961 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
962 if (!r300_add_texture(r300->rws, tex, 0, tex->domain)) {
963 r300->context.flush(&r300->context, 0, NULL);
964 goto validate;
965 }
966 }
967 /* ...depth buffer... */
968 if (fb->zsbuf) {
969 tex = r300_texture(fb->zsbuf->texture);
970 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
971 if (!r300_add_texture(r300->rws, tex,
972 0, tex->domain)) {
973 r300->context.flush(&r300->context, 0, NULL);
974 goto validate;
975 }
976 }
977 /* ...textures... */
978 for (i = 0; i < texstate->count; i++) {
979 if (!(texstate->tx_enable & (1 << i))) {
980 continue;
981 }
982
983 tex = r300_texture(texstate->sampler_views[i]->base.texture);
984 if (!r300_add_texture(r300->rws, tex, tex->domain, 0)) {
985 r300->context.flush(&r300->context, 0, NULL);
986 goto validate;
987 }
988 }
989 /* ...occlusion query buffer... */
990 if (r300->query_current) {
991 if (!r300->rws->add_buffer(r300->rws, r300->query_current->buffer,
992 0, r300->query_current->domain)) {
993 r300->context.flush(&r300->context, 0, NULL);
994 goto validate;
995 }
996 }
997 /* ...vertex buffer for SWTCL path... */
998 if (r300->vbo) {
999 if (!r300_add_buffer(r300->rws, r300->vbo,
1000 r300_buffer(r300->vbo)->domain, 0)) {
1001 r300->context.flush(&r300->context, 0, NULL);
1002 goto validate;
1003 }
1004 }
1005 /* ...vertex buffers for HWTCL path... */
1006 if (do_validate_vertex_buffers) {
1007 for (i = 0; i < r300->velems->count; i++) {
1008 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1009
1010 if (!r300_add_buffer(r300->rws, pbuf,
1011 r300_buffer(pbuf)->domain, 0)) {
1012 r300->context.flush(&r300->context, 0, NULL);
1013 goto validate;
1014 }
1015 }
1016 }
1017 /* ...and index buffer for HWTCL path. */
1018 if (index_buffer) {
1019 if (!r300_add_buffer(r300->rws, index_buffer,
1020 r300_buffer(index_buffer)->domain, 0)) {
1021 r300->context.flush(&r300->context, 0, NULL);
1022 goto validate;
1023 }
1024 }
1025 if (!r300->rws->validate(r300->rws)) {
1026 r300->context.flush(&r300->context, 0, NULL);
1027 if (invalid) {
1028 /* Well, hell. */
1029 fprintf(stderr, "r300: Stuck in validation loop, gonna quit now.\n");
1030 abort();
1031 }
1032 invalid = TRUE;
1033 goto validate;
1034 }
1035 }
1036
1037 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1038 {
1039 struct r300_atom* atom;
1040 unsigned dwords = 0;
1041
1042 foreach(atom, &r300->atom_list) {
1043 if (atom->dirty) {
1044 dwords += atom->size;
1045 }
1046 }
1047
1048 /* let's reserve some more, just in case */
1049 dwords += 32;
1050
1051 return dwords;
1052 }
1053
1054 /* Emit all dirty state. */
1055 void r300_emit_dirty_state(struct r300_context* r300)
1056 {
1057 struct r300_atom* atom;
1058
1059 foreach(atom, &r300->atom_list) {
1060 if (atom->dirty) {
1061 atom->emit(r300, atom->size, atom->state);
1062 if (SCREEN_DBG_ON(r300->screen, DBG_STATS)) {
1063 atom->counter++;
1064 }
1065 atom->dirty = FALSE;
1066 }
1067 }
1068
1069 r300->dirty_hw++;
1070 }