2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29 #include "util/u_simple_list.h"
31 #include "r300_context.h"
34 #include "r300_emit.h"
36 #include "r300_screen.h"
37 #include "r300_screen_buffer.h"
40 void r300_emit_blend_state(struct r300_context
* r300
,
41 unsigned size
, void* state
)
43 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
44 struct pipe_framebuffer_state
* fb
=
45 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
49 WRITE_CS_TABLE(blend
->cb
, size
);
51 WRITE_CS_TABLE(blend
->cb_no_readwrite
, size
);
55 void r300_emit_blend_color_state(struct r300_context
* r300
,
56 unsigned size
, void* state
)
58 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
61 WRITE_CS_TABLE(bc
->cb
, size
);
64 void r300_emit_clip_state(struct r300_context
* r300
,
65 unsigned size
, void* state
)
67 struct r300_clip_state
* clip
= (struct r300_clip_state
*)state
;
70 WRITE_CS_TABLE(clip
->cb
, size
);
73 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
75 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
76 struct pipe_framebuffer_state
* fb
=
77 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
81 WRITE_CS_TABLE(&dsa
->cb_begin
, size
);
83 WRITE_CS_TABLE(dsa
->cb_no_readwrite
, size
);
87 static void get_rc_constant_state(
89 struct r300_context
* r300
,
90 struct rc_constant
* constant
)
92 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
93 struct r300_texture
*tex
;
95 assert(constant
->Type
== RC_CONSTANT_STATE
);
97 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
98 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
101 switch (constant
->u
.State
[0]) {
102 /* Factor for converting rectangle coords to
103 * normalized coords. Should only show up on non-r500. */
104 case RC_STATE_R300_TEXRECT_FACTOR
:
105 tex
= r300_texture(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
106 vec
[0] = 1.0 / tex
->desc
.width0
;
107 vec
[1] = 1.0 / tex
->desc
.height0
;
112 case RC_STATE_R300_TEXSCALE_FACTOR
:
113 tex
= r300_texture(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
114 /* Add a small number to the texture size to work around rounding errors in hw. */
115 vec
[0] = tex
->desc
.b
.b
.width0
/ (tex
->desc
.width0
+ 0.001f
);
116 vec
[1] = tex
->desc
.b
.b
.height0
/ (tex
->desc
.height0
+ 0.001f
);
117 vec
[2] = tex
->desc
.b
.b
.depth0
/ (tex
->desc
.depth0
+ 0.001f
);
121 case RC_STATE_R300_VIEWPORT_SCALE
:
122 vec
[0] = r300
->viewport
.scale
[0];
123 vec
[1] = r300
->viewport
.scale
[1];
124 vec
[2] = r300
->viewport
.scale
[2];
128 case RC_STATE_R300_VIEWPORT_OFFSET
:
129 vec
[0] = r300
->viewport
.translate
[0];
130 vec
[1] = r300
->viewport
.translate
[1];
131 vec
[2] = r300
->viewport
.translate
[2];
136 fprintf(stderr
, "r300: Implementation error: "
137 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
145 /* Convert a normal single-precision float into the 7.16 format
146 * used by the R300 fragment shader.
148 uint32_t pack_float24(float f
)
156 uint32_t float24
= 0;
163 mantissa
= frexpf(f
, &exponent
);
167 float24
|= (1 << 23);
168 mantissa
= mantissa
* -1.0;
170 /* Handle exponent, bias of 63 */
172 float24
|= (exponent
<< 16);
173 /* Kill 7 LSB of mantissa */
174 float24
|= (u
.u
& 0x7FFFFF) >> 7;
179 void r300_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
181 struct r300_fragment_shader
*fs
= r300_fs(r300
);
184 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
187 void r300_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
189 struct r300_fragment_shader
*fs
= r300_fs(r300
);
190 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
191 unsigned count
= fs
->shader
->externals_count
;
199 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, count
* 4);
200 if (buf
->remap_table
){
201 for (i
= 0; i
< count
; i
++) {
202 float *data
= (float*)&buf
->ptr
[buf
->remap_table
[i
]*4];
203 for (j
= 0; j
< 4; j
++)
204 OUT_CS(pack_float24(data
[j
]));
207 for (i
= 0; i
< count
; i
++)
208 for (j
= 0; j
< 4; j
++)
209 OUT_CS(pack_float24(*(float*)&buf
->ptr
[i
*4+j
]));
215 void r300_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
217 struct r300_fragment_shader
*fs
= r300_fs(r300
);
218 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
220 unsigned count
= fs
->shader
->rc_state_count
;
221 unsigned first
= fs
->shader
->externals_count
;
222 unsigned end
= constants
->Count
;
230 for(i
= first
; i
< end
; ++i
) {
231 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
234 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
236 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
237 for (j
= 0; j
< 4; j
++)
238 OUT_CS(pack_float24(data
[j
]));
244 void r500_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
246 struct r300_fragment_shader
*fs
= r300_fs(r300
);
249 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
252 void r500_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
254 struct r300_fragment_shader
*fs
= r300_fs(r300
);
255 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
256 unsigned count
= fs
->shader
->externals_count
;
263 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
264 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, count
* 4);
265 if (buf
->remap_table
){
266 for (unsigned i
= 0; i
< count
; i
++) {
267 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
268 OUT_CS_TABLE(data
, 4);
271 OUT_CS_TABLE(buf
->ptr
, count
* 4);
276 void r500_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
278 struct r300_fragment_shader
*fs
= r300_fs(r300
);
279 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
281 unsigned count
= fs
->shader
->rc_state_count
;
282 unsigned first
= fs
->shader
->externals_count
;
283 unsigned end
= constants
->Count
;
290 for(i
= first
; i
< end
; ++i
) {
291 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
294 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
296 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
297 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
298 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
299 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
300 OUT_CS_TABLE(data
, 4);
306 void r300_emit_gpu_flush(struct r300_context
*r300
, unsigned size
, void *state
)
308 struct r300_gpu_flush
*gpuflush
= (struct r300_gpu_flush
*)state
;
309 struct pipe_framebuffer_state
* fb
=
310 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
311 uint32_t height
= fb
->height
;
312 uint32_t width
= fb
->width
;
315 if (r300
->cbzb_clear
) {
316 struct r300_surface
*surf
= r300_surface(fb
->cbufs
[0]);
318 height
= surf
->cbzb_height
;
319 width
= surf
->cbzb_width
;
322 DBG(r300
, DBG_SCISSOR
,
323 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
324 width
, height
, r300
->cbzb_clear
? "YES" : "NO");
329 * By writing to the SC registers, SC & US assert idle. */
330 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
331 if (r300
->screen
->caps
.is_r500
) {
333 OUT_CS(((width
- 1) << R300_SCISSORS_X_SHIFT
) |
334 ((height
- 1) << R300_SCISSORS_Y_SHIFT
));
336 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
337 (1440 << R300_SCISSORS_Y_SHIFT
));
338 OUT_CS(((width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
339 ((height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
342 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
343 OUT_CS_TABLE(gpuflush
->cb_flush_clean
, 6);
347 void r300_emit_aa_state(struct r300_context
*r300
, unsigned size
, void *state
)
349 struct r300_aa_state
*aa
= (struct r300_aa_state
*)state
;
353 OUT_CS_REG(R300_GB_AA_CONFIG
, aa
->aa_config
);
356 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET
, 1);
357 OUT_CS_RELOC(aa
->dest
->cs_buffer
, aa
->dest
->offset
, 0, aa
->dest
->domain
);
359 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_PITCH
, 1);
360 OUT_CS_RELOC(aa
->dest
->cs_buffer
, aa
->dest
->pitch
, 0, aa
->dest
->domain
);
363 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL
, aa
->aaresolve_ctl
);
367 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
369 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
370 struct r300_surface
* surf
;
372 boolean can_hyperz
= r300
->rws
->get_value(r300
->rws
, R300_CAN_HYPERZ
);
377 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
378 * what we usually want. */
379 if (r300
->screen
->caps
.is_r500
) {
380 OUT_CS_REG(R300_RB3D_CCTL
,
381 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
);
383 OUT_CS_REG(R300_RB3D_CCTL
, 0);
386 /* Set up colorbuffers. */
387 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
388 surf
= r300_surface(fb
->cbufs
[i
]);
390 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
391 OUT_CS_RELOC(surf
->cs_buffer
, surf
->offset
, 0, surf
->domain
);
393 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
394 OUT_CS_RELOC(surf
->cs_buffer
, surf
->pitch
, 0, surf
->domain
);
397 /* Set up the ZB part of the CBZB clear. */
398 if (r300
->cbzb_clear
) {
399 surf
= r300_surface(fb
->cbufs
[0]);
401 OUT_CS_REG(R300_ZB_FORMAT
, surf
->cbzb_format
);
403 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
404 OUT_CS_RELOC(surf
->cs_buffer
, surf
->cbzb_midpoint_offset
, 0, surf
->domain
);
406 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
407 OUT_CS_RELOC(surf
->cs_buffer
, surf
->cbzb_pitch
, 0, surf
->domain
);
410 "CBZB clearing cbuf %08x %08x\n", surf
->cbzb_format
,
413 /* Set up a zbuffer. */
414 else if (fb
->zsbuf
) {
415 surf
= r300_surface(fb
->zsbuf
);
417 OUT_CS_REG(R300_ZB_FORMAT
, surf
->format
);
419 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
420 OUT_CS_RELOC(surf
->cs_buffer
, surf
->offset
, 0, surf
->domain
);
422 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
423 OUT_CS_RELOC(surf
->cs_buffer
, surf
->pitch
, 0, surf
->domain
);
427 struct r300_texture
*tex
;
428 int level
= surf
->base
.u
.tex
.level
;
429 tex
= r300_texture(surf
->base
.texture
);
431 surf_pitch
= surf
->pitch
& R300_DEPTHPITCH_MASK
;
433 if (r300
->screen
->caps
.hiz_ram
) {
434 if (tex
->hiz_mem
[level
]) {
435 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, tex
->hiz_mem
[level
]->ofs
<< 2);
436 OUT_CS_REG(R300_ZB_HIZ_PITCH
, surf_pitch
);
438 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, 0);
439 OUT_CS_REG(R300_ZB_HIZ_PITCH
, 0);
442 /* Z Mask RAM. (compressed zbuffer) */
443 if (tex
->zmask_mem
[level
]) {
444 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, tex
->zmask_mem
[level
]->ofs
<< 2);
445 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, surf_pitch
);
447 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, 0);
448 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, 0);
456 void r300_emit_hyperz_state(struct r300_context
*r300
,
457 unsigned size
, void *state
)
459 struct r300_hyperz_state
*z
= state
;
462 WRITE_CS_TABLE(&z
->cb_flush_begin
, size
);
464 WRITE_CS_TABLE(&z
->cb_begin
, size
- 2);
467 void r300_emit_hyperz_end(struct r300_context
*r300
)
469 struct r300_hyperz_state z
=
470 *(struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
474 z
.zb_depthclearvalue
= 0;
475 z
.sc_hyperz
= R300_SC_HYPERZ_ADJ_2
;
476 z
.gb_z_peq_config
= 0;
478 r300_emit_hyperz_state(r300
, r300
->hyperz_state
.size
, &z
);
481 void r300_emit_fb_state_pipelined(struct r300_context
*r300
,
482 unsigned size
, void *state
)
484 struct pipe_framebuffer_state
* fb
=
485 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
491 /* Colorbuffer format in the US block.
492 * (must be written after unpipelined regs) */
493 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0
, 4);
494 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
495 OUT_CS(r300_surface(fb
->cbufs
[i
])->format
);
498 OUT_CS(R300_US_OUT_FMT_UNUSED
);
501 /* Multisampling. Depends on framebuffer sample count.
502 * These are pipelined regs and as such cannot be moved
503 * to the AA state. */
504 if (r300
->rws
->get_value(r300
->rws
, R300_VID_DRM_2_3_0
)) {
505 unsigned mspos0
= 0x66666666;
506 unsigned mspos1
= 0x6666666;
508 if (fb
->nr_cbufs
&& fb
->cbufs
[0]->texture
->nr_samples
> 1) {
509 /* Subsample placement. These may not be optimal. */
510 switch (fb
->cbufs
[0]->texture
->nr_samples
) {
528 debug_printf("r300: Bad number of multisamples!\n");
532 OUT_CS_REG_SEQ(R300_GB_MSPOS0
, 2);
539 void r300_emit_query_start(struct r300_context
*r300
, unsigned size
, void*state
)
541 struct r300_query
*query
= r300
->query_current
;
548 if (r300
->screen
->caps
.family
== CHIP_FAMILY_RV530
) {
549 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
551 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
553 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
555 query
->begin_emitted
= TRUE
;
556 query
->flushed
= FALSE
;
559 static void r300_emit_query_end_frag_pipes(struct r300_context
*r300
,
560 struct r300_query
*query
)
562 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
563 struct r300_winsys_cs_buffer
*buf
= r300
->query_current
->cs_buffer
;
566 assert(caps
->num_frag_pipes
);
568 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
569 /* I'm not so sure I like this switch, but it's hard to be elegant
570 * when there's so many special cases...
572 * So here's the basic idea. For each pipe, enable writes to it only,
573 * then put out the relocation for ZPASS_ADDR, taking into account a
574 * 4-byte offset for each pipe. RV380 and older are special; they have
575 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
576 * so there's a chipset cap for that. */
577 switch (caps
->num_frag_pipes
) {
580 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
581 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
582 OUT_CS_RELOC(buf
, (query
->num_results
+ 3) * 4,
586 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
587 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
588 OUT_CS_RELOC(buf
, (query
->num_results
+ 2) * 4,
592 /* As mentioned above, accomodate RV380 and older. */
593 OUT_CS_REG(R300_SU_REG_DEST
,
594 1 << (caps
->high_second_pipe
? 3 : 1));
595 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
596 OUT_CS_RELOC(buf
, (query
->num_results
+ 1) * 4,
600 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
601 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
602 OUT_CS_RELOC(buf
, (query
->num_results
+ 0) * 4,
606 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
607 " pixel pipes!\n", caps
->num_frag_pipes
);
611 /* And, finally, reset it to normal... */
612 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
616 static void rv530_emit_query_end_single_z(struct r300_context
*r300
,
617 struct r300_query
*query
)
619 struct r300_winsys_cs_buffer
*buf
= r300
->query_current
->cs_buffer
;
623 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
624 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
625 OUT_CS_RELOC(buf
, query
->num_results
* 4, 0, query
->domain
);
626 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
630 static void rv530_emit_query_end_double_z(struct r300_context
*r300
,
631 struct r300_query
*query
)
633 struct r300_winsys_cs_buffer
*buf
= r300
->query_current
->cs_buffer
;
637 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
638 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
639 OUT_CS_RELOC(buf
, (query
->num_results
+ 0) * 4, 0, query
->domain
);
640 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
641 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
642 OUT_CS_RELOC(buf
, (query
->num_results
+ 1) * 4, 0, query
->domain
);
643 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
647 void r300_emit_query_end(struct r300_context
* r300
)
649 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
650 struct r300_query
*query
= r300
->query_current
;
655 if (query
->begin_emitted
== FALSE
)
658 if (caps
->family
== CHIP_FAMILY_RV530
) {
659 if (caps
->num_z_pipes
== 2)
660 rv530_emit_query_end_double_z(r300
, query
);
662 rv530_emit_query_end_single_z(r300
, query
);
664 r300_emit_query_end_frag_pipes(r300
, query
);
666 query
->begin_emitted
= FALSE
;
667 query
->num_results
+= query
->num_pipes
;
669 /* XXX grab all the results and reset the counter. */
670 if (query
->num_results
>= query
->buffer_size
/ 4 - 4) {
671 query
->num_results
= (query
->buffer_size
/ 4) / 2;
672 fprintf(stderr
, "r300: Rewinding OQBO...\n");
676 void r300_emit_invariant_state(struct r300_context
*r300
,
677 unsigned size
, void *state
)
680 WRITE_CS_TABLE(state
, size
);
683 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
685 struct r300_rs_state
* rs
= state
;
689 OUT_CS_TABLE(rs
->cb_main
, RS_STATE_MAIN_SIZE
);
690 if (rs
->polygon_offset_enable
) {
691 if (r300
->zbuffer_bpp
== 16) {
692 OUT_CS_TABLE(rs
->cb_poly_offset_zb16
, 5);
694 OUT_CS_TABLE(rs
->cb_poly_offset_zb24
, 5);
700 void r300_emit_rs_block_state(struct r300_context
* r300
,
701 unsigned size
, void* state
)
703 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
705 /* It's the same for both INST and IP tables */
706 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
709 if (DBG_ON(r300
, DBG_RS_BLOCK
)) {
710 r500_dump_rs_block(rs
);
712 fprintf(stderr
, "r300: RS emit:\n");
714 for (i
= 0; i
< count
; i
++)
715 fprintf(stderr
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
717 for (i
= 0; i
< count
; i
++)
718 fprintf(stderr
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
720 fprintf(stderr
, " : count: 0x%08x inst_count: 0x%08x\n",
721 rs
->count
, rs
->inst_count
);
725 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
726 OUT_CS(rs
->vap_vtx_state_cntl
);
727 OUT_CS(rs
->vap_vsm_vtx_assm
);
728 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
729 OUT_CS(rs
->vap_out_vtx_fmt
[0]);
730 OUT_CS(rs
->vap_out_vtx_fmt
[1]);
731 OUT_CS_REG_SEQ(R300_GB_ENABLE
, 1);
732 OUT_CS(rs
->gb_enable
);
734 if (r300
->screen
->caps
.is_r500
) {
735 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
737 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
739 OUT_CS_TABLE(rs
->ip
, count
);
741 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
743 OUT_CS(rs
->inst_count
);
745 if (r300
->screen
->caps
.is_r500
) {
746 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
748 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
750 OUT_CS_TABLE(rs
->inst
, count
);
754 void r300_emit_scissor_state(struct r300_context
* r300
,
755 unsigned size
, void* state
)
757 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
761 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
762 if (r300
->screen
->caps
.is_r500
) {
763 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
764 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
765 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
766 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
768 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
769 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
770 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
771 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
776 void r300_emit_textures_state(struct r300_context
*r300
,
777 unsigned size
, void *state
)
779 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
780 struct r300_texture_sampler_state
*texstate
;
781 struct r300_texture
*tex
;
786 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
788 for (i
= 0; i
< allstate
->count
; i
++) {
789 if ((1 << i
) & allstate
->tx_enable
) {
790 texstate
= &allstate
->regs
[i
];
791 tex
= r300_texture(allstate
->sampler_views
[i
]->base
.texture
);
793 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
794 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
795 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
796 texstate
->border_color
);
798 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
799 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
800 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
802 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
803 OUT_CS_TEX_RELOC(tex
, texstate
->format
.tile_config
, tex
->domain
,
810 static void r300_update_aos_cb(struct r300_context
*r300
, unsigned packet_size
)
812 struct pipe_vertex_buffer
*vb1
, *vb2
, *vbuf
= r300
->vertex_buffer
;
813 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
814 unsigned *hw_format_size
= r300
->velems
->hw_format_size
;
815 unsigned size1
, size2
, aos_count
= r300
->velems
->count
;
819 BEGIN_CB(r300
->aos_cb
, packet_size
);
820 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
821 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
822 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
823 size1
= hw_format_size
[i
];
824 size2
= hw_format_size
[i
+1];
826 OUT_CB(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
827 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
828 OUT_CB(vb1
->buffer_offset
+ velem
[i
].src_offset
);
829 OUT_CB(vb2
->buffer_offset
+ velem
[i
+1].src_offset
);
833 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
834 size1
= hw_format_size
[i
];
836 OUT_CB(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
837 OUT_CB(vb1
->buffer_offset
+ velem
[i
].src_offset
);
841 r300
->aos_dirty
= FALSE
;
844 void r300_emit_aos(struct r300_context
* r300
, int offset
, boolean indexed
)
846 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
847 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
848 struct r300_buffer
*buf
;
850 unsigned aos_count
= r300
->velems
->count
;
851 unsigned packet_size
= (aos_count
* 3 + 1) / 2;
854 BEGIN_CS(2 + packet_size
+ aos_count
* 2);
855 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
856 OUT_CS(aos_count
| (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
859 if (r300
->aos_dirty
) {
860 r300_update_aos_cb(r300
, packet_size
);
862 OUT_CS_TABLE(r300
->aos_cb
, packet_size
);
864 struct pipe_vertex_buffer
*vb1
, *vb2
;
865 unsigned *hw_format_size
= r300
->velems
->hw_format_size
;
866 unsigned size1
, size2
;
868 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
869 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
870 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
871 size1
= hw_format_size
[i
];
872 size2
= hw_format_size
[i
+1];
874 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
875 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
876 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
877 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
881 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
882 size1
= hw_format_size
[i
];
884 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
885 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
889 for (i
= 0; i
< aos_count
; i
++) {
890 buf
= r300_buffer(vbuf
[velem
[i
].vertex_buffer_index
].buffer
);
891 OUT_CS_BUF_RELOC_NO_OFFSET(&buf
->b
.b
, buf
->domain
, 0);
896 void r300_emit_aos_swtcl(struct r300_context
*r300
, boolean indexed
)
900 DBG(r300
, DBG_SWTCL
, "r300: Preparing vertex buffer %p for render, "
901 "vertex size %d\n", r300
->vbo
,
902 r300
->vertex_info
.size
);
903 /* Set the pointer to our vertex buffer. The emitted values are this:
904 * PACKET3 [3D_LOAD_VBPNTR]
906 * FORMAT [size | stride << 8]
907 * OFFSET [offset into BO]
908 * VBPNTR [relocated BO]
911 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
912 OUT_CS(1 | (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
913 OUT_CS(r300
->vertex_info
.size
|
914 (r300
->vertex_info
.size
<< 8));
915 OUT_CS(r300
->draw_vbo_offset
);
916 OUT_CS_BUF_RELOC(r300
->vbo
, 0, r300_buffer(r300
->vbo
)->domain
, 0);
920 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
921 unsigned size
, void* state
)
923 struct r300_vertex_stream_state
*streams
=
924 (struct r300_vertex_stream_state
*)state
;
928 if (DBG_ON(r300
, DBG_PSC
)) {
929 fprintf(stderr
, "r300: PSC emit:\n");
931 for (i
= 0; i
< streams
->count
; i
++) {
932 fprintf(stderr
, " : prog_stream_cntl%d: 0x%08x\n", i
,
933 streams
->vap_prog_stream_cntl
[i
]);
936 for (i
= 0; i
< streams
->count
; i
++) {
937 fprintf(stderr
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
938 streams
->vap_prog_stream_cntl_ext
[i
]);
943 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
944 OUT_CS_TABLE(streams
->vap_prog_stream_cntl
, streams
->count
);
945 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
946 OUT_CS_TABLE(streams
->vap_prog_stream_cntl_ext
, streams
->count
);
950 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
955 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
959 void r300_emit_vap_invariant_state(struct r300_context
*r300
,
960 unsigned size
, void *state
)
963 WRITE_CS_TABLE(state
, size
);
966 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
968 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
969 struct r300_vertex_program_code
* code
= &vs
->code
;
970 struct r300_screen
* r300screen
= r300
->screen
;
971 unsigned instruction_count
= code
->length
/ 4;
973 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
974 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
975 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
976 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
978 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
979 vtx_mem_size
/ output_count
, 10);
980 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 5);
986 /* R300_VAP_PVS_CODE_CNTL_0
987 * R300_VAP_PVS_CONST_CNTL
988 * R300_VAP_PVS_CODE_CNTL_1
989 * See the r5xx docs for instructions on how to use these. */
990 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0
, R300_PVS_FIRST_INST(0) |
991 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
992 R300_PVS_LAST_INST(instruction_count
- 1));
993 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1
, instruction_count
- 1);
995 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
996 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
997 OUT_CS_TABLE(code
->body
.d
, code
->length
);
999 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
1000 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
1001 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
1002 R300_PVS_VF_MAX_VTX_NUM(12) |
1003 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
1005 /* Emit flow control instructions. */
1006 if (code
->num_fc_ops
) {
1008 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC
, code
->fc_ops
);
1009 if (r300screen
->caps
.is_r500
) {
1010 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0
, code
->num_fc_ops
* 2);
1011 OUT_CS_TABLE(code
->fc_op_addrs
.r500
, code
->num_fc_ops
* 2);
1013 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0
, code
->num_fc_ops
);
1014 OUT_CS_TABLE(code
->fc_op_addrs
.r300
, code
->num_fc_ops
);
1016 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
, code
->num_fc_ops
);
1017 OUT_CS_TABLE(code
->fc_loop_index
, code
->num_fc_ops
);
1023 void r300_emit_vs_constants(struct r300_context
* r300
,
1024 unsigned size
, void *state
)
1027 ((struct r300_vertex_shader
*)r300
->vs_state
.state
)->externals_count
;
1028 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
1029 struct r300_vertex_shader
*vs
= (struct r300_vertex_shader
*)r300
->vs_state
.state
;
1031 int imm_first
= vs
->externals_count
;
1032 int imm_end
= vs
->code
.constants
.Count
;
1033 int imm_count
= vs
->immediates_count
;
1037 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL
,
1038 R300_PVS_CONST_BASE_OFFSET(buf
->buffer_base
) |
1039 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end
- 1, 0)));
1040 if (vs
->externals_count
) {
1041 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1042 (r300
->screen
->caps
.is_r500
?
1043 R500_PVS_CONST_START
: R300_PVS_CONST_START
) + buf
->buffer_base
);
1044 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, count
* 4);
1045 if (buf
->remap_table
){
1046 for (i
= 0; i
< count
; i
++) {
1047 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
1048 OUT_CS_TABLE(data
, 4);
1051 OUT_CS_TABLE(buf
->ptr
, count
* 4);
1055 /* Emit immediates. */
1057 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1058 (r300
->screen
->caps
.is_r500
?
1059 R500_PVS_CONST_START
: R300_PVS_CONST_START
) +
1060 buf
->buffer_base
+ imm_first
);
1061 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, imm_count
* 4);
1062 for (i
= imm_first
; i
< imm_end
; i
++) {
1063 const float *data
= vs
->code
.constants
.Constants
[i
].u
.Immediate
;
1064 OUT_CS_TABLE(data
, 4);
1070 void r300_emit_viewport_state(struct r300_context
* r300
,
1071 unsigned size
, void* state
)
1073 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
1077 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
1078 OUT_CS_TABLE(&viewport
->xscale
, 6);
1079 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
1083 static void r300_emit_hiz_line_clear(struct r300_context
*r300
, int start
, uint16_t count
, uint32_t val
)
1087 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ
, 2);
1094 static void r300_emit_zmask_line_clear(struct r300_context
*r300
, int start
, uint16_t count
, uint32_t val
)
1098 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK
, 2);
1105 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1107 void r300_emit_hiz_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1109 struct pipe_framebuffer_state
*fb
=
1110 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1111 struct r300_hyperz_state
*z
=
1112 (struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
1113 struct r300_screen
* r300screen
= r300
->screen
;
1114 uint32_t stride
, offset
= 0, height
, offset_shift
;
1115 struct r300_texture
* tex
;
1118 tex
= r300_texture(fb
->zsbuf
->texture
);
1120 offset
= tex
->hiz_mem
[fb
->zsbuf
->u
.tex
.level
]->ofs
;
1121 stride
= tex
->desc
.stride_in_pixels
[fb
->zsbuf
->u
.tex
.level
];
1123 /* convert from pixels to 4x4 blocks */
1124 stride
= ALIGN_DIVUP(stride
, 4);
1126 stride
= ALIGN_DIVUP(stride
, r300screen
->caps
.num_frag_pipes
);
1127 /* there are 4 blocks per dwords */
1128 stride
= ALIGN_DIVUP(stride
, 4);
1130 height
= ALIGN_DIVUP(fb
->zsbuf
->height
, 4);
1133 offset_shift
+= (r300screen
->caps
.num_frag_pipes
/ 2);
1135 for (i
= 0; i
< height
; i
++) {
1136 offset
= i
* stride
;
1137 offset
<<= offset_shift
;
1138 r300_emit_hiz_line_clear(r300
, offset
, stride
, 0xffffffff);
1140 z
->current_func
= -1;
1142 /* Mark the current zbuffer's hiz ram as in use. */
1143 tex
->hiz_in_use
[fb
->zsbuf
->u
.tex
.level
] = TRUE
;
1146 void r300_emit_zmask_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1148 struct pipe_framebuffer_state
*fb
=
1149 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1150 struct r300_screen
* r300screen
= r300
->screen
;
1151 uint32_t stride
, offset
= 0;
1152 struct r300_texture
* tex
;
1154 int mult
, offset_shift
;
1156 tex
= r300_texture(fb
->zsbuf
->texture
);
1157 stride
= tex
->desc
.stride_in_pixels
[fb
->zsbuf
->u
.tex
.level
];
1159 offset
= tex
->zmask_mem
[fb
->zsbuf
->u
.tex
.level
]->ofs
;
1161 if (r300
->z_compression
== RV350_Z_COMPRESS_88
)
1166 height
= ALIGN_DIVUP(fb
->zsbuf
->height
, mult
);
1169 offset_shift
+= (r300screen
->caps
.num_frag_pipes
/ 2);
1170 stride
= ALIGN_DIVUP(stride
, r300screen
->caps
.num_frag_pipes
);
1172 /* okay have width in pixels - divide by block width */
1173 stride
= ALIGN_DIVUP(stride
, mult
);
1174 /* have width in blocks - divide by number of fragment pipes screen width */
1175 /* 16 blocks per dword */
1176 stride
= ALIGN_DIVUP(stride
, 16);
1178 for (i
= 0; i
< height
; i
++) {
1179 offset
= i
* stride
;
1180 offset
<<= offset_shift
;
1181 r300_emit_zmask_line_clear(r300
, offset
, stride
, 0x0);//0xffffffff);
1184 /* Mark the current zbuffer's zmask as in use. */
1185 tex
->zmask_in_use
[fb
->zsbuf
->u
.tex
.level
] = TRUE
;
1188 void r300_emit_ztop_state(struct r300_context
* r300
,
1189 unsigned size
, void* state
)
1191 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
1195 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
1199 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
1204 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
1208 boolean
r300_emit_buffer_validate(struct r300_context
*r300
,
1209 boolean do_validate_vertex_buffers
,
1210 struct pipe_resource
*index_buffer
)
1212 struct pipe_framebuffer_state
* fb
=
1213 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1214 struct r300_textures_state
*texstate
=
1215 (struct r300_textures_state
*)r300
->textures_state
.state
;
1216 struct r300_texture
* tex
;
1217 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
1218 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
1219 struct pipe_resource
*pbuf
;
1222 /* Clean out BOs. */
1223 r300
->rws
->cs_reset_buffers(r300
->cs
);
1225 /* Color buffers... */
1226 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1227 tex
= r300_texture(fb
->cbufs
[i
]->texture
);
1228 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
1229 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->cs_buffer
, 0,
1230 r300_surface(fb
->cbufs
[i
])->domain
);
1232 /* ...depth buffer... */
1234 tex
= r300_texture(fb
->zsbuf
->texture
);
1235 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
1236 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->cs_buffer
, 0,
1237 r300_surface(fb
->zsbuf
)->domain
);
1239 /* ...textures... */
1240 for (i
= 0; i
< texstate
->count
; i
++) {
1241 if (!(texstate
->tx_enable
& (1 << i
))) {
1245 tex
= r300_texture(texstate
->sampler_views
[i
]->base
.texture
);
1246 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->cs_buffer
, tex
->domain
, 0);
1248 /* ...occlusion query buffer... */
1249 if (r300
->query_current
)
1250 r300
->rws
->cs_add_buffer(r300
->cs
, r300
->query_current
->cs_buffer
,
1251 0, r300
->query_current
->domain
);
1252 /* ...vertex buffer for SWTCL path... */
1254 r300
->rws
->cs_add_buffer(r300
->cs
, r300_buffer(r300
->vbo
)->cs_buf
,
1255 r300_buffer(r300
->vbo
)->domain
, 0);
1256 /* ...vertex buffers for HWTCL path... */
1257 if (do_validate_vertex_buffers
) {
1258 for (i
= 0; i
< r300
->velems
->count
; i
++) {
1259 pbuf
= vbuf
[velem
[i
].vertex_buffer_index
].buffer
;
1263 r300
->rws
->cs_add_buffer(r300
->cs
, r300_buffer(pbuf
)->cs_buf
,
1264 r300_buffer(pbuf
)->domain
, 0);
1267 /* ...and index buffer for HWTCL path. */
1269 r300
->rws
->cs_add_buffer(r300
->cs
, r300_buffer(index_buffer
)->cs_buf
,
1270 r300_buffer(index_buffer
)->domain
, 0);
1272 if (!r300
->rws
->cs_validate(r300
->cs
)) {
1279 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1281 struct r300_atom
* atom
;
1282 unsigned dwords
= 0;
1284 foreach_dirty_atom(r300
, atom
) {
1286 dwords
+= atom
->size
;
1290 /* let's reserve some more, just in case */
1296 unsigned r300_get_num_cs_end_dwords(struct r300_context
*r300
)
1298 unsigned dwords
= 0;
1300 /* Emitted in flush. */
1301 dwords
+= 26; /* emit_query_end */
1302 dwords
+= r300
->hyperz_state
.size
+ 2; /* emit_hyperz_end + zcache flush */
1303 if (r300
->screen
->caps
.index_bias_supported
)
1309 /* Emit all dirty state. */
1310 void r300_emit_dirty_state(struct r300_context
* r300
)
1312 struct r300_atom
*atom
;
1314 foreach_dirty_atom(r300
, atom
) {
1316 atom
->emit(r300
, atom
->size
, atom
->state
);
1317 atom
->dirty
= FALSE
;
1321 r300
->first_dirty
= NULL
;
1322 r300
->last_dirty
= NULL
;