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1092ec42c8e9844bf8abdd59449bf8b462f3bb26
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_state_derived.h"
36 #include "r300_state_inlines.h"
37 #include "r300_texture.h"
38 #include "r300_vs.h"
39
40 void r300_emit_blend_state(struct r300_context* r300, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 CS_LOCALS(r300);
44 BEGIN_CS(8);
45 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
46 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
47 if (r300->framebuffer_state.nr_cbufs) {
48 OUT_CS(blend->blend_control);
49 OUT_CS(blend->alpha_blend_control);
50 OUT_CS(blend->color_channel_mask);
51 } else {
52 OUT_CS(0);
53 OUT_CS(0);
54 OUT_CS(0);
55 /* XXX also disable fastfill here once it's supported */
56 }
57 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
58 END_CS;
59 }
60
61 void r300_emit_blend_color_state(struct r300_context* r300, void* state)
62 {
63 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
64 struct r300_screen* r300screen = r300_screen(r300->context.screen);
65 CS_LOCALS(r300);
66
67 if (r300screen->caps->is_r500) {
68 BEGIN_CS(3);
69 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
70 OUT_CS(bc->blend_color_red_alpha);
71 OUT_CS(bc->blend_color_green_blue);
72 END_CS;
73 } else {
74 BEGIN_CS(2);
75 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
76 END_CS;
77 }
78 }
79
80 void r300_emit_clip_state(struct r300_context* r300, void* state)
81 {
82 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
83 int i;
84 struct r300_screen* r300screen = r300_screen(r300->context.screen);
85 CS_LOCALS(r300);
86
87 if (r300screen->caps->has_tcl) {
88 BEGIN_CS(5 + (6 * 4));
89 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
90 (r300screen->caps->is_r500 ?
91 R500_PVS_UCP_START : R300_PVS_UCP_START));
92 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
93 for (i = 0; i < 6; i++) {
94 OUT_CS_32F(clip->ucp[i][0]);
95 OUT_CS_32F(clip->ucp[i][1]);
96 OUT_CS_32F(clip->ucp[i][2]);
97 OUT_CS_32F(clip->ucp[i][3]);
98 }
99 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
100 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
101 END_CS;
102 } else {
103 BEGIN_CS(2);
104 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
105 END_CS;
106 }
107
108 }
109
110 void r300_emit_dsa_state(struct r300_context* r300, void* state)
111 {
112 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
113 struct r300_screen* r300screen = r300_screen(r300->context.screen);
114 CS_LOCALS(r300);
115
116 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 6);
117 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
118
119 /* not needed since we use the 8bit alpha ref */
120 /*if (r300screen->caps->is_r500) {
121 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
122 }*/
123
124 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
125
126 if (r300->framebuffer_state.zsbuf) {
127 OUT_CS(dsa->z_buffer_control);
128 OUT_CS(dsa->z_stencil_control);
129 } else {
130 OUT_CS(0);
131 OUT_CS(0);
132 }
133
134 OUT_CS(dsa->stencil_ref_mask);
135
136 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
137 if (r300screen->caps->is_r500) {
138 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
139 }
140 END_CS;
141 }
142
143 static const float * get_shader_constant(
144 struct r300_context * r300,
145 struct rc_constant * constant,
146 struct r300_constant_buffer * externals)
147 {
148 struct r300_viewport_state* viewport =
149 (struct r300_viewport_state*)r300->viewport_state.state;
150 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
151 struct pipe_texture *tex;
152
153 switch(constant->Type) {
154 case RC_CONSTANT_EXTERNAL:
155 return externals->constants[constant->u.External];
156
157 case RC_CONSTANT_IMMEDIATE:
158 return constant->u.Immediate;
159
160 case RC_CONSTANT_STATE:
161 switch (constant->u.State[0]) {
162 /* Factor for converting rectangle coords to
163 * normalized coords. Should only show up on non-r500. */
164 case RC_STATE_R300_TEXRECT_FACTOR:
165 tex = &r300->textures[constant->u.State[1]]->tex;
166 vec[0] = 1.0 / tex->width0;
167 vec[1] = 1.0 / tex->height0;
168 break;
169
170 /* Texture compare-fail value. */
171 /* XXX Since Gallium doesn't support GL_ARB_shadow_ambient,
172 * this is always (0,0,0,0), right? */
173 case RC_STATE_SHADOW_AMBIENT:
174 vec[3] = 0;
175 break;
176
177 case RC_STATE_R300_VIEWPORT_SCALE:
178 if (r300->tcl_bypass) {
179 vec[0] = 1;
180 vec[1] = 1;
181 vec[2] = 1;
182 } else {
183 vec[0] = viewport->xscale;
184 vec[1] = viewport->yscale;
185 vec[2] = viewport->zscale;
186 }
187 break;
188
189 case RC_STATE_R300_VIEWPORT_OFFSET:
190 if (!r300->tcl_bypass) {
191 vec[0] = viewport->xoffset;
192 vec[1] = viewport->yoffset;
193 vec[2] = viewport->zoffset;
194 }
195 break;
196
197 default:
198 debug_printf("r300: Implementation error: "
199 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
200 }
201 break;
202
203 default:
204 debug_printf("r300: Implementation error: "
205 "Unhandled constant type %d\n", constant->Type);
206 }
207
208 /* This should either be (0, 0, 0, 1), which should be a relatively safe
209 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
210 * state factors. */
211 return vec;
212 }
213
214 /* Convert a normal single-precision float into the 7.16 format
215 * used by the R300 fragment shader.
216 */
217 static uint32_t pack_float24(float f)
218 {
219 union {
220 float fl;
221 uint32_t u;
222 } u;
223 float mantissa;
224 int exponent;
225 uint32_t float24 = 0;
226
227 if (f == 0.0)
228 return 0;
229
230 u.fl = f;
231
232 mantissa = frexpf(f, &exponent);
233
234 /* Handle -ve */
235 if (mantissa < 0) {
236 float24 |= (1 << 23);
237 mantissa = mantissa * -1.0;
238 }
239 /* Handle exponent, bias of 63 */
240 exponent += 62;
241 float24 |= (exponent << 16);
242 /* Kill 7 LSB of mantissa */
243 float24 |= (u.u & 0x7FFFFF) >> 7;
244
245 return float24;
246 }
247
248 void r300_emit_fragment_program_code(struct r300_context* r300,
249 struct rX00_fragment_program_code* generic_code)
250 {
251 struct r300_fragment_program_code * code = &generic_code->code.r300;
252 int i;
253 CS_LOCALS(r300);
254
255 BEGIN_CS(15 +
256 code->alu.length * 4 +
257 (code->tex.length ? (1 + code->tex.length) : 0));
258
259 OUT_CS_REG(R300_US_CONFIG, code->config);
260 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
261 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
262
263 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
264 for(i = 0; i < 4; ++i)
265 OUT_CS(code->code_addr[i]);
266
267 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
268 for (i = 0; i < code->alu.length; i++)
269 OUT_CS(code->alu.inst[i].rgb_inst);
270
271 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
272 for (i = 0; i < code->alu.length; i++)
273 OUT_CS(code->alu.inst[i].rgb_addr);
274
275 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
276 for (i = 0; i < code->alu.length; i++)
277 OUT_CS(code->alu.inst[i].alpha_inst);
278
279 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
280 for (i = 0; i < code->alu.length; i++)
281 OUT_CS(code->alu.inst[i].alpha_addr);
282
283 if (code->tex.length) {
284 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
285 for(i = 0; i < code->tex.length; ++i)
286 OUT_CS(code->tex.inst[i]);
287 }
288
289 END_CS;
290 }
291
292 void r300_emit_fs_constant_buffer(struct r300_context* r300,
293 struct rc_constant_list* constants)
294 {
295 int i;
296 CS_LOCALS(r300);
297
298 if (constants->Count == 0)
299 return;
300
301 BEGIN_CS(constants->Count * 4 + 1);
302 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
303 for(i = 0; i < constants->Count; ++i) {
304 const float * data = get_shader_constant(r300,
305 &constants->Constants[i],
306 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
307 OUT_CS(pack_float24(data[0]));
308 OUT_CS(pack_float24(data[1]));
309 OUT_CS(pack_float24(data[2]));
310 OUT_CS(pack_float24(data[3]));
311 }
312 END_CS;
313 }
314
315 static void r300_emit_fragment_depth_config(struct r300_context* r300,
316 struct r300_fragment_shader* fs)
317 {
318 CS_LOCALS(r300);
319
320 BEGIN_CS(4);
321 if (r300_fragment_shader_writes_depth(fs)) {
322 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
323 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
324 } else {
325 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
326 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
327 }
328 END_CS;
329 }
330
331 void r500_emit_fragment_program_code(struct r300_context* r300,
332 struct rX00_fragment_program_code* generic_code)
333 {
334 struct r500_fragment_program_code * code = &generic_code->code.r500;
335 int i;
336 CS_LOCALS(r300);
337
338 BEGIN_CS(13 +
339 ((code->inst_end + 1) * 6));
340 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
341 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
342 OUT_CS_REG(R500_US_CODE_RANGE,
343 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
344 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
345 OUT_CS_REG(R500_US_CODE_ADDR,
346 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
347
348 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
349 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
350 for (i = 0; i <= code->inst_end; i++) {
351 OUT_CS(code->inst[i].inst0);
352 OUT_CS(code->inst[i].inst1);
353 OUT_CS(code->inst[i].inst2);
354 OUT_CS(code->inst[i].inst3);
355 OUT_CS(code->inst[i].inst4);
356 OUT_CS(code->inst[i].inst5);
357 }
358
359 END_CS;
360 }
361
362 void r500_emit_fs_constant_buffer(struct r300_context* r300,
363 struct rc_constant_list* constants)
364 {
365 int i;
366 CS_LOCALS(r300);
367
368 if (constants->Count == 0)
369 return;
370
371 BEGIN_CS(constants->Count * 4 + 3);
372 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
373 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
374 for (i = 0; i < constants->Count; i++) {
375 const float * data = get_shader_constant(r300,
376 &constants->Constants[i],
377 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
378 OUT_CS_32F(data[0]);
379 OUT_CS_32F(data[1]);
380 OUT_CS_32F(data[2]);
381 OUT_CS_32F(data[3]);
382 }
383 END_CS;
384 }
385
386 void r300_emit_fb_state(struct r300_context* r300,
387 struct pipe_framebuffer_state* fb)
388 {
389 struct r300_texture* tex;
390 struct pipe_surface* surf;
391 int i;
392 CS_LOCALS(r300);
393
394 /* Shouldn't fail unless there is a bug in the state tracker. */
395 assert(fb->nr_cbufs <= 4);
396
397 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
398 (fb->zsbuf ? 10 : 0) + 6);
399
400 /* Flush and free renderbuffer caches. */
401 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
402 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
403 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
404 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
405 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
406 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
407
408 /* Set the number of colorbuffers. */
409 OUT_CS_REG(R300_RB3D_CCTL, R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
410
411 /* Set up colorbuffers. */
412 for (i = 0; i < fb->nr_cbufs; i++) {
413 surf = fb->cbufs[i];
414 tex = (struct r300_texture*)surf->texture;
415 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
416
417 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
418 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
419
420 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
421 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
422 r300_translate_colorformat(tex->tex.format) |
423 R300_COLOR_TILE(tex->macrotile) |
424 R300_COLOR_MICROTILE(tex->microtile),
425 0, RADEON_GEM_DOMAIN_VRAM, 0);
426
427 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
428 r300_translate_out_fmt(surf->format));
429 }
430
431 /* Disable unused colorbuffers. */
432 for (; i < 4; i++) {
433 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
434 }
435
436 /* Set up a zbuffer. */
437 if (fb->zsbuf) {
438 surf = fb->zsbuf;
439 tex = (struct r300_texture*)surf->texture;
440 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
441
442 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
443 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
444
445 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
446
447 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
448 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
449 R300_DEPTHMACROTILE(tex->macrotile) |
450 R300_DEPTHMICROTILE(tex->microtile),
451 0, RADEON_GEM_DOMAIN_VRAM, 0);
452 }
453
454 END_CS;
455 }
456
457 static void r300_emit_query_start(struct r300_context *r300)
458 {
459 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
460 struct r300_query *query = r300->query_current;
461 CS_LOCALS(r300);
462
463 if (!query)
464 return;
465
466 BEGIN_CS(4);
467 if (caps->family == CHIP_FAMILY_RV530) {
468 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
469 } else {
470 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
471 }
472 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
473 END_CS;
474 query->begin_emitted = TRUE;
475 }
476
477
478 static void r300_emit_query_finish(struct r300_context *r300,
479 struct r300_query *query)
480 {
481 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
482 CS_LOCALS(r300);
483
484 assert(caps->num_frag_pipes);
485
486 BEGIN_CS(6 * caps->num_frag_pipes + 2);
487 /* I'm not so sure I like this switch, but it's hard to be elegant
488 * when there's so many special cases...
489 *
490 * So here's the basic idea. For each pipe, enable writes to it only,
491 * then put out the relocation for ZPASS_ADDR, taking into account a
492 * 4-byte offset for each pipe. RV380 and older are special; they have
493 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
494 * so there's a chipset cap for that. */
495 switch (caps->num_frag_pipes) {
496 case 4:
497 /* pipe 3 only */
498 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
499 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
500 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
501 0, RADEON_GEM_DOMAIN_GTT, 0);
502 case 3:
503 /* pipe 2 only */
504 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
505 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
506 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
507 0, RADEON_GEM_DOMAIN_GTT, 0);
508 case 2:
509 /* pipe 1 only */
510 /* As mentioned above, accomodate RV380 and older. */
511 OUT_CS_REG(R300_SU_REG_DEST,
512 1 << (caps->high_second_pipe ? 3 : 1));
513 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
514 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
515 0, RADEON_GEM_DOMAIN_GTT, 0);
516 case 1:
517 /* pipe 0 only */
518 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
519 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
520 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
521 0, RADEON_GEM_DOMAIN_GTT, 0);
522 break;
523 default:
524 debug_printf("r300: Implementation error: Chipset reports %d"
525 " pixel pipes!\n", caps->num_frag_pipes);
526 assert(0);
527 }
528
529 /* And, finally, reset it to normal... */
530 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
531 END_CS;
532 }
533
534 static void rv530_emit_query_single(struct r300_context *r300,
535 struct r300_query *query)
536 {
537 CS_LOCALS(r300);
538
539 BEGIN_CS(8);
540 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
541 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
542 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
543 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
544 END_CS;
545 }
546
547 static void rv530_emit_query_double(struct r300_context *r300,
548 struct r300_query *query)
549 {
550 CS_LOCALS(r300);
551
552 BEGIN_CS(14);
553 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
554 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
555 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
556 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
557 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
558 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
559 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
560 END_CS;
561 }
562
563 void r300_emit_query_end(struct r300_context* r300)
564 {
565 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
566 struct r300_query *query = r300->query_current;
567
568 if (!query)
569 return;
570
571 if (query->begin_emitted == FALSE)
572 return;
573
574 if (caps->family == CHIP_FAMILY_RV530) {
575 if (caps->num_z_pipes == 2)
576 rv530_emit_query_double(r300, query);
577 else
578 rv530_emit_query_single(r300, query);
579 } else
580 r300_emit_query_finish(r300, query);
581 }
582
583 void r300_emit_rs_state(struct r300_context* r300, void* state)
584 {
585 struct r300_rs_state* rs = (struct r300_rs_state*)state;
586 CS_LOCALS(r300);
587
588 BEGIN_CS(22);
589 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
590 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
591 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
592 OUT_CS(rs->point_minmax);
593 OUT_CS(rs->line_control);
594 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
595 OUT_CS(rs->depth_scale_front);
596 OUT_CS(rs->depth_offset_front);
597 OUT_CS(rs->depth_scale_back);
598 OUT_CS(rs->depth_offset_back);
599 OUT_CS(rs->polygon_offset_enable);
600 OUT_CS(rs->cull_mode);
601 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
602 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
603 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
604 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
605 END_CS;
606 }
607
608 void r300_emit_rs_block_state(struct r300_context* r300,
609 struct r300_rs_block* rs)
610 {
611 int i;
612 struct r300_screen* r300screen = r300_screen(r300->context.screen);
613 CS_LOCALS(r300);
614
615 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
616
617 BEGIN_CS(21);
618 if (r300screen->caps->is_r500) {
619 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
620 } else {
621 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
622 }
623 for (i = 0; i < 8; i++) {
624 OUT_CS(rs->ip[i]);
625 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
626 }
627
628 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
629 OUT_CS(rs->count);
630 OUT_CS(rs->inst_count);
631
632 if (r300screen->caps->is_r500) {
633 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
634 } else {
635 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
636 }
637 for (i = 0; i < 8; i++) {
638 OUT_CS(rs->inst[i]);
639 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
640 }
641
642 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
643 rs->count, rs->inst_count);
644
645 END_CS;
646 }
647
648 void r300_emit_scissor_state(struct r300_context* r300, void* state)
649 {
650 unsigned minx, miny, maxx, maxy;
651 uint32_t top_left, bottom_right;
652 struct r300_screen* r300screen = r300_screen(r300->context.screen);
653 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
654 CS_LOCALS(r300);
655
656 minx = miny = 0;
657 maxx = r300->framebuffer_state.width;
658 maxy = r300->framebuffer_state.height;
659
660 if (((struct r300_rs_state*)r300->rs_state.state)->rs.scissor) {
661 minx = MAX2(minx, scissor->minx);
662 miny = MAX2(miny, scissor->miny);
663 maxx = MIN2(maxx, scissor->maxx);
664 maxy = MIN2(maxy, scissor->maxy);
665 }
666
667 if (r300screen->caps->is_r500) {
668 top_left =
669 (minx << R300_SCISSORS_X_SHIFT) |
670 (miny << R300_SCISSORS_Y_SHIFT);
671 bottom_right =
672 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
673 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
674 } else {
675 /* Offset of 1440 in non-R500 chipsets. */
676 top_left =
677 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
678 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
679 bottom_right =
680 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
681 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
682 }
683
684 BEGIN_CS(3);
685 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
686 OUT_CS(top_left);
687 OUT_CS(bottom_right);
688 END_CS;
689 }
690
691 void r300_emit_texture(struct r300_context* r300,
692 struct r300_sampler_state* sampler,
693 struct r300_texture* tex,
694 unsigned offset)
695 {
696 uint32_t filter0 = sampler->filter0;
697 uint32_t format0 = tex->state.format0;
698 unsigned min_level, max_level;
699 CS_LOCALS(r300);
700
701 /* to emulate 1D textures through 2D ones correctly */
702 if (tex->tex.target == PIPE_TEXTURE_1D) {
703 filter0 &= ~R300_TX_WRAP_T_MASK;
704 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
705 }
706
707 /* determine min/max levels */
708 /* the MAX_MIP level is the largest (finest) one */
709 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
710 min_level = MIN2(sampler->min_lod, max_level);
711 format0 |= R300_TX_NUM_LEVELS(max_level);
712 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
713
714 BEGIN_CS(16);
715 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
716 (offset << 28));
717 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
718 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
719
720 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
721 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
722 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
723 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
724 OUT_CS_RELOC(tex->buffer,
725 R300_TXO_MACRO_TILE(tex->macrotile) |
726 R300_TXO_MICRO_TILE(tex->microtile),
727 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
728 END_CS;
729 }
730
731 static boolean r300_validate_aos(struct r300_context *r300)
732 {
733 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
734 struct pipe_vertex_element *velem = r300->vertex_element;
735 int i;
736
737 /* Check if formats and strides are aligned to the size of DWORD. */
738 for (i = 0; i < r300->vertex_element_count; i++) {
739 if (vbuf[velem[i].vertex_buffer_index].stride % 4 != 0 ||
740 util_format_get_blocksize(velem[i].src_format) % 4 != 0) {
741 return FALSE;
742 }
743 }
744 return TRUE;
745 }
746
747 void r300_emit_aos(struct r300_context* r300, unsigned offset)
748 {
749 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
750 struct pipe_vertex_element *velem = r300->vertex_element;
751 int i;
752 unsigned size1, size2, aos_count = r300->vertex_element_count;
753 unsigned packet_size = (aos_count * 3 + 1) / 2;
754 CS_LOCALS(r300);
755
756 /* XXX Move this checking to a more approriate place. */
757 if (!r300_validate_aos(r300)) {
758 /* XXX We should fallback using Draw. */
759 assert(0);
760 }
761
762 BEGIN_CS(2 + packet_size + aos_count * 2);
763 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
764 OUT_CS(aos_count);
765
766 for (i = 0; i < aos_count - 1; i += 2) {
767 vb1 = &vbuf[velem[i].vertex_buffer_index];
768 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
769 size1 = util_format_get_blocksize(velem[i].src_format);
770 size2 = util_format_get_blocksize(velem[i+1].src_format);
771
772 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
773 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
774 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
775 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
776 }
777
778 if (aos_count & 1) {
779 vb1 = &vbuf[velem[i].vertex_buffer_index];
780 size1 = util_format_get_blocksize(velem[i].src_format);
781
782 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
783 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
784 }
785
786 for (i = 0; i < aos_count; i++) {
787 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
788 RADEON_GEM_DOMAIN_GTT, 0, 0);
789 }
790 END_CS;
791 }
792
793 #if 0
794 void r300_emit_draw_packet(struct r300_context* r300)
795 {
796 CS_LOCALS(r300);
797
798 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
799 "vertex size %d\n", r300->vbo,
800 r300->vertex_info->vinfo.size);
801 /* Set the pointer to our vertex buffer. The emitted values are this:
802 * PACKET3 [3D_LOAD_VBPNTR]
803 * COUNT [1]
804 * FORMAT [size | stride << 8]
805 * OFFSET [offset into BO]
806 * VBPNTR [relocated BO]
807 */
808 BEGIN_CS(7);
809 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
810 OUT_CS(1);
811 OUT_CS(r300->vertex_info->vinfo.size |
812 (r300->vertex_info->vinfo.size << 8));
813 OUT_CS(r300->vbo_offset);
814 OUT_CS_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
815 END_CS;
816 }
817 #endif
818
819 void r300_emit_vertex_format_state(struct r300_context* r300)
820 {
821 int i;
822 CS_LOCALS(r300);
823
824 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
825
826 BEGIN_CS(26);
827 OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info->vinfo.size);
828
829 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
830 OUT_CS(r300->vertex_info->vinfo.hwfmt[0]);
831 OUT_CS(r300->vertex_info->vinfo.hwfmt[1]);
832 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
833 OUT_CS(r300->vertex_info->vinfo.hwfmt[2]);
834 OUT_CS(r300->vertex_info->vinfo.hwfmt[3]);
835 for (i = 0; i < 4; i++) {
836 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
837 r300->vertex_info->vinfo.hwfmt[i]);
838 }
839
840 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
841 for (i = 0; i < 8; i++) {
842 OUT_CS(r300->vertex_info->vap_prog_stream_cntl[i]);
843 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
844 r300->vertex_info->vap_prog_stream_cntl[i]);
845 }
846 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
847 for (i = 0; i < 8; i++) {
848 OUT_CS(r300->vertex_info->vap_prog_stream_cntl_ext[i]);
849 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
850 r300->vertex_info->vap_prog_stream_cntl_ext[i]);
851 }
852 END_CS;
853 }
854
855
856 void r300_emit_vertex_program_code(struct r300_context* r300,
857 struct r300_vertex_program_code* code)
858 {
859 int i;
860 struct r300_screen* r300screen = r300_screen(r300->context.screen);
861 unsigned instruction_count = code->length / 4;
862
863 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
864 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
865 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
866 int temp_count = MAX2(code->num_temporaries, 1);
867 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
868 vtx_mem_size / output_count, 10);
869 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
870
871 CS_LOCALS(r300);
872
873 if (!r300screen->caps->has_tcl) {
874 debug_printf("r300: Implementation error: emit_vertex_shader called,"
875 " but has_tcl is FALSE!\n");
876 return;
877 }
878
879 BEGIN_CS(9 + code->length);
880 /* R300_VAP_PVS_CODE_CNTL_0
881 * R300_VAP_PVS_CONST_CNTL
882 * R300_VAP_PVS_CODE_CNTL_1
883 * See the r5xx docs for instructions on how to use these. */
884 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
885 OUT_CS(R300_PVS_FIRST_INST(0) |
886 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
887 R300_PVS_LAST_INST(instruction_count - 1));
888 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
889 OUT_CS(instruction_count - 1);
890
891 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
892 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
893 for (i = 0; i < code->length; i++)
894 OUT_CS(code->body.d[i]);
895
896 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
897 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
898 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
899 R300_PVS_VF_MAX_VTX_NUM(12) |
900 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
901 END_CS;
902 }
903
904 void r300_emit_vertex_shader(struct r300_context* r300,
905 struct r300_vertex_shader* vs)
906 {
907 r300_emit_vertex_program_code(r300, &vs->code);
908 }
909
910 void r300_emit_vs_constant_buffer(struct r300_context* r300,
911 struct rc_constant_list* constants)
912 {
913 int i;
914 struct r300_screen* r300screen = r300_screen(r300->context.screen);
915 CS_LOCALS(r300);
916
917 if (!r300screen->caps->has_tcl) {
918 debug_printf("r300: Implementation error: emit_vertex_shader called,"
919 " but has_tcl is FALSE!\n");
920 return;
921 }
922
923 if (constants->Count == 0)
924 return;
925
926 BEGIN_CS(constants->Count * 4 + 3);
927 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
928 (r300screen->caps->is_r500 ?
929 R500_PVS_CONST_START : R300_PVS_CONST_START));
930 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
931 for (i = 0; i < constants->Count; i++) {
932 const float * data = get_shader_constant(r300,
933 &constants->Constants[i],
934 &r300->shader_constants[PIPE_SHADER_VERTEX]);
935 OUT_CS_32F(data[0]);
936 OUT_CS_32F(data[1]);
937 OUT_CS_32F(data[2]);
938 OUT_CS_32F(data[3]);
939 }
940 END_CS;
941 }
942
943 void r300_emit_viewport_state(struct r300_context* r300, void* state)
944 {
945 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
946 CS_LOCALS(r300);
947
948 if (r300->tcl_bypass) {
949 BEGIN_CS(2);
950 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
951 END_CS;
952 } else {
953 BEGIN_CS(9);
954 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
955 OUT_CS_32F(viewport->xscale);
956 OUT_CS_32F(viewport->xoffset);
957 OUT_CS_32F(viewport->yscale);
958 OUT_CS_32F(viewport->yoffset);
959 OUT_CS_32F(viewport->zscale);
960 OUT_CS_32F(viewport->zoffset);
961 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
962 END_CS;
963 }
964 }
965
966 void r300_emit_texture_count(struct r300_context* r300)
967 {
968 uint32_t tx_enable = 0;
969 int i;
970 CS_LOCALS(r300);
971
972 /* Notice that texture_count and sampler_count are just sizes
973 * of the respective arrays. We still have to check for the individual
974 * elements. */
975 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
976 if (r300->textures[i]) {
977 tx_enable |= 1 << i;
978 }
979 }
980
981 BEGIN_CS(2);
982 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
983 END_CS;
984
985 }
986
987 void r300_emit_ztop_state(struct r300_context* r300, void* state)
988 {
989 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
990 CS_LOCALS(r300);
991
992 BEGIN_CS(2);
993 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
994 END_CS;
995 }
996
997 void r300_flush_textures(struct r300_context* r300)
998 {
999 CS_LOCALS(r300);
1000
1001 BEGIN_CS(2);
1002 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1003 END_CS;
1004 }
1005
1006 static void r300_flush_pvs(struct r300_context* r300)
1007 {
1008 CS_LOCALS(r300);
1009
1010 BEGIN_CS(2);
1011 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
1012 END_CS;
1013 }
1014
1015 /* Emit all dirty state. */
1016 void r300_emit_dirty_state(struct r300_context* r300)
1017 {
1018 struct r300_screen* r300screen = r300_screen(r300->context.screen);
1019 struct r300_texture* tex;
1020 struct r300_atom* atom;
1021 int i, dirty_tex = 0;
1022 boolean invalid = FALSE;
1023
1024 /* Check size of CS. */
1025 /* Make sure we have at least 8*1024 spare dwords. */
1026 /* XXX It would be nice to know the number of dwords we really need to
1027 * XXX emit. */
1028 if (!r300->winsys->check_cs(r300->winsys, 8*1024)) {
1029 r300->context.flush(&r300->context, 0, NULL);
1030 }
1031
1032 if (!(r300->dirty_state)) {
1033 return;
1034 }
1035
1036 /* Clean out BOs. */
1037 r300->winsys->reset_bos(r300->winsys);
1038
1039 validate:
1040 /* Color buffers... */
1041 for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
1042 tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
1043 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1044 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1045 0, RADEON_GEM_DOMAIN_VRAM)) {
1046 r300->context.flush(&r300->context, 0, NULL);
1047 goto validate;
1048 }
1049 }
1050 /* ...depth buffer... */
1051 if (r300->framebuffer_state.zsbuf) {
1052 tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
1053 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1054 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1055 0, RADEON_GEM_DOMAIN_VRAM)) {
1056 r300->context.flush(&r300->context, 0, NULL);
1057 goto validate;
1058 }
1059 }
1060 /* ...textures... */
1061 for (i = 0; i < r300->texture_count; i++) {
1062 tex = r300->textures[i];
1063 if (!tex)
1064 continue;
1065 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1066 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1067 r300->context.flush(&r300->context, 0, NULL);
1068 goto validate;
1069 }
1070 }
1071 /* ...occlusion query buffer... */
1072 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1073 0, RADEON_GEM_DOMAIN_GTT)) {
1074 r300->context.flush(&r300->context, 0, NULL);
1075 goto validate;
1076 }
1077 /* ...and vertex buffer. */
1078 if (r300->vbo) {
1079 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1080 RADEON_GEM_DOMAIN_GTT, 0)) {
1081 r300->context.flush(&r300->context, 0, NULL);
1082 goto validate;
1083 }
1084 } else {
1085 /* debug_printf("No VBO while emitting dirty state!\n"); */
1086 }
1087 if (!r300->winsys->validate(r300->winsys)) {
1088 r300->context.flush(&r300->context, 0, NULL);
1089 if (invalid) {
1090 /* Well, hell. */
1091 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1092 exit(1);
1093 }
1094 invalid = TRUE;
1095 goto validate;
1096 }
1097
1098 if (r300->dirty_state & R300_NEW_QUERY) {
1099 r300_emit_query_start(r300);
1100 r300->dirty_state &= ~R300_NEW_QUERY;
1101 }
1102
1103 foreach(atom, &r300->atom_list) {
1104 if (atom->dirty || atom->always_dirty) {
1105 atom->emit(r300, atom->state);
1106 atom->dirty = FALSE;
1107 }
1108 }
1109
1110 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1111 r300_emit_fragment_depth_config(r300, r300->fs);
1112 if (r300screen->caps->is_r500) {
1113 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1114 } else {
1115 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1116 }
1117 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1118 }
1119
1120 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1121 if (r300screen->caps->is_r500) {
1122 r500_emit_fs_constant_buffer(r300,
1123 &r300->fs->shader->code.constants);
1124 } else {
1125 r300_emit_fs_constant_buffer(r300,
1126 &r300->fs->shader->code.constants);
1127 }
1128 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1129 }
1130
1131 if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
1132 r300_emit_fb_state(r300, &r300->framebuffer_state);
1133 r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
1134 }
1135
1136 if (r300->dirty_state & R300_NEW_RS_BLOCK) {
1137 r300_emit_rs_block_state(r300, r300->rs_block);
1138 r300->dirty_state &= ~R300_NEW_RS_BLOCK;
1139 }
1140
1141 /* Samplers and textures are tracked separately but emitted together. */
1142 if (r300->dirty_state &
1143 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1144 r300_emit_texture_count(r300);
1145
1146 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1147 if (r300->dirty_state &
1148 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1149 if (r300->textures[i])
1150 r300_emit_texture(r300,
1151 r300->sampler_states[i],
1152 r300->textures[i],
1153 i);
1154 r300->dirty_state &=
1155 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1156 dirty_tex++;
1157 }
1158 }
1159 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1160 }
1161
1162 if (dirty_tex) {
1163 r300_flush_textures(r300);
1164 }
1165
1166 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
1167 r300_emit_vertex_format_state(r300);
1168 r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
1169 }
1170
1171 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1172 r300_flush_pvs(r300);
1173 }
1174
1175 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1176 r300_emit_vertex_shader(r300, r300->vs);
1177 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1178 }
1179
1180 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1181 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1182 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1183 }
1184
1185 /* XXX
1186 assert(r300->dirty_state == 0);
1187 */
1188
1189 /* Finally, emit the VBO. */
1190 /* r300_emit_vertex_buffer(r300); */
1191
1192 r300->dirty_hw++;
1193 }