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[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28
29 #include "r300_context.h"
30 #include "r300_cs.h"
31 #include "r300_emit.h"
32 #include "r300_fs.h"
33 #include "r300_screen.h"
34 #include "r300_state_derived.h"
35 #include "r300_state_inlines.h"
36 #include "r300_texture.h"
37 #include "r300_vs.h"
38
39 void r300_emit_blend_state(struct r300_context* r300,
40 struct r300_blend_state* blend)
41 {
42 CS_LOCALS(r300);
43 BEGIN_CS(8);
44 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
45 if (r300->framebuffer_state.nr_cbufs) {
46 OUT_CS(blend->blend_control);
47 OUT_CS(blend->alpha_blend_control);
48 OUT_CS(blend->color_channel_mask);
49 } else {
50 OUT_CS(0);
51 OUT_CS(0);
52 OUT_CS(0);
53 /* XXX also disable fastfill here once it's supported */
54 }
55 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
56 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
57 END_CS;
58 }
59
60 void r300_emit_blend_color_state(struct r300_context* r300,
61 struct r300_blend_color_state* bc)
62 {
63 struct r300_screen* r300screen = r300_screen(r300->context.screen);
64 CS_LOCALS(r300);
65
66 if (r300screen->caps->is_r500) {
67 BEGIN_CS(3);
68 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
69 OUT_CS(bc->blend_color_red_alpha);
70 OUT_CS(bc->blend_color_green_blue);
71 END_CS;
72 } else {
73 BEGIN_CS(2);
74 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
75 END_CS;
76 }
77 }
78
79 void r300_emit_clip_state(struct r300_context* r300,
80 struct pipe_clip_state* clip)
81 {
82 int i;
83 struct r300_screen* r300screen = r300_screen(r300->context.screen);
84 CS_LOCALS(r300);
85
86 if (r300screen->caps->has_tcl) {
87 BEGIN_CS(5 + (6 * 4));
88 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
89 (r300screen->caps->is_r500 ?
90 R500_PVS_UCP_START : R300_PVS_UCP_START));
91 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
92 for (i = 0; i < 6; i++) {
93 OUT_CS_32F(clip->ucp[i][0]);
94 OUT_CS_32F(clip->ucp[i][1]);
95 OUT_CS_32F(clip->ucp[i][2]);
96 OUT_CS_32F(clip->ucp[i][3]);
97 }
98 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
99 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
100 END_CS;
101 } else {
102 BEGIN_CS(2);
103 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
104 END_CS;
105 }
106
107 }
108
109 void r300_emit_dsa_state(struct r300_context* r300,
110 struct r300_dsa_state* dsa)
111 {
112 struct r300_screen* r300screen = r300_screen(r300->context.screen);
113 CS_LOCALS(r300);
114
115 BEGIN_CS(r300screen->caps->is_r500 ? 10 : 8);
116 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
117
118 /* not needed since we use the 8bit alpha ref */
119 /*if (r300screen->caps->is_r500) {
120 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
121 }*/
122
123 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
124 OUT_CS(dsa->z_buffer_control);
125 OUT_CS(dsa->z_stencil_control);
126 OUT_CS(dsa->stencil_ref_mask);
127 OUT_CS_REG(R300_ZB_ZTOP, r300->ztop_state.z_buffer_top);
128
129 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
130 if (r300screen->caps->is_r500) {
131 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
132 }
133 END_CS;
134 }
135
136 static const float * get_shader_constant(
137 struct r300_context * r300,
138 struct rc_constant * constant,
139 struct r300_constant_buffer * externals)
140 {
141 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
142 struct pipe_texture *tex;
143
144 switch(constant->Type) {
145 case RC_CONSTANT_EXTERNAL:
146 return externals->constants[constant->u.External];
147
148 case RC_CONSTANT_IMMEDIATE:
149 return constant->u.Immediate;
150
151 case RC_CONSTANT_STATE:
152 switch (constant->u.State[0]) {
153 /* Factor for converting rectangle coords to
154 * normalized coords. Should only show up on non-r500. */
155 case RC_STATE_R300_TEXRECT_FACTOR:
156 tex = &r300->textures[constant->u.State[1]]->tex;
157 vec[0] = 1.0 / tex->width0;
158 vec[1] = 1.0 / tex->height0;
159 break;
160
161 /* Texture compare-fail value. */
162 /* XXX Since Gallium doesn't support GL_ARB_shadow_ambient,
163 * this is always (0,0,0,0). */
164 case RC_STATE_SHADOW_AMBIENT:
165 vec[3] = 0;
166 break;
167
168 default:
169 debug_printf("r300: Implementation error: "
170 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
171 }
172 break;
173
174 default:
175 debug_printf("r300: Implementation error: "
176 "Unhandled constant type %d\n", constant->Type);
177 }
178
179 /* This should either be (0, 0, 0, 1), which should be a relatively safe
180 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
181 * state factors. */
182 return vec;
183 }
184
185 /* Convert a normal single-precision float into the 7.16 format
186 * used by the R300 fragment shader.
187 */
188 static uint32_t pack_float24(float f)
189 {
190 union {
191 float fl;
192 uint32_t u;
193 } u;
194 float mantissa;
195 int exponent;
196 uint32_t float24 = 0;
197
198 if (f == 0.0)
199 return 0;
200
201 u.fl = f;
202
203 mantissa = frexpf(f, &exponent);
204
205 /* Handle -ve */
206 if (mantissa < 0) {
207 float24 |= (1 << 23);
208 mantissa = mantissa * -1.0;
209 }
210 /* Handle exponent, bias of 63 */
211 exponent += 62;
212 float24 |= (exponent << 16);
213 /* Kill 7 LSB of mantissa */
214 float24 |= (u.u & 0x7FFFFF) >> 7;
215
216 return float24;
217 }
218
219 void r300_emit_fragment_program_code(struct r300_context* r300,
220 struct rX00_fragment_program_code* generic_code)
221 {
222 struct r300_fragment_program_code * code = &generic_code->code.r300;
223 int i;
224 CS_LOCALS(r300);
225
226 BEGIN_CS(15 +
227 code->alu.length * 4 +
228 (code->tex.length ? (1 + code->tex.length) : 0));
229
230 OUT_CS_REG(R300_US_CONFIG, code->config);
231 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
232 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
233
234 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
235 for(i = 0; i < 4; ++i)
236 OUT_CS(code->code_addr[i]);
237
238 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
239 for (i = 0; i < code->alu.length; i++)
240 OUT_CS(code->alu.inst[i].rgb_inst);
241
242 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
243 for (i = 0; i < code->alu.length; i++)
244 OUT_CS(code->alu.inst[i].rgb_addr);
245
246 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
247 for (i = 0; i < code->alu.length; i++)
248 OUT_CS(code->alu.inst[i].alpha_inst);
249
250 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
251 for (i = 0; i < code->alu.length; i++)
252 OUT_CS(code->alu.inst[i].alpha_addr);
253
254 if (code->tex.length) {
255 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
256 for(i = 0; i < code->tex.length; ++i)
257 OUT_CS(code->tex.inst[i]);
258 }
259
260 END_CS;
261 }
262
263 void r300_emit_fs_constant_buffer(struct r300_context* r300,
264 struct rc_constant_list* constants)
265 {
266 int i;
267 CS_LOCALS(r300);
268
269 if (constants->Count == 0)
270 return;
271
272 BEGIN_CS(constants->Count * 4 + 1);
273 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
274 for(i = 0; i < constants->Count; ++i) {
275 const float * data = get_shader_constant(r300,
276 &constants->Constants[i],
277 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
278 OUT_CS(pack_float24(data[0]));
279 OUT_CS(pack_float24(data[1]));
280 OUT_CS(pack_float24(data[2]));
281 OUT_CS(pack_float24(data[3]));
282 }
283 END_CS;
284 }
285
286 void r500_emit_fragment_program_code(struct r300_context* r300,
287 struct rX00_fragment_program_code* generic_code)
288 {
289 struct r500_fragment_program_code * code = &generic_code->code.r500;
290 int i;
291 CS_LOCALS(r300);
292
293 BEGIN_CS(13 +
294 ((code->inst_end + 1) * 6));
295 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
296 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
297 OUT_CS_REG(R500_US_CODE_RANGE,
298 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
299 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
300 OUT_CS_REG(R500_US_CODE_ADDR,
301 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
302
303 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
304 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
305 for (i = 0; i <= code->inst_end; i++) {
306 OUT_CS(code->inst[i].inst0);
307 OUT_CS(code->inst[i].inst1);
308 OUT_CS(code->inst[i].inst2);
309 OUT_CS(code->inst[i].inst3);
310 OUT_CS(code->inst[i].inst4);
311 OUT_CS(code->inst[i].inst5);
312 }
313
314 END_CS;
315 }
316
317 void r500_emit_fs_constant_buffer(struct r300_context* r300,
318 struct rc_constant_list* constants)
319 {
320 int i;
321 CS_LOCALS(r300);
322
323 if (constants->Count == 0)
324 return;
325
326 BEGIN_CS(constants->Count * 4 + 3);
327 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
328 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
329 for (i = 0; i < constants->Count; i++) {
330 const float * data = get_shader_constant(r300,
331 &constants->Constants[i],
332 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
333 OUT_CS_32F(data[0]);
334 OUT_CS_32F(data[1]);
335 OUT_CS_32F(data[2]);
336 OUT_CS_32F(data[3]);
337 }
338 END_CS;
339 }
340
341 void r300_emit_fb_state(struct r300_context* r300,
342 struct pipe_framebuffer_state* fb)
343 {
344 struct r300_texture* tex;
345 struct pipe_surface* surf;
346 int i;
347 CS_LOCALS(r300);
348
349 /* Shouldn't fail unless there is a bug in the state tracker. */
350 assert(fb->nr_cbufs <= 4);
351
352 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
353 (fb->zsbuf ? 10 : 0) + 6);
354
355 /* Flush and free renderbuffer caches. */
356 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
357 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
358 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
359 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
360 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
361 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
362
363 /* Set the number of colorbuffers. */
364 OUT_CS_REG(R300_RB3D_CCTL, R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
365
366 /* Set up colorbuffers. */
367 for (i = 0; i < fb->nr_cbufs; i++) {
368 surf = fb->cbufs[i];
369 tex = (struct r300_texture*)surf->texture;
370 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
371
372 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
373 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
374
375 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
376 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
377 r300_translate_colorformat(tex->tex.format), 0,
378 RADEON_GEM_DOMAIN_VRAM, 0);
379
380 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
381 r300_translate_out_fmt(surf->format));
382 }
383
384 /* Disable unused colorbuffers. */
385 for (; i < 4; i++) {
386 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
387 }
388
389 /* Set up a zbuffer. */
390 if (fb->zsbuf) {
391 surf = fb->zsbuf;
392 tex = (struct r300_texture*)surf->texture;
393 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
394
395 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
396 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
397
398 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
399
400 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
401 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level], 0,
402 RADEON_GEM_DOMAIN_VRAM, 0);
403 }
404
405 END_CS;
406 }
407
408 static void r300_emit_query_start(struct r300_context *r300)
409 {
410 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
411 struct r300_query *query = r300->query_current;
412 CS_LOCALS(r300);
413
414 if (!query)
415 return;
416
417 BEGIN_CS(4);
418 if (caps->family == CHIP_FAMILY_RV530) {
419 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
420 } else {
421 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
422 }
423 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
424 END_CS;
425 query->begin_emitted = TRUE;
426 }
427
428
429 static void r300_emit_query_finish(struct r300_context *r300,
430 struct r300_query *query)
431 {
432 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
433 CS_LOCALS(r300);
434
435 assert(caps->num_frag_pipes);
436
437 BEGIN_CS(6 * caps->num_frag_pipes + 2);
438 /* I'm not so sure I like this switch, but it's hard to be elegant
439 * when there's so many special cases...
440 *
441 * So here's the basic idea. For each pipe, enable writes to it only,
442 * then put out the relocation for ZPASS_ADDR, taking into account a
443 * 4-byte offset for each pipe. RV380 and older are special; they have
444 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
445 * so there's a chipset cap for that. */
446 switch (caps->num_frag_pipes) {
447 case 4:
448 /* pipe 3 only */
449 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
450 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
451 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
452 0, RADEON_GEM_DOMAIN_GTT, 0);
453 case 3:
454 /* pipe 2 only */
455 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
456 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
457 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
458 0, RADEON_GEM_DOMAIN_GTT, 0);
459 case 2:
460 /* pipe 1 only */
461 /* As mentioned above, accomodate RV380 and older. */
462 OUT_CS_REG(R300_SU_REG_DEST,
463 1 << (caps->high_second_pipe ? 3 : 1));
464 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
465 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
466 0, RADEON_GEM_DOMAIN_GTT, 0);
467 case 1:
468 /* pipe 0 only */
469 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
470 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
471 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
472 0, RADEON_GEM_DOMAIN_GTT, 0);
473 break;
474 default:
475 debug_printf("r300: Implementation error: Chipset reports %d"
476 " pixel pipes!\n", caps->num_frag_pipes);
477 assert(0);
478 }
479
480 /* And, finally, reset it to normal... */
481 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
482 END_CS;
483 }
484
485 static void rv530_emit_query_single(struct r300_context *r300,
486 struct r300_query *query)
487 {
488 CS_LOCALS(r300);
489
490 BEGIN_CS(8);
491 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
492 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
493 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
494 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
495 END_CS;
496 }
497
498 static void rv530_emit_query_double(struct r300_context *r300,
499 struct r300_query *query)
500 {
501 CS_LOCALS(r300);
502
503 BEGIN_CS(14);
504 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
505 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
506 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
507 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
508 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
509 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
510 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
511 END_CS;
512 }
513
514 void r300_emit_query_end(struct r300_context* r300)
515 {
516 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
517 struct r300_query *query = r300->query_current;
518
519 if (!query)
520 return;
521
522 if (query->begin_emitted == FALSE)
523 return;
524
525 if (caps->family == CHIP_FAMILY_RV530) {
526 if (caps->num_z_pipes == 2)
527 rv530_emit_query_double(r300, query);
528 else
529 rv530_emit_query_single(r300, query);
530 } else
531 r300_emit_query_finish(r300, query);
532 }
533
534 void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs)
535 {
536 CS_LOCALS(r300);
537
538 BEGIN_CS(22);
539 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
540 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
541 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
542 OUT_CS(rs->point_minmax);
543 OUT_CS(rs->line_control);
544 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
545 OUT_CS(rs->depth_scale_front);
546 OUT_CS(rs->depth_offset_front);
547 OUT_CS(rs->depth_scale_back);
548 OUT_CS(rs->depth_offset_back);
549 OUT_CS(rs->polygon_offset_enable);
550 OUT_CS(rs->cull_mode);
551 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
552 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
553 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
554 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
555 END_CS;
556 }
557
558 void r300_emit_rs_block_state(struct r300_context* r300,
559 struct r300_rs_block* rs)
560 {
561 int i;
562 struct r300_screen* r300screen = r300_screen(r300->context.screen);
563 CS_LOCALS(r300);
564
565 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
566
567 BEGIN_CS(21);
568 if (r300screen->caps->is_r500) {
569 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
570 } else {
571 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
572 }
573 for (i = 0; i < 8; i++) {
574 OUT_CS(rs->ip[i]);
575 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
576 }
577
578 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
579 OUT_CS(rs->count);
580 OUT_CS(rs->inst_count);
581
582 if (r300screen->caps->is_r500) {
583 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
584 } else {
585 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
586 }
587 for (i = 0; i < 8; i++) {
588 OUT_CS(rs->inst[i]);
589 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
590 }
591
592 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
593 rs->count, rs->inst_count);
594
595 END_CS;
596 }
597
598 static void r300_emit_scissor_regs(struct r300_context* r300,
599 struct r300_scissor_regs* scissor)
600 {
601 CS_LOCALS(r300);
602
603 BEGIN_CS(3);
604 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
605 OUT_CS(scissor->top_left);
606 OUT_CS(scissor->bottom_right);
607 END_CS;
608 }
609
610 void r300_emit_scissor_state(struct r300_context* r300,
611 struct r300_scissor_state* scissor)
612 {
613 if (r300->rs_state->rs.scissor) {
614 r300_emit_scissor_regs(r300, &scissor->scissor);
615 } else {
616 r300_emit_scissor_regs(r300, &scissor->framebuffer);
617 }
618 }
619
620 void r300_emit_texture(struct r300_context* r300,
621 struct r300_sampler_state* sampler,
622 struct r300_texture* tex,
623 unsigned offset)
624 {
625 uint32_t filter0 = sampler->filter0;
626 uint32_t format0 = tex->state.format0;
627 unsigned min_level, max_level;
628 CS_LOCALS(r300);
629
630 /* to emulate 1D textures through 2D ones correctly */
631 if (tex->tex.target == PIPE_TEXTURE_1D) {
632 filter0 &= ~R300_TX_WRAP_T_MASK;
633 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
634 }
635
636 /* determine min/max levels */
637 /* the MAX_MIP level is the largest (finest) one */
638 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
639 min_level = MIN2(sampler->min_lod, max_level);
640 format0 |= R300_TX_NUM_LEVELS(max_level);
641 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
642
643 BEGIN_CS(16);
644 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
645 (offset << 28));
646 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
647 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
648
649 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
650 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
651 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
652 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
653 OUT_CS_RELOC(tex->buffer, 0,
654 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
655 END_CS;
656 }
657
658 static boolean r300_validate_aos(struct r300_context *r300)
659 {
660 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
661 struct pipe_vertex_element *velem = r300->vertex_element;
662 int i;
663
664 /* Check if formats and strides are aligned to the size of DWORD. */
665 for (i = 0; i < r300->vertex_element_count; i++) {
666 if (vbuf[velem[i].vertex_buffer_index].stride % 4 != 0 ||
667 util_format_get_blocksize(velem[i].src_format) % 4 != 0) {
668 return FALSE;
669 }
670 }
671 return TRUE;
672 }
673
674 void r300_emit_aos(struct r300_context* r300, unsigned offset)
675 {
676 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
677 struct pipe_vertex_element *velem = r300->vertex_element;
678 int i;
679 unsigned size1, size2, aos_count = r300->vertex_element_count;
680 unsigned packet_size = (aos_count * 3 + 1) / 2;
681 CS_LOCALS(r300);
682
683 /* XXX Move this checking to a more approriate place. */
684 if (!r300_validate_aos(r300)) {
685 /* XXX We should fallback using Draw. */
686 assert(0);
687 }
688
689 BEGIN_CS(2 + packet_size + aos_count * 2);
690 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
691 OUT_CS(aos_count);
692
693 for (i = 0; i < aos_count - 1; i += 2) {
694 vb1 = &vbuf[velem[i].vertex_buffer_index];
695 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
696 size1 = util_format_get_blocksize(velem[i].src_format);
697 size2 = util_format_get_blocksize(velem[i+1].src_format);
698
699 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
700 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
701 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
702 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
703 }
704
705 if (aos_count & 1) {
706 vb1 = &vbuf[velem[i].vertex_buffer_index];
707 size1 = util_format_get_blocksize(velem[i].src_format);
708
709 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
710 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
711 }
712
713 for (i = 0; i < aos_count; i++) {
714 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
715 RADEON_GEM_DOMAIN_GTT, 0, 0);
716 }
717 END_CS;
718 }
719
720 #if 0
721 void r300_emit_draw_packet(struct r300_context* r300)
722 {
723 CS_LOCALS(r300);
724
725 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
726 "vertex size %d\n", r300->vbo,
727 r300->vertex_info->vinfo.size);
728 /* Set the pointer to our vertex buffer. The emitted values are this:
729 * PACKET3 [3D_LOAD_VBPNTR]
730 * COUNT [1]
731 * FORMAT [size | stride << 8]
732 * OFFSET [offset into BO]
733 * VBPNTR [relocated BO]
734 */
735 BEGIN_CS(7);
736 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
737 OUT_CS(1);
738 OUT_CS(r300->vertex_info->vinfo.size |
739 (r300->vertex_info->vinfo.size << 8));
740 OUT_CS(r300->vbo_offset);
741 OUT_CS_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
742 END_CS;
743 }
744 #endif
745
746 void r300_emit_vertex_format_state(struct r300_context* r300)
747 {
748 int i;
749 CS_LOCALS(r300);
750
751 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
752
753 BEGIN_CS(26);
754 OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info->vinfo.size);
755
756 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
757 OUT_CS(r300->vertex_info->vinfo.hwfmt[0]);
758 OUT_CS(r300->vertex_info->vinfo.hwfmt[1]);
759 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
760 OUT_CS(r300->vertex_info->vinfo.hwfmt[2]);
761 OUT_CS(r300->vertex_info->vinfo.hwfmt[3]);
762 for (i = 0; i < 4; i++) {
763 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
764 r300->vertex_info->vinfo.hwfmt[i]);
765 }
766
767 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
768 for (i = 0; i < 8; i++) {
769 OUT_CS(r300->vertex_info->vap_prog_stream_cntl[i]);
770 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
771 r300->vertex_info->vap_prog_stream_cntl[i]);
772 }
773 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
774 for (i = 0; i < 8; i++) {
775 OUT_CS(r300->vertex_info->vap_prog_stream_cntl_ext[i]);
776 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
777 r300->vertex_info->vap_prog_stream_cntl_ext[i]);
778 }
779 END_CS;
780 }
781
782
783 void r300_emit_vertex_program_code(struct r300_context* r300,
784 struct r300_vertex_program_code* code)
785 {
786 int i;
787 struct r300_screen* r300screen = r300_screen(r300->context.screen);
788 unsigned instruction_count = code->length / 4;
789
790 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
791 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
792 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
793 int temp_count = MAX2(code->num_temporaries, 1);
794 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
795 vtx_mem_size / output_count, 10);
796 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
797
798 CS_LOCALS(r300);
799
800 if (!r300screen->caps->has_tcl) {
801 debug_printf("r300: Implementation error: emit_vertex_shader called,"
802 " but has_tcl is FALSE!\n");
803 return;
804 }
805
806 BEGIN_CS(9 + code->length);
807 /* R300_VAP_PVS_CODE_CNTL_0
808 * R300_VAP_PVS_CONST_CNTL
809 * R300_VAP_PVS_CODE_CNTL_1
810 * See the r5xx docs for instructions on how to use these. */
811 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
812 OUT_CS(R300_PVS_FIRST_INST(0) |
813 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
814 R300_PVS_LAST_INST(instruction_count - 1));
815 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
816 OUT_CS(instruction_count - 1);
817
818 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
819 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
820 for (i = 0; i < code->length; i++)
821 OUT_CS(code->body.d[i]);
822
823 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
824 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
825 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
826 R300_PVS_VF_MAX_VTX_NUM(12) |
827 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
828 END_CS;
829 }
830
831 void r300_emit_vertex_shader(struct r300_context* r300,
832 struct r300_vertex_shader* vs)
833 {
834 r300_emit_vertex_program_code(r300, &vs->code);
835 }
836
837 void r300_emit_vs_constant_buffer(struct r300_context* r300,
838 struct rc_constant_list* constants)
839 {
840 int i;
841 struct r300_screen* r300screen = r300_screen(r300->context.screen);
842 CS_LOCALS(r300);
843
844 if (!r300screen->caps->has_tcl) {
845 debug_printf("r300: Implementation error: emit_vertex_shader called,"
846 " but has_tcl is FALSE!\n");
847 return;
848 }
849
850 if (constants->Count == 0)
851 return;
852
853 BEGIN_CS(constants->Count * 4 + 3);
854 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
855 (r300screen->caps->is_r500 ?
856 R500_PVS_CONST_START : R300_PVS_CONST_START));
857 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
858 for (i = 0; i < constants->Count; i++) {
859 const float * data = get_shader_constant(r300,
860 &constants->Constants[i],
861 &r300->shader_constants[PIPE_SHADER_VERTEX]);
862 OUT_CS_32F(data[0]);
863 OUT_CS_32F(data[1]);
864 OUT_CS_32F(data[2]);
865 OUT_CS_32F(data[3]);
866 }
867 END_CS;
868 }
869
870 void r300_emit_viewport_state(struct r300_context* r300,
871 struct r300_viewport_state* viewport)
872 {
873 CS_LOCALS(r300);
874
875 BEGIN_CS(9);
876 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
877 OUT_CS_32F(viewport->xscale);
878 OUT_CS_32F(viewport->xoffset);
879 OUT_CS_32F(viewport->yscale);
880 OUT_CS_32F(viewport->yoffset);
881 OUT_CS_32F(viewport->zscale);
882 OUT_CS_32F(viewport->zoffset);
883
884 if (r300->rs_state->enable_vte) {
885 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
886 } else {
887 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
888 }
889 END_CS;
890 }
891
892 void r300_emit_texture_count(struct r300_context* r300)
893 {
894 uint32_t tx_enable = 0;
895 int i;
896 CS_LOCALS(r300);
897
898 /* Notice that texture_count and sampler_count are just sizes
899 * of the respective arrays. We still have to check for the individual
900 * elements. */
901 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
902 if (r300->textures[i]) {
903 tx_enable |= 1 << i;
904 }
905 }
906
907 BEGIN_CS(2);
908 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
909 END_CS;
910
911 }
912
913 void r300_flush_textures(struct r300_context* r300)
914 {
915 CS_LOCALS(r300);
916
917 BEGIN_CS(2);
918 OUT_CS_REG(R300_TX_INVALTAGS, 0);
919 END_CS;
920 }
921
922 static void r300_flush_pvs(struct r300_context* r300)
923 {
924 CS_LOCALS(r300);
925
926 BEGIN_CS(2);
927 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
928 END_CS;
929 }
930
931 /* Emit all dirty state. */
932 void r300_emit_dirty_state(struct r300_context* r300)
933 {
934 struct r300_screen* r300screen = r300_screen(r300->context.screen);
935 struct r300_texture* tex;
936 int i, dirty_tex = 0;
937 boolean invalid = FALSE;
938
939 if (!(r300->dirty_state)) {
940 return;
941 }
942
943 /* Check size of CS. */
944 /* Make sure we have at least 8*1024 spare dwords. */
945 /* XXX It would be nice to know the number of dwords we really need to
946 * XXX emit. */
947 if (!r300->winsys->check_cs(r300->winsys, 8*1024)) {
948 r300->context.flush(&r300->context, 0, NULL);
949 }
950
951 /* Clean out BOs. */
952 r300->winsys->reset_bos(r300->winsys);
953
954 validate:
955 /* Color buffers... */
956 for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
957 tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
958 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
959 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
960 0, RADEON_GEM_DOMAIN_VRAM)) {
961 r300->context.flush(&r300->context, 0, NULL);
962 goto validate;
963 }
964 }
965 /* ...depth buffer... */
966 if (r300->framebuffer_state.zsbuf) {
967 tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
968 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
969 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
970 0, RADEON_GEM_DOMAIN_VRAM)) {
971 r300->context.flush(&r300->context, 0, NULL);
972 goto validate;
973 }
974 }
975 /* ...textures... */
976 for (i = 0; i < r300->texture_count; i++) {
977 tex = r300->textures[i];
978 if (!tex)
979 continue;
980 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
981 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
982 r300->context.flush(&r300->context, 0, NULL);
983 goto validate;
984 }
985 }
986 /* ...occlusion query buffer... */
987 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
988 0, RADEON_GEM_DOMAIN_GTT)) {
989 r300->context.flush(&r300->context, 0, NULL);
990 goto validate;
991 }
992 /* ...and vertex buffer. */
993 if (r300->vbo) {
994 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
995 RADEON_GEM_DOMAIN_GTT, 0)) {
996 r300->context.flush(&r300->context, 0, NULL);
997 goto validate;
998 }
999 } else {
1000 /* debug_printf("No VBO while emitting dirty state!\n"); */
1001 }
1002 if (!r300->winsys->validate(r300->winsys)) {
1003 r300->context.flush(&r300->context, 0, NULL);
1004 if (invalid) {
1005 /* Well, hell. */
1006 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1007 exit(1);
1008 }
1009 invalid = TRUE;
1010 goto validate;
1011 }
1012
1013 if (r300->dirty_state & R300_NEW_QUERY) {
1014 r300_emit_query_start(r300);
1015 r300->dirty_state &= ~R300_NEW_QUERY;
1016 }
1017
1018 if (r300->dirty_state & R300_NEW_BLEND) {
1019 r300_emit_blend_state(r300, r300->blend_state);
1020 r300->dirty_state &= ~R300_NEW_BLEND;
1021 }
1022
1023 if (r300->dirty_state & R300_NEW_BLEND_COLOR) {
1024 r300_emit_blend_color_state(r300, r300->blend_color_state);
1025 r300->dirty_state &= ~R300_NEW_BLEND_COLOR;
1026 }
1027
1028 if (r300->dirty_state & R300_NEW_CLIP) {
1029 r300_emit_clip_state(r300, &r300->clip_state);
1030 r300->dirty_state &= ~R300_NEW_CLIP;
1031 }
1032
1033 if (r300->dirty_state & R300_NEW_DSA) {
1034 r300_emit_dsa_state(r300, r300->dsa_state);
1035 r300->dirty_state &= ~R300_NEW_DSA;
1036 }
1037
1038 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1039 if (r300screen->caps->is_r500) {
1040 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1041 } else {
1042 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1043 }
1044 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1045 }
1046
1047 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1048 if (r300screen->caps->is_r500) {
1049 r500_emit_fs_constant_buffer(r300,
1050 &r300->fs->shader->code.constants);
1051 } else {
1052 r300_emit_fs_constant_buffer(r300,
1053 &r300->fs->shader->code.constants);
1054 }
1055 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1056 }
1057
1058 if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
1059 r300_emit_fb_state(r300, &r300->framebuffer_state);
1060 r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
1061 }
1062
1063 if (r300->dirty_state & R300_NEW_RASTERIZER) {
1064 r300_emit_rs_state(r300, r300->rs_state);
1065 r300->dirty_state &= ~R300_NEW_RASTERIZER;
1066 }
1067
1068 if (r300->dirty_state & R300_NEW_RS_BLOCK) {
1069 r300_emit_rs_block_state(r300, r300->rs_block);
1070 r300->dirty_state &= ~R300_NEW_RS_BLOCK;
1071 }
1072
1073 if (r300->dirty_state & R300_NEW_SCISSOR) {
1074 r300_emit_scissor_state(r300, r300->scissor_state);
1075 r300->dirty_state &= ~R300_NEW_SCISSOR;
1076 }
1077
1078 /* Samplers and textures are tracked separately but emitted together. */
1079 if (r300->dirty_state &
1080 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1081 r300_emit_texture_count(r300);
1082
1083 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1084 if (r300->dirty_state &
1085 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1086 if (r300->textures[i])
1087 r300_emit_texture(r300,
1088 r300->sampler_states[i],
1089 r300->textures[i],
1090 i);
1091 r300->dirty_state &=
1092 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1093 dirty_tex++;
1094 }
1095 }
1096 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1097 }
1098
1099 if (r300->dirty_state & R300_NEW_VIEWPORT) {
1100 r300_emit_viewport_state(r300, r300->viewport_state);
1101 r300->dirty_state &= ~R300_NEW_VIEWPORT;
1102 }
1103
1104 if (dirty_tex) {
1105 r300_flush_textures(r300);
1106 }
1107
1108 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
1109 r300_emit_vertex_format_state(r300);
1110 r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
1111 }
1112
1113 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1114 r300_flush_pvs(r300);
1115 }
1116
1117 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1118 r300_emit_vertex_shader(r300, r300->vs);
1119 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1120 }
1121
1122 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1123 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1124 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1125 }
1126
1127 /* XXX
1128 assert(r300->dirty_state == 0);
1129 */
1130
1131 /* Finally, emit the VBO. */
1132 /* r300_emit_vertex_buffer(r300); */
1133
1134 r300->dirty_hw++;
1135 }