2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29 #include "util/u_simple_list.h"
31 #include "r300_context.h"
33 #include "r300_emit.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
39 void r300_emit_blend_state(struct r300_context
* r300
,
40 unsigned size
, void* state
)
42 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
43 struct pipe_framebuffer_state
* fb
=
44 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
48 WRITE_CS_TABLE(blend
->cb
, size
);
50 WRITE_CS_TABLE(blend
->cb_no_readwrite
, size
);
54 void r300_emit_blend_color_state(struct r300_context
* r300
,
55 unsigned size
, void* state
)
57 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
60 WRITE_CS_TABLE(bc
->cb
, size
);
63 void r300_emit_clip_state(struct r300_context
* r300
,
64 unsigned size
, void* state
)
66 struct r300_clip_state
* clip
= (struct r300_clip_state
*)state
;
69 WRITE_CS_TABLE(clip
->cb
, size
);
72 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
74 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
75 struct pipe_framebuffer_state
* fb
=
76 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
80 WRITE_CS_TABLE(&dsa
->cb_begin
, size
);
82 WRITE_CS_TABLE(dsa
->cb_no_readwrite
, size
);
86 static const float * get_rc_constant_state(
87 struct r300_context
* r300
,
88 struct rc_constant
* constant
)
90 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
91 static float vec
[4] = { 0.0, 0.0, 0.0, 1.0 };
92 struct pipe_resource
*tex
;
94 assert(constant
->Type
== RC_CONSTANT_STATE
);
96 switch (constant
->u
.State
[0]) {
97 /* Factor for converting rectangle coords to
98 * normalized coords. Should only show up on non-r500. */
99 case RC_STATE_R300_TEXRECT_FACTOR
:
100 tex
= texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
;
101 vec
[0] = 1.0 / tex
->width0
;
102 vec
[1] = 1.0 / tex
->height0
;
105 case RC_STATE_R300_VIEWPORT_SCALE
:
106 vec
[0] = r300
->viewport
.scale
[0];
107 vec
[1] = r300
->viewport
.scale
[1];
108 vec
[2] = r300
->viewport
.scale
[2];
111 case RC_STATE_R300_VIEWPORT_OFFSET
:
112 vec
[0] = r300
->viewport
.translate
[0];
113 vec
[1] = r300
->viewport
.translate
[1];
114 vec
[2] = r300
->viewport
.translate
[2];
118 fprintf(stderr
, "r300: Implementation error: "
119 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
122 /* This should either be (0, 0, 0, 1), which should be a relatively safe
123 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
128 /* Convert a normal single-precision float into the 7.16 format
129 * used by the R300 fragment shader.
131 uint32_t pack_float24(float f
)
139 uint32_t float24
= 0;
146 mantissa
= frexpf(f
, &exponent
);
150 float24
|= (1 << 23);
151 mantissa
= mantissa
* -1.0;
153 /* Handle exponent, bias of 63 */
155 float24
|= (exponent
<< 16);
156 /* Kill 7 LSB of mantissa */
157 float24
|= (u
.u
& 0x7FFFFF) >> 7;
162 void r300_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
164 struct r300_fragment_shader
*fs
= r300_fs(r300
);
167 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
170 void r300_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
172 struct r300_fragment_shader
*fs
= r300_fs(r300
);
173 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
174 unsigned count
= fs
->shader
->externals_count
;
182 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, count
* 4);
183 if (buf
->remap_table
){
184 for (i
= 0; i
< count
; i
++) {
185 float *data
= (float*)&buf
->ptr
[buf
->remap_table
[i
]*4];
186 for (j
= 0; j
< 4; j
++)
187 OUT_CS(pack_float24(data
[j
]));
190 for (i
= 0; i
< count
; i
++)
191 for (j
= 0; j
< 4; j
++)
192 OUT_CS(pack_float24(*(float*)&buf
->ptr
[i
*4+j
]));
198 void r300_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
200 struct r300_fragment_shader
*fs
= r300_fs(r300
);
201 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
203 unsigned count
= fs
->shader
->rc_state_count
;
204 unsigned first
= fs
->shader
->externals_count
;
205 unsigned end
= constants
->Count
;
213 for(i
= first
; i
< end
; ++i
) {
214 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
216 get_rc_constant_state(r300
, &constants
->Constants
[i
]);
218 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
219 for (j
= 0; j
< 4; j
++)
220 OUT_CS(pack_float24(data
[j
]));
226 void r500_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
228 struct r300_fragment_shader
*fs
= r300_fs(r300
);
231 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
234 void r500_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
236 struct r300_fragment_shader
*fs
= r300_fs(r300
);
237 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
238 unsigned count
= fs
->shader
->externals_count
;
245 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
246 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, count
* 4);
247 if (buf
->remap_table
){
248 for (unsigned i
= 0; i
< count
; i
++) {
249 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
250 OUT_CS_TABLE(data
, 4);
253 OUT_CS_TABLE(buf
->ptr
, count
* 4);
258 void r500_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
260 struct r300_fragment_shader
*fs
= r300_fs(r300
);
261 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
263 unsigned count
= fs
->shader
->rc_state_count
;
264 unsigned first
= fs
->shader
->externals_count
;
265 unsigned end
= constants
->Count
;
272 for(i
= first
; i
< end
; ++i
) {
273 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
275 get_rc_constant_state(r300
, &constants
->Constants
[i
]);
277 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
278 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
279 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
280 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
281 OUT_CS_TABLE(data
, 4);
287 void r300_emit_gpu_flush(struct r300_context
*r300
, unsigned size
, void *state
)
289 struct r300_gpu_flush
*gpuflush
= (struct r300_gpu_flush
*)state
;
290 struct pipe_framebuffer_state
* fb
=
291 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
292 uint32_t height
= fb
->height
;
293 uint32_t width
= fb
->width
;
296 if (r300
->cbzb_clear
) {
297 struct r300_surface
*surf
= r300_surface(fb
->cbufs
[0]);
299 height
= surf
->cbzb_height
;
300 width
= surf
->cbzb_width
;
306 * By writing to the SC registers, SC & US assert idle. */
307 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
308 if (r300
->screen
->caps
.is_r500
) {
310 OUT_CS(((width
- 1) << R300_SCISSORS_X_SHIFT
) |
311 ((height
- 1) << R300_SCISSORS_Y_SHIFT
));
313 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
314 (1440 << R300_SCISSORS_Y_SHIFT
));
315 OUT_CS(((width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
316 ((height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
319 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
320 OUT_CS_TABLE(gpuflush
->cb_flush_clean
, 6);
324 void r300_emit_aa_state(struct r300_context
*r300
, unsigned size
, void *state
)
326 struct r300_aa_state
*aa
= (struct r300_aa_state
*)state
;
330 OUT_CS_REG(R300_GB_AA_CONFIG
, aa
->aa_config
);
333 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET
, 1);
334 OUT_CS_RELOC(aa
->dest
->buffer
, aa
->dest
->offset
, 0, aa
->dest
->domain
);
336 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_PITCH
, 1);
337 OUT_CS_RELOC(aa
->dest
->buffer
, aa
->dest
->pitch
, 0, aa
->dest
->domain
);
340 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL
, aa
->aaresolve_ctl
);
344 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
346 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
347 struct r300_surface
* surf
;
349 boolean has_hyperz
= r300
->rws
->get_value(r300
->rws
, R300_CAN_HYPERZ
);
354 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
355 * what we usually want. */
356 if (r300
->screen
->caps
.is_r500
) {
357 OUT_CS_REG(R300_RB3D_CCTL
,
358 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
);
360 OUT_CS_REG(R300_RB3D_CCTL
, 0);
363 /* Set up colorbuffers. */
364 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
365 surf
= r300_surface(fb
->cbufs
[i
]);
367 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
368 OUT_CS_RELOC(surf
->buffer
, surf
->offset
, 0, surf
->domain
);
370 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
371 OUT_CS_RELOC(surf
->buffer
, surf
->pitch
, 0, surf
->domain
);
374 /* Set up the ZB part of the CBZB clear. */
375 if (r300
->cbzb_clear
) {
376 surf
= r300_surface(fb
->cbufs
[0]);
378 OUT_CS_REG(R300_ZB_FORMAT
, surf
->cbzb_format
);
380 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
381 OUT_CS_RELOC(surf
->buffer
, surf
->cbzb_midpoint_offset
, 0, surf
->domain
);
383 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
384 OUT_CS_RELOC(surf
->buffer
, surf
->cbzb_pitch
, 0, surf
->domain
);
387 "CBZB clearing cbuf %08x %08x\n", surf
->cbzb_format
,
390 /* Set up a zbuffer. */
391 else if (fb
->zsbuf
) {
392 surf
= r300_surface(fb
->zsbuf
);
394 OUT_CS_REG(R300_ZB_FORMAT
, surf
->format
);
396 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
397 OUT_CS_RELOC(surf
->buffer
, surf
->offset
, 0, surf
->domain
);
399 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
400 OUT_CS_RELOC(surf
->buffer
, surf
->pitch
, 0, surf
->domain
);
404 struct r300_texture
*tex
;
405 int level
= surf
->base
.level
;
406 tex
= r300_texture(surf
->base
.texture
);
408 surf_pitch
= surf
->pitch
& R300_DEPTHPITCH_MASK
;
410 if (r300
->screen
->caps
.hiz_ram
) {
411 if (tex
->hiz_mem
[level
]) {
412 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, tex
->hiz_mem
[level
]->ofs
<< 2);
413 OUT_CS_REG(R300_ZB_HIZ_PITCH
, surf_pitch
);
415 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, 0);
416 OUT_CS_REG(R300_ZB_HIZ_PITCH
, 0);
419 /* Z Mask RAM. (compressed zbuffer) */
420 if (tex
->zmask_mem
[level
]) {
421 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, tex
->zmask_mem
[level
]->ofs
<< 2);
422 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, surf_pitch
);
424 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, 0);
425 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, 0);
433 void r300_emit_hyperz_state(struct r300_context
*r300
,
434 unsigned size
, void *state
)
436 struct r300_hyperz_state
*z
= state
;
439 WRITE_CS_TABLE(&z
->cb_flush_begin
, size
);
441 WRITE_CS_TABLE(&z
->cb_begin
, size
- 2);
444 void r300_emit_hyperz_end(struct r300_context
*r300
)
446 struct r300_hyperz_state z
=
447 *(struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
451 z
.zb_depthclearvalue
= 0;
452 z
.sc_hyperz
= R300_SC_HYPERZ_ADJ_2
;
453 z
.gb_z_peq_config
= 0;
455 r300_emit_hyperz_state(r300
, r300
->hyperz_state
.size
, &z
);
458 void r300_emit_fb_state_pipelined(struct r300_context
*r300
,
459 unsigned size
, void *state
)
461 struct pipe_framebuffer_state
* fb
=
462 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
468 /* Colorbuffer format in the US block.
469 * (must be written after unpipelined regs) */
470 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0
, 4);
471 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
472 OUT_CS(r300_surface(fb
->cbufs
[i
])->format
);
475 OUT_CS(R300_US_OUT_FMT_UNUSED
);
478 /* Multisampling. Depends on framebuffer sample count.
479 * These are pipelined regs and as such cannot be moved
480 * to the AA state. */
481 if (r300
->rws
->get_value(r300
->rws
, R300_VID_DRM_2_3_0
)) {
482 unsigned mspos0
= 0x66666666;
483 unsigned mspos1
= 0x6666666;
485 if (fb
->nr_cbufs
&& fb
->cbufs
[0]->texture
->nr_samples
> 1) {
486 /* Subsample placement. These may not be optimal. */
487 switch (fb
->cbufs
[0]->texture
->nr_samples
) {
505 debug_printf("r300: Bad number of multisamples!\n");
509 OUT_CS_REG_SEQ(R300_GB_MSPOS0
, 2);
516 void r300_emit_query_start(struct r300_context
*r300
, unsigned size
, void*state
)
518 struct r300_query
*query
= r300
->query_current
;
525 if (r300
->screen
->caps
.family
== CHIP_FAMILY_RV530
) {
526 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
528 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
530 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
532 query
->begin_emitted
= TRUE
;
533 query
->flushed
= FALSE
;
536 static void r300_emit_query_end_frag_pipes(struct r300_context
*r300
,
537 struct r300_query
*query
)
539 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
540 struct r300_winsys_buffer
*buf
= r300
->query_current
->buffer
;
543 assert(caps
->num_frag_pipes
);
545 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
546 /* I'm not so sure I like this switch, but it's hard to be elegant
547 * when there's so many special cases...
549 * So here's the basic idea. For each pipe, enable writes to it only,
550 * then put out the relocation for ZPASS_ADDR, taking into account a
551 * 4-byte offset for each pipe. RV380 and older are special; they have
552 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
553 * so there's a chipset cap for that. */
554 switch (caps
->num_frag_pipes
) {
557 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
558 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
559 OUT_CS_RELOC(buf
, (query
->num_results
+ 3) * 4,
563 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
564 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
565 OUT_CS_RELOC(buf
, (query
->num_results
+ 2) * 4,
569 /* As mentioned above, accomodate RV380 and older. */
570 OUT_CS_REG(R300_SU_REG_DEST
,
571 1 << (caps
->high_second_pipe
? 3 : 1));
572 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
573 OUT_CS_RELOC(buf
, (query
->num_results
+ 1) * 4,
577 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
578 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
579 OUT_CS_RELOC(buf
, (query
->num_results
+ 0) * 4,
583 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
584 " pixel pipes!\n", caps
->num_frag_pipes
);
588 /* And, finally, reset it to normal... */
589 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
593 static void rv530_emit_query_end_single_z(struct r300_context
*r300
,
594 struct r300_query
*query
)
596 struct r300_winsys_buffer
*buf
= r300
->query_current
->buffer
;
600 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
601 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
602 OUT_CS_RELOC(buf
, query
->num_results
* 4, 0, query
->domain
);
603 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
607 static void rv530_emit_query_end_double_z(struct r300_context
*r300
,
608 struct r300_query
*query
)
610 struct r300_winsys_buffer
*buf
= r300
->query_current
->buffer
;
614 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
615 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
616 OUT_CS_RELOC(buf
, (query
->num_results
+ 0) * 4, 0, query
->domain
);
617 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
618 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
619 OUT_CS_RELOC(buf
, (query
->num_results
+ 1) * 4, 0, query
->domain
);
620 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
624 void r300_emit_query_end(struct r300_context
* r300
)
626 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
627 struct r300_query
*query
= r300
->query_current
;
632 if (query
->begin_emitted
== FALSE
)
635 if (caps
->family
== CHIP_FAMILY_RV530
) {
636 if (caps
->num_z_pipes
== 2)
637 rv530_emit_query_end_double_z(r300
, query
);
639 rv530_emit_query_end_single_z(r300
, query
);
641 r300_emit_query_end_frag_pipes(r300
, query
);
643 query
->begin_emitted
= FALSE
;
644 query
->num_results
+= query
->num_pipes
;
646 /* XXX grab all the results and reset the counter. */
647 if (query
->num_results
>= query
->buffer_size
/ 4 - 4) {
648 query
->num_results
= (query
->buffer_size
/ 4) / 2;
649 fprintf(stderr
, "r300: Rewinding OQBO...\n");
653 void r300_emit_invariant_state(struct r300_context
*r300
,
654 unsigned size
, void *state
)
657 WRITE_CS_TABLE(state
, size
);
660 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
662 struct r300_rs_state
* rs
= state
;
666 OUT_CS_TABLE(rs
->cb_main
, 25);
667 if (rs
->polygon_offset_enable
) {
668 if (r300
->zbuffer_bpp
== 16) {
669 OUT_CS_TABLE(rs
->cb_poly_offset_zb16
, 5);
671 OUT_CS_TABLE(rs
->cb_poly_offset_zb24
, 5);
677 void r300_emit_rs_block_state(struct r300_context
* r300
,
678 unsigned size
, void* state
)
680 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
682 /* It's the same for both INST and IP tables */
683 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
686 if (DBG_ON(r300
, DBG_RS_BLOCK
)) {
687 r500_dump_rs_block(rs
);
689 fprintf(stderr
, "r300: RS emit:\n");
691 for (i
= 0; i
< count
; i
++)
692 fprintf(stderr
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
694 for (i
= 0; i
< count
; i
++)
695 fprintf(stderr
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
697 fprintf(stderr
, " : count: 0x%08x inst_count: 0x%08x\n",
698 rs
->count
, rs
->inst_count
);
702 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
703 OUT_CS(rs
->vap_vtx_state_cntl
);
704 OUT_CS(rs
->vap_vsm_vtx_assm
);
705 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
706 OUT_CS(rs
->vap_out_vtx_fmt
[0]);
707 OUT_CS(rs
->vap_out_vtx_fmt
[1]);
709 if (r300
->screen
->caps
.is_r500
) {
710 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
712 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
714 OUT_CS_TABLE(rs
->ip
, count
);
716 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
718 OUT_CS(rs
->inst_count
);
720 if (r300
->screen
->caps
.is_r500
) {
721 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
723 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
725 OUT_CS_TABLE(rs
->inst
, count
);
729 void r300_emit_scissor_state(struct r300_context
* r300
,
730 unsigned size
, void* state
)
732 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
736 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
737 if (r300
->screen
->caps
.is_r500
) {
738 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
739 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
740 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
741 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
743 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
744 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
745 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
746 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
751 void r300_emit_textures_state(struct r300_context
*r300
,
752 unsigned size
, void *state
)
754 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
755 struct r300_texture_sampler_state
*texstate
;
756 struct r300_texture
*tex
;
761 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
763 for (i
= 0; i
< allstate
->count
; i
++) {
764 if ((1 << i
) & allstate
->tx_enable
) {
765 texstate
= &allstate
->regs
[i
];
766 tex
= r300_texture(allstate
->sampler_views
[i
]->base
.texture
);
768 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
769 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
770 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
771 texstate
->border_color
);
773 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
774 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
775 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
777 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
778 OUT_CS_TEX_RELOC(tex
, texstate
->format
.tile_config
, tex
->domain
,
785 void r300_emit_aos(struct r300_context
* r300
, int offset
, boolean indexed
)
787 struct pipe_vertex_buffer
*vb1
, *vb2
, *vbuf
= r300
->vertex_buffer
;
788 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
789 struct r300_buffer
*buf
;
791 unsigned *hw_format_size
= r300
->velems
->hw_format_size
;
792 unsigned size1
, size2
, aos_count
= r300
->velems
->count
;
793 unsigned packet_size
= (aos_count
* 3 + 1) / 2;
796 BEGIN_CS(2 + packet_size
+ aos_count
* 2);
797 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
798 OUT_CS(aos_count
| (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
800 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
801 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
802 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
803 size1
= hw_format_size
[i
];
804 size2
= hw_format_size
[i
+1];
806 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
807 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
808 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
809 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
813 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
814 size1
= hw_format_size
[i
];
816 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
817 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
820 for (i
= 0; i
< aos_count
; i
++) {
821 buf
= r300_buffer(vbuf
[velem
[i
].vertex_buffer_index
].buffer
);
822 OUT_CS_BUF_RELOC_NO_OFFSET(&buf
->b
.b
, buf
->domain
, 0);
827 void r300_emit_aos_swtcl(struct r300_context
*r300
, boolean indexed
)
831 DBG(r300
, DBG_SWTCL
, "r300: Preparing vertex buffer %p for render, "
832 "vertex size %d\n", r300
->vbo
,
833 r300
->vertex_info
.size
);
834 /* Set the pointer to our vertex buffer. The emitted values are this:
835 * PACKET3 [3D_LOAD_VBPNTR]
837 * FORMAT [size | stride << 8]
838 * OFFSET [offset into BO]
839 * VBPNTR [relocated BO]
842 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
843 OUT_CS(1 | (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
844 OUT_CS(r300
->vertex_info
.size
|
845 (r300
->vertex_info
.size
<< 8));
846 OUT_CS(r300
->vbo_offset
);
847 OUT_CS_BUF_RELOC(r300
->vbo
, 0, r300_buffer(r300
->vbo
)->domain
, 0);
851 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
852 unsigned size
, void* state
)
854 struct r300_vertex_stream_state
*streams
=
855 (struct r300_vertex_stream_state
*)state
;
859 if (DBG_ON(r300
, DBG_PSC
)) {
860 fprintf(stderr
, "r300: PSC emit:\n");
862 for (i
= 0; i
< streams
->count
; i
++) {
863 fprintf(stderr
, " : prog_stream_cntl%d: 0x%08x\n", i
,
864 streams
->vap_prog_stream_cntl
[i
]);
867 for (i
= 0; i
< streams
->count
; i
++) {
868 fprintf(stderr
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
869 streams
->vap_prog_stream_cntl_ext
[i
]);
874 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
875 OUT_CS_TABLE(streams
->vap_prog_stream_cntl
, streams
->count
);
876 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
877 OUT_CS_TABLE(streams
->vap_prog_stream_cntl_ext
, streams
->count
);
881 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
886 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
890 void r300_emit_vap_invariant_state(struct r300_context
*r300
,
891 unsigned size
, void *state
)
894 WRITE_CS_TABLE(state
, size
);
897 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
899 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
900 struct r300_vertex_program_code
* code
= &vs
->code
;
901 struct r300_screen
* r300screen
= r300
->screen
;
902 unsigned instruction_count
= code
->length
/ 4;
905 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
906 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
907 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
908 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
910 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
911 vtx_mem_size
/ output_count
, 10);
912 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 5);
914 unsigned imm_first
= vs
->externals_count
;
915 unsigned imm_end
= vs
->code
.constants
.Count
;
916 unsigned imm_count
= vs
->immediates_count
;
922 /* R300_VAP_PVS_CODE_CNTL_0
923 * R300_VAP_PVS_CONST_CNTL
924 * R300_VAP_PVS_CODE_CNTL_1
925 * See the r5xx docs for instructions on how to use these. */
926 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
927 OUT_CS(R300_PVS_FIRST_INST(0) |
928 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
929 R300_PVS_LAST_INST(instruction_count
- 1));
930 OUT_CS(R300_PVS_MAX_CONST_ADDR(code
->constants
.Count
- 1));
931 OUT_CS(instruction_count
- 1);
933 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
934 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
935 OUT_CS_TABLE(code
->body
.d
, code
->length
);
937 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
938 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
939 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
940 R300_PVS_VF_MAX_VTX_NUM(12) |
941 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
943 /* Emit immediates. */
945 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
946 (r300
->screen
->caps
.is_r500
?
947 R500_PVS_CONST_START
: R300_PVS_CONST_START
) +
949 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, imm_count
* 4);
950 for (i
= imm_first
; i
< imm_end
; i
++) {
951 const float *data
= vs
->code
.constants
.Constants
[i
].u
.Immediate
;
952 OUT_CS_TABLE(data
, 4);
956 /* Emit flow control instructions. */
957 if (code
->num_fc_ops
) {
959 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC
, code
->fc_ops
);
960 if (r300screen
->caps
.is_r500
) {
961 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0
, code
->num_fc_ops
* 2);
962 OUT_CS_TABLE(code
->fc_op_addrs
.r500
, code
->num_fc_ops
* 2);
964 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0
, code
->num_fc_ops
);
965 OUT_CS_TABLE(code
->fc_op_addrs
.r300
, code
->num_fc_ops
);
967 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
, code
->num_fc_ops
);
968 OUT_CS_TABLE(code
->fc_loop_index
, code
->num_fc_ops
);
974 void r300_emit_vs_constants(struct r300_context
* r300
,
975 unsigned size
, void *state
)
978 ((struct r300_vertex_shader
*)r300
->vs_state
.state
)->externals_count
;
979 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
987 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
988 (r300
->screen
->caps
.is_r500
?
989 R500_PVS_CONST_START
: R300_PVS_CONST_START
));
990 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, count
* 4);
991 if (buf
->remap_table
){
992 for (i
= 0; i
< count
; i
++) {
993 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
994 OUT_CS_TABLE(data
, 4);
997 OUT_CS_TABLE(buf
->ptr
, count
* 4);
1002 void r300_emit_viewport_state(struct r300_context
* r300
,
1003 unsigned size
, void* state
)
1005 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
1009 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
1010 OUT_CS_TABLE(&viewport
->xscale
, 6);
1011 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
1015 static void r300_emit_hiz_line_clear(struct r300_context
*r300
, int start
, uint16_t count
, uint32_t val
)
1019 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ
, 2);
1026 static void r300_emit_zmask_line_clear(struct r300_context
*r300
, int start
, uint16_t count
, uint32_t val
)
1030 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK
, 2);
1037 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1039 void r300_emit_hiz_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1041 struct pipe_framebuffer_state
*fb
=
1042 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1043 struct r300_hyperz_state
*z
=
1044 (struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
1045 struct r300_screen
* r300screen
= r300
->screen
;
1046 uint32_t stride
, offset
= 0, height
, offset_shift
;
1047 struct r300_texture
* tex
;
1050 tex
= r300_texture(fb
->zsbuf
->texture
);
1052 offset
= tex
->hiz_mem
[fb
->zsbuf
->level
]->ofs
;
1053 stride
= tex
->desc
.stride_in_pixels
[fb
->zsbuf
->level
];
1055 /* convert from pixels to 4x4 blocks */
1056 stride
= ALIGN_DIVUP(stride
, 4);
1058 stride
= ALIGN_DIVUP(stride
, r300screen
->caps
.num_frag_pipes
);
1059 /* there are 4 blocks per dwords */
1060 stride
= ALIGN_DIVUP(stride
, 4);
1062 height
= ALIGN_DIVUP(fb
->zsbuf
->height
, 4);
1065 offset_shift
+= (r300screen
->caps
.num_frag_pipes
/ 2);
1067 for (i
= 0; i
< height
; i
++) {
1068 offset
= i
* stride
;
1069 offset
<<= offset_shift
;
1070 r300_emit_hiz_line_clear(r300
, offset
, stride
, 0xffffffff);
1072 z
->current_func
= -1;
1074 /* Mark the current zbuffer's hiz ram as in use. */
1075 tex
->hiz_in_use
[fb
->zsbuf
->level
] = TRUE
;
1078 void r300_emit_zmask_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1080 struct pipe_framebuffer_state
*fb
=
1081 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1082 struct r300_screen
* r300screen
= r300
->screen
;
1083 uint32_t stride
, offset
= 0;
1084 struct r300_texture
* tex
;
1086 int mult
, offset_shift
;
1088 tex
= r300_texture(fb
->zsbuf
->texture
);
1089 stride
= tex
->desc
.stride_in_pixels
[fb
->zsbuf
->level
];
1091 offset
= tex
->zmask_mem
[fb
->zsbuf
->level
]->ofs
;
1093 if (r300
->z_compression
== RV350_Z_COMPRESS_88
)
1098 height
= ALIGN_DIVUP(fb
->zsbuf
->height
, mult
);
1101 offset_shift
+= (r300screen
->caps
.num_frag_pipes
/ 2);
1102 stride
= ALIGN_DIVUP(stride
, r300screen
->caps
.num_frag_pipes
);
1104 /* okay have width in pixels - divide by block width */
1105 stride
= ALIGN_DIVUP(stride
, mult
);
1106 /* have width in blocks - divide by number of fragment pipes screen width */
1107 /* 16 blocks per dword */
1108 stride
= ALIGN_DIVUP(stride
, 16);
1110 for (i
= 0; i
< height
; i
++) {
1111 offset
= i
* stride
;
1112 offset
<<= offset_shift
;
1113 r300_emit_zmask_line_clear(r300
, offset
, stride
, 0x0);//0xffffffff);
1116 /* Mark the current zbuffer's zmask as in use. */
1117 tex
->zmask_in_use
[fb
->zsbuf
->level
] = TRUE
;
1120 void r300_emit_ztop_state(struct r300_context
* r300
,
1121 unsigned size
, void* state
)
1123 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
1127 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
1131 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
1136 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
1140 void r300_emit_buffer_validate(struct r300_context
*r300
,
1141 boolean do_validate_vertex_buffers
,
1142 struct pipe_resource
*index_buffer
)
1144 struct pipe_framebuffer_state
* fb
=
1145 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1146 struct r300_textures_state
*texstate
=
1147 (struct r300_textures_state
*)r300
->textures_state
.state
;
1148 struct r300_texture
* tex
;
1149 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
1150 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
1151 struct pipe_resource
*pbuf
;
1153 boolean invalid
= FALSE
;
1155 /* upload buffers first */
1156 if (r300
->screen
->caps
.has_tcl
&& r300
->any_user_vbs
) {
1157 r300_upload_user_buffers(r300
);
1158 r300
->any_user_vbs
= false;
1161 /* Clean out BOs. */
1162 r300
->rws
->cs_reset_buffers(r300
->cs
);
1165 /* Color buffers... */
1166 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1167 tex
= r300_texture(fb
->cbufs
[i
]->texture
);
1168 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
1169 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->buffer
, 0,
1170 r300_surface(fb
->cbufs
[i
])->domain
);
1172 /* ...depth buffer... */
1174 tex
= r300_texture(fb
->zsbuf
->texture
);
1175 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
1176 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->buffer
, 0,
1177 r300_surface(fb
->zsbuf
)->domain
);
1179 /* ...textures... */
1180 for (i
= 0; i
< texstate
->count
; i
++) {
1181 if (!(texstate
->tx_enable
& (1 << i
))) {
1185 tex
= r300_texture(texstate
->sampler_views
[i
]->base
.texture
);
1186 r300
->rws
->cs_add_buffer(r300
->cs
, tex
->buffer
, tex
->domain
, 0);
1188 /* ...occlusion query buffer... */
1189 if (r300
->query_current
)
1190 r300
->rws
->cs_add_buffer(r300
->cs
, r300
->query_current
->buffer
,
1191 0, r300
->query_current
->domain
);
1192 /* ...vertex buffer for SWTCL path... */
1194 r300
->rws
->cs_add_buffer(r300
->cs
, r300_buffer(r300
->vbo
)->buf
,
1195 r300_buffer(r300
->vbo
)->domain
, 0);
1196 /* ...vertex buffers for HWTCL path... */
1197 if (do_validate_vertex_buffers
) {
1198 for (i
= 0; i
< r300
->velems
->count
; i
++) {
1199 pbuf
= vbuf
[velem
[i
].vertex_buffer_index
].buffer
;
1201 r300
->rws
->cs_add_buffer(r300
->cs
, r300_buffer(pbuf
)->buf
,
1202 r300_buffer(pbuf
)->domain
, 0);
1205 /* ...and index buffer for HWTCL path. */
1207 r300
->rws
->cs_add_buffer(r300
->cs
, r300_buffer(index_buffer
)->buf
,
1208 r300_buffer(index_buffer
)->domain
, 0);
1210 if (!r300
->rws
->cs_validate(r300
->cs
)) {
1211 r300
->context
.flush(&r300
->context
, 0, NULL
);
1214 fprintf(stderr
, "r300: Stuck in validation loop, gonna quit now.\n");
1222 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1224 struct r300_atom
* atom
;
1225 unsigned dwords
= 0;
1227 foreach(atom
, &r300
->atom_list
) {
1229 dwords
+= atom
->size
;
1233 /* let's reserve some more, just in case */
1239 unsigned r300_get_num_cs_end_dwords(struct r300_context
*r300
)
1241 unsigned dwords
= 0;
1243 /* Emitted in flush. */
1244 dwords
+= 26; /* emit_query_end */
1245 dwords
+= r300
->hyperz_state
.size
+ 2; /* emit_hyperz_end + zcache flush */
1246 if (r500_index_bias_supported(r300
))
1252 /* Emit all dirty state. */
1253 void r300_emit_dirty_state(struct r300_context
* r300
)
1255 struct r300_atom
* atom
;
1257 foreach(atom
, &r300
->atom_list
) {
1259 atom
->emit(r300
, atom
->size
, atom
->state
);
1260 if (SCREEN_DBG_ON(r300
->screen
, DBG_STATS
)) {
1263 atom
->dirty
= FALSE
;