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27fb9aa9ba8d5a823e64bc0f7d0fbcbe58c159a5
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_state_derived.h"
36 #include "r300_state_inlines.h"
37 #include "r300_texture.h"
38 #include "r300_vs.h"
39
40 void r300_emit_blend_state(struct r300_context* r300, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 CS_LOCALS(r300);
44 BEGIN_CS(8);
45 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
46 if (r300->framebuffer_state.nr_cbufs) {
47 OUT_CS(blend->blend_control);
48 OUT_CS(blend->alpha_blend_control);
49 OUT_CS(blend->color_channel_mask);
50 } else {
51 OUT_CS(0);
52 OUT_CS(0);
53 OUT_CS(0);
54 /* XXX also disable fastfill here once it's supported */
55 }
56 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
57 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
58 END_CS;
59 }
60
61 void r300_emit_blend_color_state(struct r300_context* r300, void* state)
62 {
63 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
64 struct r300_screen* r300screen = r300_screen(r300->context.screen);
65 CS_LOCALS(r300);
66
67 if (r300screen->caps->is_r500) {
68 BEGIN_CS(3);
69 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
70 OUT_CS(bc->blend_color_red_alpha);
71 OUT_CS(bc->blend_color_green_blue);
72 END_CS;
73 } else {
74 BEGIN_CS(2);
75 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
76 END_CS;
77 }
78 }
79
80 void r300_emit_clip_state(struct r300_context* r300, void* state)
81 {
82 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
83 int i;
84 struct r300_screen* r300screen = r300_screen(r300->context.screen);
85 CS_LOCALS(r300);
86
87 if (r300screen->caps->has_tcl) {
88 BEGIN_CS(5 + (6 * 4));
89 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
90 (r300screen->caps->is_r500 ?
91 R500_PVS_UCP_START : R300_PVS_UCP_START));
92 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
93 for (i = 0; i < 6; i++) {
94 OUT_CS_32F(clip->ucp[i][0]);
95 OUT_CS_32F(clip->ucp[i][1]);
96 OUT_CS_32F(clip->ucp[i][2]);
97 OUT_CS_32F(clip->ucp[i][3]);
98 }
99 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
100 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
101 END_CS;
102 } else {
103 BEGIN_CS(2);
104 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
105 END_CS;
106 }
107
108 }
109
110 void r300_emit_dsa_state(struct r300_context* r300, void* state)
111 {
112 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
113 struct r300_screen* r300screen = r300_screen(r300->context.screen);
114 CS_LOCALS(r300);
115
116 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 6);
117 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
118
119 /* not needed since we use the 8bit alpha ref */
120 /*if (r300screen->caps->is_r500) {
121 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
122 }*/
123
124 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
125
126 if (r300->framebuffer_state.zsbuf) {
127 OUT_CS(dsa->z_buffer_control);
128 OUT_CS(dsa->z_stencil_control);
129 } else {
130 OUT_CS(0);
131 OUT_CS(0);
132 }
133
134 OUT_CS(dsa->stencil_ref_mask);
135
136 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
137 if (r300screen->caps->is_r500) {
138 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
139 }
140 END_CS;
141 }
142
143 static const float * get_shader_constant(
144 struct r300_context * r300,
145 struct rc_constant * constant,
146 struct r300_constant_buffer * externals)
147 {
148 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
149 struct pipe_texture *tex;
150
151 switch(constant->Type) {
152 case RC_CONSTANT_EXTERNAL:
153 return externals->constants[constant->u.External];
154
155 case RC_CONSTANT_IMMEDIATE:
156 return constant->u.Immediate;
157
158 case RC_CONSTANT_STATE:
159 switch (constant->u.State[0]) {
160 /* Factor for converting rectangle coords to
161 * normalized coords. Should only show up on non-r500. */
162 case RC_STATE_R300_TEXRECT_FACTOR:
163 tex = &r300->textures[constant->u.State[1]]->tex;
164 vec[0] = 1.0 / tex->width0;
165 vec[1] = 1.0 / tex->height0;
166 break;
167
168 /* Texture compare-fail value. */
169 /* XXX Since Gallium doesn't support GL_ARB_shadow_ambient,
170 * this is always (0,0,0,0). */
171 case RC_STATE_SHADOW_AMBIENT:
172 vec[3] = 0;
173 break;
174
175 case RC_STATE_R300_VIEWPORT_SCALE:
176 if (r300->rs_state->enable_vte) {
177 vec[0] = r300->viewport_state->xscale;
178 vec[1] = r300->viewport_state->yscale;
179 vec[2] = r300->viewport_state->zscale;
180 } else {
181 vec[0] = 1;
182 vec[1] = 1;
183 vec[2] = 1;
184 }
185 break;
186
187 case RC_STATE_R300_VIEWPORT_OFFSET:
188 if (r300->rs_state->enable_vte) {
189 vec[0] = r300->viewport_state->xoffset;
190 vec[1] = r300->viewport_state->yoffset;
191 vec[2] = r300->viewport_state->zoffset;
192 } else {
193 /* Zeros. */
194 }
195 break;
196
197 default:
198 debug_printf("r300: Implementation error: "
199 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
200 }
201 break;
202
203 default:
204 debug_printf("r300: Implementation error: "
205 "Unhandled constant type %d\n", constant->Type);
206 }
207
208 /* This should either be (0, 0, 0, 1), which should be a relatively safe
209 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
210 * state factors. */
211 return vec;
212 }
213
214 /* Convert a normal single-precision float into the 7.16 format
215 * used by the R300 fragment shader.
216 */
217 static uint32_t pack_float24(float f)
218 {
219 union {
220 float fl;
221 uint32_t u;
222 } u;
223 float mantissa;
224 int exponent;
225 uint32_t float24 = 0;
226
227 if (f == 0.0)
228 return 0;
229
230 u.fl = f;
231
232 mantissa = frexpf(f, &exponent);
233
234 /* Handle -ve */
235 if (mantissa < 0) {
236 float24 |= (1 << 23);
237 mantissa = mantissa * -1.0;
238 }
239 /* Handle exponent, bias of 63 */
240 exponent += 62;
241 float24 |= (exponent << 16);
242 /* Kill 7 LSB of mantissa */
243 float24 |= (u.u & 0x7FFFFF) >> 7;
244
245 return float24;
246 }
247
248 void r300_emit_fragment_program_code(struct r300_context* r300,
249 struct rX00_fragment_program_code* generic_code)
250 {
251 struct r300_fragment_program_code * code = &generic_code->code.r300;
252 int i;
253 CS_LOCALS(r300);
254
255 BEGIN_CS(15 +
256 code->alu.length * 4 +
257 (code->tex.length ? (1 + code->tex.length) : 0));
258
259 OUT_CS_REG(R300_US_CONFIG, code->config);
260 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
261 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
262
263 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
264 for(i = 0; i < 4; ++i)
265 OUT_CS(code->code_addr[i]);
266
267 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
268 for (i = 0; i < code->alu.length; i++)
269 OUT_CS(code->alu.inst[i].rgb_inst);
270
271 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
272 for (i = 0; i < code->alu.length; i++)
273 OUT_CS(code->alu.inst[i].rgb_addr);
274
275 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
276 for (i = 0; i < code->alu.length; i++)
277 OUT_CS(code->alu.inst[i].alpha_inst);
278
279 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
280 for (i = 0; i < code->alu.length; i++)
281 OUT_CS(code->alu.inst[i].alpha_addr);
282
283 if (code->tex.length) {
284 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
285 for(i = 0; i < code->tex.length; ++i)
286 OUT_CS(code->tex.inst[i]);
287 }
288
289 END_CS;
290 }
291
292 void r300_emit_fs_constant_buffer(struct r300_context* r300,
293 struct rc_constant_list* constants)
294 {
295 int i;
296 CS_LOCALS(r300);
297
298 if (constants->Count == 0)
299 return;
300
301 BEGIN_CS(constants->Count * 4 + 1);
302 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
303 for(i = 0; i < constants->Count; ++i) {
304 const float * data = get_shader_constant(r300,
305 &constants->Constants[i],
306 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
307 OUT_CS(pack_float24(data[0]));
308 OUT_CS(pack_float24(data[1]));
309 OUT_CS(pack_float24(data[2]));
310 OUT_CS(pack_float24(data[3]));
311 }
312 END_CS;
313 }
314
315 static void r300_emit_fragment_depth_config(struct r300_context* r300,
316 struct r300_fragment_shader* fs)
317 {
318 CS_LOCALS(r300);
319
320 BEGIN_CS(4);
321 if (r300_fragment_shader_writes_depth(fs)) {
322 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
323 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
324 } else {
325 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
326 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
327 }
328 END_CS;
329 }
330
331 void r500_emit_fragment_program_code(struct r300_context* r300,
332 struct rX00_fragment_program_code* generic_code)
333 {
334 struct r500_fragment_program_code * code = &generic_code->code.r500;
335 int i;
336 CS_LOCALS(r300);
337
338 BEGIN_CS(13 +
339 ((code->inst_end + 1) * 6));
340 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
341 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
342 OUT_CS_REG(R500_US_CODE_RANGE,
343 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
344 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
345 OUT_CS_REG(R500_US_CODE_ADDR,
346 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
347
348 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
349 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
350 for (i = 0; i <= code->inst_end; i++) {
351 OUT_CS(code->inst[i].inst0);
352 OUT_CS(code->inst[i].inst1);
353 OUT_CS(code->inst[i].inst2);
354 OUT_CS(code->inst[i].inst3);
355 OUT_CS(code->inst[i].inst4);
356 OUT_CS(code->inst[i].inst5);
357 }
358
359 END_CS;
360 }
361
362 void r500_emit_fs_constant_buffer(struct r300_context* r300,
363 struct rc_constant_list* constants)
364 {
365 int i;
366 CS_LOCALS(r300);
367
368 if (constants->Count == 0)
369 return;
370
371 BEGIN_CS(constants->Count * 4 + 3);
372 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
373 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
374 for (i = 0; i < constants->Count; i++) {
375 const float * data = get_shader_constant(r300,
376 &constants->Constants[i],
377 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
378 OUT_CS_32F(data[0]);
379 OUT_CS_32F(data[1]);
380 OUT_CS_32F(data[2]);
381 OUT_CS_32F(data[3]);
382 }
383 END_CS;
384 }
385
386 void r300_emit_fb_state(struct r300_context* r300,
387 struct pipe_framebuffer_state* fb)
388 {
389 struct r300_texture* tex;
390 struct pipe_surface* surf;
391 int i;
392 CS_LOCALS(r300);
393
394 /* Shouldn't fail unless there is a bug in the state tracker. */
395 assert(fb->nr_cbufs <= 4);
396
397 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
398 (fb->zsbuf ? 10 : 0) + 6);
399
400 /* Flush and free renderbuffer caches. */
401 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
402 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
403 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
404 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
405 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
406 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
407
408 /* Set the number of colorbuffers. */
409 OUT_CS_REG(R300_RB3D_CCTL, R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
410
411 /* Set up colorbuffers. */
412 for (i = 0; i < fb->nr_cbufs; i++) {
413 surf = fb->cbufs[i];
414 tex = (struct r300_texture*)surf->texture;
415 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
416
417 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
418 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
419
420 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
421 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
422 r300_translate_colorformat(tex->tex.format), 0,
423 RADEON_GEM_DOMAIN_VRAM, 0);
424
425 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
426 r300_translate_out_fmt(surf->format));
427 }
428
429 /* Disable unused colorbuffers. */
430 for (; i < 4; i++) {
431 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
432 }
433
434 /* Set up a zbuffer. */
435 if (fb->zsbuf) {
436 surf = fb->zsbuf;
437 tex = (struct r300_texture*)surf->texture;
438 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
439
440 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
441 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
442
443 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
444
445 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
446 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level], 0,
447 RADEON_GEM_DOMAIN_VRAM, 0);
448 }
449
450 END_CS;
451 }
452
453 static void r300_emit_query_start(struct r300_context *r300)
454 {
455 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
456 struct r300_query *query = r300->query_current;
457 CS_LOCALS(r300);
458
459 if (!query)
460 return;
461
462 BEGIN_CS(4);
463 if (caps->family == CHIP_FAMILY_RV530) {
464 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
465 } else {
466 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
467 }
468 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
469 END_CS;
470 query->begin_emitted = TRUE;
471 }
472
473
474 static void r300_emit_query_finish(struct r300_context *r300,
475 struct r300_query *query)
476 {
477 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
478 CS_LOCALS(r300);
479
480 assert(caps->num_frag_pipes);
481
482 BEGIN_CS(6 * caps->num_frag_pipes + 2);
483 /* I'm not so sure I like this switch, but it's hard to be elegant
484 * when there's so many special cases...
485 *
486 * So here's the basic idea. For each pipe, enable writes to it only,
487 * then put out the relocation for ZPASS_ADDR, taking into account a
488 * 4-byte offset for each pipe. RV380 and older are special; they have
489 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
490 * so there's a chipset cap for that. */
491 switch (caps->num_frag_pipes) {
492 case 4:
493 /* pipe 3 only */
494 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
495 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
496 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
497 0, RADEON_GEM_DOMAIN_GTT, 0);
498 case 3:
499 /* pipe 2 only */
500 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
501 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
502 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
503 0, RADEON_GEM_DOMAIN_GTT, 0);
504 case 2:
505 /* pipe 1 only */
506 /* As mentioned above, accomodate RV380 and older. */
507 OUT_CS_REG(R300_SU_REG_DEST,
508 1 << (caps->high_second_pipe ? 3 : 1));
509 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
510 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
511 0, RADEON_GEM_DOMAIN_GTT, 0);
512 case 1:
513 /* pipe 0 only */
514 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
515 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
516 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
517 0, RADEON_GEM_DOMAIN_GTT, 0);
518 break;
519 default:
520 debug_printf("r300: Implementation error: Chipset reports %d"
521 " pixel pipes!\n", caps->num_frag_pipes);
522 assert(0);
523 }
524
525 /* And, finally, reset it to normal... */
526 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
527 END_CS;
528 }
529
530 static void rv530_emit_query_single(struct r300_context *r300,
531 struct r300_query *query)
532 {
533 CS_LOCALS(r300);
534
535 BEGIN_CS(8);
536 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
537 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
538 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
539 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
540 END_CS;
541 }
542
543 static void rv530_emit_query_double(struct r300_context *r300,
544 struct r300_query *query)
545 {
546 CS_LOCALS(r300);
547
548 BEGIN_CS(14);
549 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
550 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
551 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
552 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
553 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
554 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
555 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
556 END_CS;
557 }
558
559 void r300_emit_query_end(struct r300_context* r300)
560 {
561 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
562 struct r300_query *query = r300->query_current;
563
564 if (!query)
565 return;
566
567 if (query->begin_emitted == FALSE)
568 return;
569
570 if (caps->family == CHIP_FAMILY_RV530) {
571 if (caps->num_z_pipes == 2)
572 rv530_emit_query_double(r300, query);
573 else
574 rv530_emit_query_single(r300, query);
575 } else
576 r300_emit_query_finish(r300, query);
577 }
578
579 void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs)
580 {
581 CS_LOCALS(r300);
582
583 BEGIN_CS(22);
584 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
585 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
586 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
587 OUT_CS(rs->point_minmax);
588 OUT_CS(rs->line_control);
589 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
590 OUT_CS(rs->depth_scale_front);
591 OUT_CS(rs->depth_offset_front);
592 OUT_CS(rs->depth_scale_back);
593 OUT_CS(rs->depth_offset_back);
594 OUT_CS(rs->polygon_offset_enable);
595 OUT_CS(rs->cull_mode);
596 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
597 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
598 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
599 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
600 END_CS;
601 }
602
603 void r300_emit_rs_block_state(struct r300_context* r300,
604 struct r300_rs_block* rs)
605 {
606 int i;
607 struct r300_screen* r300screen = r300_screen(r300->context.screen);
608 CS_LOCALS(r300);
609
610 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
611
612 BEGIN_CS(21);
613 if (r300screen->caps->is_r500) {
614 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
615 } else {
616 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
617 }
618 for (i = 0; i < 8; i++) {
619 OUT_CS(rs->ip[i]);
620 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
621 }
622
623 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
624 OUT_CS(rs->count);
625 OUT_CS(rs->inst_count);
626
627 if (r300screen->caps->is_r500) {
628 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
629 } else {
630 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
631 }
632 for (i = 0; i < 8; i++) {
633 OUT_CS(rs->inst[i]);
634 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
635 }
636
637 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
638 rs->count, rs->inst_count);
639
640 END_CS;
641 }
642
643 static void r300_emit_scissor_regs(struct r300_context* r300,
644 struct r300_scissor_regs* scissor)
645 {
646 CS_LOCALS(r300);
647
648 BEGIN_CS(3);
649 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
650 OUT_CS(scissor->top_left);
651 OUT_CS(scissor->bottom_right);
652 END_CS;
653 }
654
655 void r300_emit_scissor_state(struct r300_context* r300,
656 struct r300_scissor_state* scissor)
657 {
658 if (r300->rs_state->rs.scissor) {
659 r300_emit_scissor_regs(r300, &scissor->scissor);
660 } else {
661 r300_emit_scissor_regs(r300, &scissor->framebuffer);
662 }
663 }
664
665 void r300_emit_texture(struct r300_context* r300,
666 struct r300_sampler_state* sampler,
667 struct r300_texture* tex,
668 unsigned offset)
669 {
670 uint32_t filter0 = sampler->filter0;
671 uint32_t format0 = tex->state.format0;
672 unsigned min_level, max_level;
673 CS_LOCALS(r300);
674
675 /* to emulate 1D textures through 2D ones correctly */
676 if (tex->tex.target == PIPE_TEXTURE_1D) {
677 filter0 &= ~R300_TX_WRAP_T_MASK;
678 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
679 }
680
681 /* determine min/max levels */
682 /* the MAX_MIP level is the largest (finest) one */
683 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
684 min_level = MIN2(sampler->min_lod, max_level);
685 format0 |= R300_TX_NUM_LEVELS(max_level);
686 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
687
688 BEGIN_CS(16);
689 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
690 (offset << 28));
691 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
692 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
693
694 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
695 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
696 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
697 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
698 OUT_CS_RELOC(tex->buffer, 0,
699 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
700 END_CS;
701 }
702
703 static boolean r300_validate_aos(struct r300_context *r300)
704 {
705 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
706 struct pipe_vertex_element *velem = r300->vertex_element;
707 int i;
708
709 /* Check if formats and strides are aligned to the size of DWORD. */
710 for (i = 0; i < r300->vertex_element_count; i++) {
711 if (vbuf[velem[i].vertex_buffer_index].stride % 4 != 0 ||
712 util_format_get_blocksize(velem[i].src_format) % 4 != 0) {
713 return FALSE;
714 }
715 }
716 return TRUE;
717 }
718
719 void r300_emit_aos(struct r300_context* r300, unsigned offset)
720 {
721 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
722 struct pipe_vertex_element *velem = r300->vertex_element;
723 int i;
724 unsigned size1, size2, aos_count = r300->vertex_element_count;
725 unsigned packet_size = (aos_count * 3 + 1) / 2;
726 CS_LOCALS(r300);
727
728 /* XXX Move this checking to a more approriate place. */
729 if (!r300_validate_aos(r300)) {
730 /* XXX We should fallback using Draw. */
731 assert(0);
732 }
733
734 BEGIN_CS(2 + packet_size + aos_count * 2);
735 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
736 OUT_CS(aos_count);
737
738 for (i = 0; i < aos_count - 1; i += 2) {
739 vb1 = &vbuf[velem[i].vertex_buffer_index];
740 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
741 size1 = util_format_get_blocksize(velem[i].src_format);
742 size2 = util_format_get_blocksize(velem[i+1].src_format);
743
744 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
745 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
746 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
747 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
748 }
749
750 if (aos_count & 1) {
751 vb1 = &vbuf[velem[i].vertex_buffer_index];
752 size1 = util_format_get_blocksize(velem[i].src_format);
753
754 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
755 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
756 }
757
758 for (i = 0; i < aos_count; i++) {
759 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
760 RADEON_GEM_DOMAIN_GTT, 0, 0);
761 }
762 END_CS;
763 }
764
765 #if 0
766 void r300_emit_draw_packet(struct r300_context* r300)
767 {
768 CS_LOCALS(r300);
769
770 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
771 "vertex size %d\n", r300->vbo,
772 r300->vertex_info->vinfo.size);
773 /* Set the pointer to our vertex buffer. The emitted values are this:
774 * PACKET3 [3D_LOAD_VBPNTR]
775 * COUNT [1]
776 * FORMAT [size | stride << 8]
777 * OFFSET [offset into BO]
778 * VBPNTR [relocated BO]
779 */
780 BEGIN_CS(7);
781 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
782 OUT_CS(1);
783 OUT_CS(r300->vertex_info->vinfo.size |
784 (r300->vertex_info->vinfo.size << 8));
785 OUT_CS(r300->vbo_offset);
786 OUT_CS_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
787 END_CS;
788 }
789 #endif
790
791 void r300_emit_vertex_format_state(struct r300_context* r300)
792 {
793 int i;
794 CS_LOCALS(r300);
795
796 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
797
798 BEGIN_CS(26);
799 OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info->vinfo.size);
800
801 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
802 OUT_CS(r300->vertex_info->vinfo.hwfmt[0]);
803 OUT_CS(r300->vertex_info->vinfo.hwfmt[1]);
804 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
805 OUT_CS(r300->vertex_info->vinfo.hwfmt[2]);
806 OUT_CS(r300->vertex_info->vinfo.hwfmt[3]);
807 for (i = 0; i < 4; i++) {
808 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
809 r300->vertex_info->vinfo.hwfmt[i]);
810 }
811
812 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
813 for (i = 0; i < 8; i++) {
814 OUT_CS(r300->vertex_info->vap_prog_stream_cntl[i]);
815 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
816 r300->vertex_info->vap_prog_stream_cntl[i]);
817 }
818 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
819 for (i = 0; i < 8; i++) {
820 OUT_CS(r300->vertex_info->vap_prog_stream_cntl_ext[i]);
821 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
822 r300->vertex_info->vap_prog_stream_cntl_ext[i]);
823 }
824 END_CS;
825 }
826
827
828 void r300_emit_vertex_program_code(struct r300_context* r300,
829 struct r300_vertex_program_code* code)
830 {
831 int i;
832 struct r300_screen* r300screen = r300_screen(r300->context.screen);
833 unsigned instruction_count = code->length / 4;
834
835 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
836 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
837 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
838 int temp_count = MAX2(code->num_temporaries, 1);
839 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
840 vtx_mem_size / output_count, 10);
841 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
842
843 CS_LOCALS(r300);
844
845 if (!r300screen->caps->has_tcl) {
846 debug_printf("r300: Implementation error: emit_vertex_shader called,"
847 " but has_tcl is FALSE!\n");
848 return;
849 }
850
851 BEGIN_CS(9 + code->length);
852 /* R300_VAP_PVS_CODE_CNTL_0
853 * R300_VAP_PVS_CONST_CNTL
854 * R300_VAP_PVS_CODE_CNTL_1
855 * See the r5xx docs for instructions on how to use these. */
856 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
857 OUT_CS(R300_PVS_FIRST_INST(0) |
858 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
859 R300_PVS_LAST_INST(instruction_count - 1));
860 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
861 OUT_CS(instruction_count - 1);
862
863 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
864 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
865 for (i = 0; i < code->length; i++)
866 OUT_CS(code->body.d[i]);
867
868 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
869 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
870 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
871 R300_PVS_VF_MAX_VTX_NUM(12) |
872 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
873 END_CS;
874 }
875
876 void r300_emit_vertex_shader(struct r300_context* r300,
877 struct r300_vertex_shader* vs)
878 {
879 r300_emit_vertex_program_code(r300, &vs->code);
880 }
881
882 void r300_emit_vs_constant_buffer(struct r300_context* r300,
883 struct rc_constant_list* constants)
884 {
885 int i;
886 struct r300_screen* r300screen = r300_screen(r300->context.screen);
887 CS_LOCALS(r300);
888
889 if (!r300screen->caps->has_tcl) {
890 debug_printf("r300: Implementation error: emit_vertex_shader called,"
891 " but has_tcl is FALSE!\n");
892 return;
893 }
894
895 if (constants->Count == 0)
896 return;
897
898 BEGIN_CS(constants->Count * 4 + 3);
899 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
900 (r300screen->caps->is_r500 ?
901 R500_PVS_CONST_START : R300_PVS_CONST_START));
902 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
903 for (i = 0; i < constants->Count; i++) {
904 const float * data = get_shader_constant(r300,
905 &constants->Constants[i],
906 &r300->shader_constants[PIPE_SHADER_VERTEX]);
907 OUT_CS_32F(data[0]);
908 OUT_CS_32F(data[1]);
909 OUT_CS_32F(data[2]);
910 OUT_CS_32F(data[3]);
911 }
912 END_CS;
913 }
914
915 void r300_emit_viewport_state(struct r300_context* r300,
916 struct r300_viewport_state* viewport)
917 {
918 CS_LOCALS(r300);
919
920 BEGIN_CS(9);
921 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
922 OUT_CS_32F(viewport->xscale);
923 OUT_CS_32F(viewport->xoffset);
924 OUT_CS_32F(viewport->yscale);
925 OUT_CS_32F(viewport->yoffset);
926 OUT_CS_32F(viewport->zscale);
927 OUT_CS_32F(viewport->zoffset);
928
929 if (r300->rs_state->enable_vte) {
930 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
931 } else {
932 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
933 }
934 END_CS;
935 }
936
937 void r300_emit_texture_count(struct r300_context* r300)
938 {
939 uint32_t tx_enable = 0;
940 int i;
941 CS_LOCALS(r300);
942
943 /* Notice that texture_count and sampler_count are just sizes
944 * of the respective arrays. We still have to check for the individual
945 * elements. */
946 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
947 if (r300->textures[i]) {
948 tx_enable |= 1 << i;
949 }
950 }
951
952 BEGIN_CS(2);
953 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
954 END_CS;
955
956 }
957
958 void r300_emit_ztop_state(struct r300_context* r300, void* state)
959 {
960 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
961 CS_LOCALS(r300);
962
963 BEGIN_CS(2);
964 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
965 END_CS;
966 }
967
968 void r300_flush_textures(struct r300_context* r300)
969 {
970 CS_LOCALS(r300);
971
972 BEGIN_CS(2);
973 OUT_CS_REG(R300_TX_INVALTAGS, 0);
974 END_CS;
975 }
976
977 static void r300_flush_pvs(struct r300_context* r300)
978 {
979 CS_LOCALS(r300);
980
981 BEGIN_CS(2);
982 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
983 END_CS;
984 }
985
986 /* Emit all dirty state. */
987 void r300_emit_dirty_state(struct r300_context* r300)
988 {
989 struct r300_screen* r300screen = r300_screen(r300->context.screen);
990 struct r300_texture* tex;
991 struct r300_atom* atom;
992 int i, dirty_tex = 0;
993 boolean invalid = FALSE;
994
995 /* Check size of CS. */
996 /* Make sure we have at least 8*1024 spare dwords. */
997 /* XXX It would be nice to know the number of dwords we really need to
998 * XXX emit. */
999 if (!r300->winsys->check_cs(r300->winsys, 8*1024)) {
1000 r300->context.flush(&r300->context, 0, NULL);
1001 }
1002
1003 /* Clean out BOs. */
1004 r300->winsys->reset_bos(r300->winsys);
1005
1006 validate:
1007 /* Color buffers... */
1008 for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
1009 tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
1010 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1011 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1012 0, RADEON_GEM_DOMAIN_VRAM)) {
1013 r300->context.flush(&r300->context, 0, NULL);
1014 goto validate;
1015 }
1016 }
1017 /* ...depth buffer... */
1018 if (r300->framebuffer_state.zsbuf) {
1019 tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
1020 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1021 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1022 0, RADEON_GEM_DOMAIN_VRAM)) {
1023 r300->context.flush(&r300->context, 0, NULL);
1024 goto validate;
1025 }
1026 }
1027 /* ...textures... */
1028 for (i = 0; i < r300->texture_count; i++) {
1029 tex = r300->textures[i];
1030 if (!tex)
1031 continue;
1032 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1033 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1034 r300->context.flush(&r300->context, 0, NULL);
1035 goto validate;
1036 }
1037 }
1038 /* ...occlusion query buffer... */
1039 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1040 0, RADEON_GEM_DOMAIN_GTT)) {
1041 r300->context.flush(&r300->context, 0, NULL);
1042 goto validate;
1043 }
1044 /* ...and vertex buffer. */
1045 if (r300->vbo) {
1046 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1047 RADEON_GEM_DOMAIN_GTT, 0)) {
1048 r300->context.flush(&r300->context, 0, NULL);
1049 goto validate;
1050 }
1051 } else {
1052 /* debug_printf("No VBO while emitting dirty state!\n"); */
1053 }
1054 if (!r300->winsys->validate(r300->winsys)) {
1055 r300->context.flush(&r300->context, 0, NULL);
1056 if (invalid) {
1057 /* Well, hell. */
1058 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1059 exit(1);
1060 }
1061 invalid = TRUE;
1062 goto validate;
1063 }
1064
1065 if (r300->dirty_state & R300_NEW_QUERY) {
1066 r300_emit_query_start(r300);
1067 r300->dirty_state &= ~R300_NEW_QUERY;
1068 }
1069
1070 foreach(atom, &r300->atom_list) {
1071 if (atom->dirty) {
1072 atom->emit(r300, atom->state);
1073 atom->dirty = FALSE;
1074 }
1075 }
1076
1077 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1078 r300_emit_fragment_depth_config(r300, r300->fs);
1079 if (r300screen->caps->is_r500) {
1080 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1081 } else {
1082 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1083 }
1084 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1085 }
1086
1087 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1088 if (r300screen->caps->is_r500) {
1089 r500_emit_fs_constant_buffer(r300,
1090 &r300->fs->shader->code.constants);
1091 } else {
1092 r300_emit_fs_constant_buffer(r300,
1093 &r300->fs->shader->code.constants);
1094 }
1095 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1096 }
1097
1098 if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
1099 r300_emit_fb_state(r300, &r300->framebuffer_state);
1100 r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
1101 }
1102
1103 if (r300->dirty_state & R300_NEW_RASTERIZER) {
1104 r300_emit_rs_state(r300, r300->rs_state);
1105 r300->dirty_state &= ~R300_NEW_RASTERIZER;
1106 }
1107
1108 if (r300->dirty_state & R300_NEW_RS_BLOCK) {
1109 r300_emit_rs_block_state(r300, r300->rs_block);
1110 r300->dirty_state &= ~R300_NEW_RS_BLOCK;
1111 }
1112
1113 if (r300->dirty_state & R300_NEW_SCISSOR) {
1114 r300_emit_scissor_state(r300, r300->scissor_state);
1115 r300->dirty_state &= ~R300_NEW_SCISSOR;
1116 }
1117
1118 /* Samplers and textures are tracked separately but emitted together. */
1119 if (r300->dirty_state &
1120 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1121 r300_emit_texture_count(r300);
1122
1123 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1124 if (r300->dirty_state &
1125 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1126 if (r300->textures[i])
1127 r300_emit_texture(r300,
1128 r300->sampler_states[i],
1129 r300->textures[i],
1130 i);
1131 r300->dirty_state &=
1132 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1133 dirty_tex++;
1134 }
1135 }
1136 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1137 }
1138
1139 if (r300->dirty_state & R300_NEW_VIEWPORT) {
1140 r300_emit_viewport_state(r300, r300->viewport_state);
1141 r300->dirty_state &= ~R300_NEW_VIEWPORT;
1142 }
1143
1144 if (dirty_tex) {
1145 r300_flush_textures(r300);
1146 }
1147
1148 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
1149 r300_emit_vertex_format_state(r300);
1150 r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
1151 }
1152
1153 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1154 r300_flush_pvs(r300);
1155 }
1156
1157 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1158 r300_emit_vertex_shader(r300, r300->vs);
1159 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1160 }
1161
1162 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1163 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1164 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1165 }
1166
1167 /* XXX
1168 assert(r300->dirty_state == 0);
1169 */
1170
1171 /* Finally, emit the VBO. */
1172 /* r300_emit_vertex_buffer(r300); */
1173
1174 r300->dirty_hw++;
1175 }