projects / mesa.git / blob
? search:


2fa3f6fe2eca50f56a2586e9b4878e4b9f8a0ae6
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300,
39 unsigned size, void* state)
40 {
41 struct r300_blend_state* blend = (struct r300_blend_state*)state;
42 struct pipe_framebuffer_state* fb =
43 (struct pipe_framebuffer_state*)r300->fb_state.state;
44 CS_LOCALS(r300);
45
46 BEGIN_CS(size);
47 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
48 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
49 if (fb->nr_cbufs) {
50 OUT_CS(blend->blend_control);
51 OUT_CS(blend->alpha_blend_control);
52 OUT_CS(blend->color_channel_mask);
53 } else {
54 OUT_CS(0);
55 OUT_CS(0);
56 OUT_CS(0);
57 /* XXX also disable fastfill here once it's supported */
58 }
59 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
60 END_CS;
61 }
62
63 void r300_emit_blend_color_state(struct r300_context* r300,
64 unsigned size, void* state)
65 {
66 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
67 CS_LOCALS(r300);
68
69 if (r300->screen->caps.is_r500) {
70 BEGIN_CS(size);
71 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
72 OUT_CS(bc->blend_color_red_alpha);
73 OUT_CS(bc->blend_color_green_blue);
74 END_CS;
75 } else {
76 BEGIN_CS(size);
77 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
78 END_CS;
79 }
80 }
81
82 void r300_emit_clip_state(struct r300_context* r300,
83 unsigned size, void* state)
84 {
85 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
86 int i;
87 CS_LOCALS(r300);
88
89 if (r300->screen->caps.has_tcl) {
90 BEGIN_CS(size);
91 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
92 (r300->screen->caps.is_r500 ?
93 R500_PVS_UCP_START : R300_PVS_UCP_START));
94 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
95 for (i = 0; i < 6; i++) {
96 OUT_CS_32F(clip->ucp[i][0]);
97 OUT_CS_32F(clip->ucp[i][1]);
98 OUT_CS_32F(clip->ucp[i][2]);
99 OUT_CS_32F(clip->ucp[i][3]);
100 }
101 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
102 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
103 END_CS;
104 } else {
105 BEGIN_CS(size);
106 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
107 END_CS;
108 }
109
110 }
111
112 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
113 {
114 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
115 struct pipe_framebuffer_state* fb =
116 (struct pipe_framebuffer_state*)r300->fb_state.state;
117 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
118 CS_LOCALS(r300);
119
120 BEGIN_CS(size);
121 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
122 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
123
124 if (fb->zsbuf) {
125 OUT_CS(dsa->z_buffer_control);
126 OUT_CS(dsa->z_stencil_control);
127 } else {
128 OUT_CS(0);
129 OUT_CS(0);
130 }
131
132 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
133
134 if (r300->screen->caps.is_r500) {
135 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
136 }
137 END_CS;
138 }
139
140 static const float * get_shader_constant(
141 struct r300_context * r300,
142 struct rc_constant * constant,
143 struct r300_constant_buffer * externals)
144 {
145 struct r300_viewport_state* viewport = r300->viewport_state.state;
146 struct r300_textures_state* texstate = r300->textures_state.state;
147 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
148 struct pipe_resource *tex;
149
150 switch(constant->Type) {
151 case RC_CONSTANT_EXTERNAL:
152 return externals->constants[constant->u.External];
153
154 case RC_CONSTANT_IMMEDIATE:
155 return constant->u.Immediate;
156
157 case RC_CONSTANT_STATE:
158 switch (constant->u.State[0]) {
159 /* Factor for converting rectangle coords to
160 * normalized coords. Should only show up on non-r500. */
161 case RC_STATE_R300_TEXRECT_FACTOR:
162 tex = texstate->sampler_views[constant->u.State[1]]->base.texture;
163 vec[0] = 1.0 / tex->width0;
164 vec[1] = 1.0 / tex->height0;
165 break;
166
167 /* Texture compare-fail value. Shouldn't ever show up, but if
168 * it does, we'll be ready. */
169 case RC_STATE_SHADOW_AMBIENT:
170 vec[3] = 0;
171 break;
172
173 case RC_STATE_R300_VIEWPORT_SCALE:
174 vec[0] = viewport->xscale;
175 vec[1] = viewport->yscale;
176 vec[2] = viewport->zscale;
177 break;
178
179 case RC_STATE_R300_VIEWPORT_OFFSET:
180 vec[0] = viewport->xoffset;
181 vec[1] = viewport->yoffset;
182 vec[2] = viewport->zoffset;
183 break;
184
185 default:
186 fprintf(stderr, "r300: Implementation error: "
187 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
188 }
189 break;
190
191 default:
192 fprintf(stderr, "r300: Implementation error: "
193 "Unhandled constant type %d\n", constant->Type);
194 }
195
196 /* This should either be (0, 0, 0, 1), which should be a relatively safe
197 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
198 * state factors. */
199 return vec;
200 }
201
202 /* Convert a normal single-precision float into the 7.16 format
203 * used by the R300 fragment shader.
204 */
205 static uint32_t pack_float24(float f)
206 {
207 union {
208 float fl;
209 uint32_t u;
210 } u;
211 float mantissa;
212 int exponent;
213 uint32_t float24 = 0;
214
215 if (f == 0.0)
216 return 0;
217
218 u.fl = f;
219
220 mantissa = frexpf(f, &exponent);
221
222 /* Handle -ve */
223 if (mantissa < 0) {
224 float24 |= (1 << 23);
225 mantissa = mantissa * -1.0;
226 }
227 /* Handle exponent, bias of 63 */
228 exponent += 62;
229 float24 |= (exponent << 16);
230 /* Kill 7 LSB of mantissa */
231 float24 |= (u.u & 0x7FFFFF) >> 7;
232
233 return float24;
234 }
235
236 static void r300_emit_fragment_depth_config(struct r300_context* r300)
237 {
238 CS_LOCALS(r300);
239 if (r300_fragment_shader_writes_depth(r300_fs(r300))) {
240 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
241 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
242 } else {
243 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
244 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
245 }
246 }
247
248 unsigned r300_get_fs_atom_size(struct r300_context *r300)
249 {
250 struct r300_fragment_shader *fs = r300_fs(r300);
251 unsigned imm_count = fs->shader->immediates_count;
252 struct r300_fragment_program_code *code = &fs->shader->code.code.r300;
253
254 return 19 +
255 code->alu.length * 4 +
256 (code->tex.length ? (1 + code->tex.length) : 0) +
257 (imm_count ? imm_count * 5 : 0);
258 }
259
260 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
261 {
262 struct r300_fragment_shader *fs = r300_fs(r300);
263 struct rX00_fragment_program_code* generic_code = &fs->shader->code;
264 struct r300_fragment_program_code * code = &generic_code->code.r300;
265 unsigned i;
266 unsigned imm_count = fs->shader->immediates_count;
267 unsigned imm_first = fs->shader->externals_count;
268 unsigned imm_end = generic_code->constants.Count;
269 struct rc_constant *constants = generic_code->constants.Constants;
270 CS_LOCALS(r300);
271
272 BEGIN_CS(size);
273 OUT_CS_REG(R300_US_CONFIG, code->config);
274 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
275 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
276
277 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
278 for(i = 0; i < 4; ++i)
279 OUT_CS(code->code_addr[i]);
280
281 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
282 for (i = 0; i < code->alu.length; i++)
283 OUT_CS(code->alu.inst[i].rgb_inst);
284
285 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
286 for (i = 0; i < code->alu.length; i++)
287 OUT_CS(code->alu.inst[i].rgb_addr);
288
289 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
290 for (i = 0; i < code->alu.length; i++)
291 OUT_CS(code->alu.inst[i].alpha_inst);
292
293 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
294 for (i = 0; i < code->alu.length; i++)
295 OUT_CS(code->alu.inst[i].alpha_addr);
296
297 if (code->tex.length) {
298 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
299 for(i = 0; i < code->tex.length; ++i)
300 OUT_CS(code->tex.inst[i]);
301 }
302
303 /* Emit immediates. */
304 if (imm_count) {
305 for(i = imm_first; i < imm_end; ++i) {
306 if (constants[i].Type == RC_CONSTANT_IMMEDIATE) {
307 const float *data = constants[i].u.Immediate;
308
309 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
310 OUT_CS(pack_float24(data[0]));
311 OUT_CS(pack_float24(data[1]));
312 OUT_CS(pack_float24(data[2]));
313 OUT_CS(pack_float24(data[3]));
314 }
315 }
316 }
317
318 r300_emit_fragment_depth_config(r300);
319 cs_count -= 4;
320 END_CS;
321 }
322
323 void r300_emit_fs_constant_buffer(struct r300_context* r300,
324 struct rc_constant_list* constants)
325 {
326 struct r300_fragment_shader *fs = r300_fs(r300);
327 unsigned i, count = fs->shader->externals_count;
328 CS_LOCALS(r300);
329
330 if (count == 0)
331 return;
332
333 BEGIN_CS(count * 4 + 1);
334 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
335 for(i = 0; i < count; ++i) {
336 assert(constants->Constants[i].Type == RC_CONSTANT_EXTERNAL);
337 const float *data =
338 r300->shader_constants[PIPE_SHADER_FRAGMENT].constants[i];
339 OUT_CS(pack_float24(data[0]));
340 OUT_CS(pack_float24(data[1]));
341 OUT_CS(pack_float24(data[2]));
342 OUT_CS(pack_float24(data[3]));
343 }
344 END_CS;
345 }
346
347 void r300_emit_fs_constant_rc_state(struct r300_context* r300,
348 struct rc_constant_list* constants)
349 {
350 struct r300_fragment_shader *fs = r300_fs(r300);
351 unsigned i;
352 unsigned count = fs->shader->rc_state_count;
353 unsigned first = fs->shader->externals_count;
354 unsigned end = constants->Count;
355 CS_LOCALS(r300);
356
357 if (count == 0)
358 return;
359
360 BEGIN_CS(count * 5);
361 for(i = first; i < end; ++i) {
362 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
363 const float *data = get_shader_constant(r300,
364 &constants->Constants[i], 0);
365
366 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
367 OUT_CS(pack_float24(data[0]));
368 OUT_CS(pack_float24(data[1]));
369 OUT_CS(pack_float24(data[2]));
370 OUT_CS(pack_float24(data[3]));
371 }
372 }
373 END_CS;
374 }
375
376 unsigned r500_get_fs_atom_size(struct r300_context *r300)
377 {
378 struct r300_fragment_shader *fs = r300_fs(r300);
379 unsigned imm_count = fs->shader->immediates_count;
380 struct r500_fragment_program_code *code = &fs->shader->code.code.r500;
381
382 return 17 +
383 ((code->inst_end + 1) * 6) +
384 (imm_count ? imm_count * 7 : 0);
385 }
386
387 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
388 {
389 struct r300_fragment_shader *fs = r300_fs(r300);
390 struct rX00_fragment_program_code* generic_code = &fs->shader->code;
391 struct r500_fragment_program_code * code = &generic_code->code.r500;
392 unsigned i;
393 unsigned imm_count = fs->shader->immediates_count;
394 unsigned imm_first = fs->shader->externals_count;
395 unsigned imm_end = generic_code->constants.Count;
396 struct rc_constant *constants = generic_code->constants.Constants;
397 CS_LOCALS(r300);
398
399 BEGIN_CS(size);
400 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
401 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
402 OUT_CS_REG(R500_US_CODE_RANGE,
403 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
404 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
405 OUT_CS_REG(R500_US_CODE_ADDR,
406 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
407
408 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
409 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
410 for (i = 0; i <= code->inst_end; i++) {
411 OUT_CS(code->inst[i].inst0);
412 OUT_CS(code->inst[i].inst1);
413 OUT_CS(code->inst[i].inst2);
414 OUT_CS(code->inst[i].inst3);
415 OUT_CS(code->inst[i].inst4);
416 OUT_CS(code->inst[i].inst5);
417 }
418
419 /* Emit immediates. */
420 if (imm_count) {
421 for(i = imm_first; i < imm_end; ++i) {
422 if (constants[i].Type == RC_CONSTANT_IMMEDIATE) {
423 const float *data = constants[i].u.Immediate;
424
425 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
426 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
427 (i & R500_GA_US_VECTOR_INDEX_MASK));
428 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
429 OUT_CS_32F(data[0]);
430 OUT_CS_32F(data[1]);
431 OUT_CS_32F(data[2]);
432 OUT_CS_32F(data[3]);
433 }
434 }
435 }
436
437 r300_emit_fragment_depth_config(r300);
438 cs_count -= 4;
439 END_CS;
440 }
441
442 void r500_emit_fs_constant_buffer(struct r300_context* r300,
443 struct rc_constant_list* constants)
444 {
445 struct r300_fragment_shader *fs = r300_fs(r300);
446 unsigned i, count = fs->shader->externals_count;
447 CS_LOCALS(r300);
448
449 if (count == 0)
450 return;
451
452 BEGIN_CS(count * 4 + 3);
453 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
454 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
455 for(i = 0; i < count; ++i) {
456 assert(constants->Constants[i].Type == RC_CONSTANT_EXTERNAL);
457 const float *data =
458 r300->shader_constants[PIPE_SHADER_FRAGMENT].constants[i];
459
460 OUT_CS_32F(data[0]);
461 OUT_CS_32F(data[1]);
462 OUT_CS_32F(data[2]);
463 OUT_CS_32F(data[3]);
464 }
465 END_CS;
466 }
467
468 void r500_emit_fs_constant_rc_state(struct r300_context* r300,
469 struct rc_constant_list* constants)
470 {
471 struct r300_fragment_shader *fs = r300_fs(r300);
472 unsigned i;
473 unsigned count = fs->shader->rc_state_count;
474 unsigned first = fs->shader->externals_count;
475 unsigned end = constants->Count;
476 CS_LOCALS(r300);
477
478 if (count == 0)
479 return;
480
481 BEGIN_CS(count * 7);
482 for(i = first; i < end; ++i) {
483 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
484 const float *data = get_shader_constant(r300,
485 &constants->Constants[i], 0);
486
487 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
488 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
489 (i & R500_GA_US_VECTOR_INDEX_MASK));
490 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
491 OUT_CS_32F(data[0]);
492 OUT_CS_32F(data[1]);
493 OUT_CS_32F(data[2]);
494 OUT_CS_32F(data[3]);
495 }
496 }
497 END_CS;
498 }
499
500 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
501 {
502 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
503 struct r300_texture* tex;
504 struct pipe_surface* surf;
505 int i;
506 CS_LOCALS(r300);
507
508 BEGIN_CS(size);
509
510 /* Flush and free renderbuffer caches. */
511 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
512 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
513 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
514 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
515 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
516 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
517
518 /* Set the number of colorbuffers. */
519 if (fb->nr_cbufs > 1) {
520 if (r300->screen->caps.is_r500) {
521 OUT_CS_REG(R300_RB3D_CCTL,
522 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
523 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
524 } else {
525 OUT_CS_REG(R300_RB3D_CCTL,
526 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
527 }
528 } else {
529 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
530 }
531
532 /* Set up colorbuffers. */
533 for (i = 0; i < fb->nr_cbufs; i++) {
534 surf = fb->cbufs[i];
535 tex = r300_texture(surf->texture);
536 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
537
538 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
539 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
540
541 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
542 OUT_CS_TEX_RELOC(tex, tex->fb_state.colorpitch[surf->level],
543 0, RADEON_GEM_DOMAIN_VRAM, 0);
544
545 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
546 }
547 for (; i < 4; i++) {
548 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
549 }
550
551 /* Set up a zbuffer. */
552 if (fb->zsbuf) {
553 surf = fb->zsbuf;
554 tex = r300_texture(surf->texture);
555 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
556
557 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
558 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
559
560 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
561
562 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
563 OUT_CS_TEX_RELOC(tex, tex->fb_state.depthpitch[surf->level],
564 0, RADEON_GEM_DOMAIN_VRAM, 0);
565 }
566
567 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
568 if (r300->screen->caps.is_r500) {
569 OUT_CS(0);
570 OUT_CS(((fb->width - 1) << R300_SCISSORS_X_SHIFT) |
571 ((fb->height - 1) << R300_SCISSORS_Y_SHIFT));
572 } else {
573 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
574 (1440 << R300_SCISSORS_Y_SHIFT));
575 OUT_CS(((fb->width + 1440-1) << R300_SCISSORS_X_SHIFT) |
576 ((fb->height + 1440-1) << R300_SCISSORS_Y_SHIFT));
577 }
578 OUT_CS_REG(R300_GA_POINT_MINMAX,
579 (MAX2(fb->width, fb->height) * 6) << R300_GA_POINT_MINMAX_MAX_SHIFT);
580 END_CS;
581 }
582
583 void r300_emit_query_start(struct r300_context *r300)
584 {
585 struct r300_query *query = r300->query_current;
586 CS_LOCALS(r300);
587
588 if (!query)
589 return;
590
591 BEGIN_CS(4);
592 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
593 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
594 } else {
595 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
596 }
597 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
598 END_CS;
599 query->begin_emitted = TRUE;
600 }
601
602
603 static void r300_emit_query_finish(struct r300_context *r300,
604 struct r300_query *query)
605 {
606 struct r300_capabilities* caps = &r300->screen->caps;
607 CS_LOCALS(r300);
608
609 assert(caps->num_frag_pipes);
610
611 BEGIN_CS(6 * caps->num_frag_pipes + 2);
612 /* I'm not so sure I like this switch, but it's hard to be elegant
613 * when there's so many special cases...
614 *
615 * So here's the basic idea. For each pipe, enable writes to it only,
616 * then put out the relocation for ZPASS_ADDR, taking into account a
617 * 4-byte offset for each pipe. RV380 and older are special; they have
618 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
619 * so there's a chipset cap for that. */
620 switch (caps->num_frag_pipes) {
621 case 4:
622 /* pipe 3 only */
623 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
624 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
625 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
626 0, RADEON_GEM_DOMAIN_GTT, 0);
627 case 3:
628 /* pipe 2 only */
629 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
630 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
631 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
632 0, RADEON_GEM_DOMAIN_GTT, 0);
633 case 2:
634 /* pipe 1 only */
635 /* As mentioned above, accomodate RV380 and older. */
636 OUT_CS_REG(R300_SU_REG_DEST,
637 1 << (caps->high_second_pipe ? 3 : 1));
638 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
639 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
640 0, RADEON_GEM_DOMAIN_GTT, 0);
641 case 1:
642 /* pipe 0 only */
643 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
644 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
645 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
646 0, RADEON_GEM_DOMAIN_GTT, 0);
647 break;
648 default:
649 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
650 " pixel pipes!\n", caps->num_frag_pipes);
651 abort();
652 }
653
654 /* And, finally, reset it to normal... */
655 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
656 END_CS;
657 }
658
659 static void rv530_emit_query_single(struct r300_context *r300,
660 struct r300_query *query)
661 {
662 CS_LOCALS(r300);
663
664 BEGIN_CS(8);
665 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
666 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
667 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
668 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
669 END_CS;
670 }
671
672 static void rv530_emit_query_double(struct r300_context *r300,
673 struct r300_query *query)
674 {
675 CS_LOCALS(r300);
676
677 BEGIN_CS(14);
678 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
679 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
680 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
681 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
682 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
683 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
684 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
685 END_CS;
686 }
687
688 void r300_emit_query_end(struct r300_context* r300)
689 {
690 struct r300_capabilities *caps = &r300->screen->caps;
691 struct r300_query *query = r300->query_current;
692
693 if (!query)
694 return;
695
696 if (query->begin_emitted == FALSE)
697 return;
698
699 if (caps->family == CHIP_FAMILY_RV530) {
700 if (caps->num_z_pipes == 2)
701 rv530_emit_query_double(r300, query);
702 else
703 rv530_emit_query_single(r300, query);
704 } else
705 r300_emit_query_finish(r300, query);
706 }
707
708 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
709 {
710 struct r300_rs_state* rs = (struct r300_rs_state*)state;
711 float scale, offset;
712 CS_LOCALS(r300);
713
714 BEGIN_CS(size);
715 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
716
717 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
718
719 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
720 OUT_CS_REG(R300_GA_LINE_CNTL, rs->line_control);
721
722 if (rs->polygon_offset_enable) {
723 scale = rs->depth_scale * 12;
724 offset = rs->depth_offset;
725
726 switch (r300->zbuffer_bpp) {
727 case 16:
728 offset *= 4;
729 break;
730 case 24:
731 offset *= 2;
732 break;
733 }
734
735 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
736 OUT_CS_32F(scale);
737 OUT_CS_32F(offset);
738 OUT_CS_32F(scale);
739 OUT_CS_32F(offset);
740 }
741
742 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
743 OUT_CS(rs->polygon_offset_enable);
744 OUT_CS(rs->cull_mode);
745 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
746 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
747 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
748 OUT_CS_REG(R300_SC_CLIP_RULE, rs->clip_rule);
749 END_CS;
750 }
751
752 void r300_emit_rs_block_state(struct r300_context* r300,
753 unsigned size, void* state)
754 {
755 struct r300_rs_block* rs = (struct r300_rs_block*)state;
756 unsigned i;
757 /* It's the same for both INST and IP tables */
758 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
759 CS_LOCALS(r300);
760
761 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
762
763 BEGIN_CS(size);
764 if (r300->screen->caps.is_r500) {
765 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
766 } else {
767 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
768 }
769 for (i = 0; i < count; i++) {
770 OUT_CS(rs->ip[i]);
771 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
772 }
773
774 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
775 OUT_CS(rs->count);
776 OUT_CS(rs->inst_count);
777
778 if (r300->screen->caps.is_r500) {
779 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
780 } else {
781 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
782 }
783 for (i = 0; i < count; i++) {
784 OUT_CS(rs->inst[i]);
785 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
786 }
787
788 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
789 rs->count, rs->inst_count);
790
791 END_CS;
792 }
793
794 void r300_emit_scissor_state(struct r300_context* r300,
795 unsigned size, void* state)
796 {
797 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
798 CS_LOCALS(r300);
799
800 BEGIN_CS(size);
801 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
802 if (r300->screen->caps.is_r500) {
803 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
804 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
805 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
806 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
807 } else {
808 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
809 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
810 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
811 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
812 }
813 END_CS;
814 }
815
816 void r300_emit_textures_state(struct r300_context *r300,
817 unsigned size, void *state)
818 {
819 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
820 struct r300_texture_sampler_state *texstate;
821 unsigned i;
822 CS_LOCALS(r300);
823
824 BEGIN_CS(size);
825 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
826
827 for (i = 0; i < allstate->count; i++) {
828 if ((1 << i) & allstate->tx_enable) {
829 texstate = &allstate->regs[i];
830
831 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
832 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
833 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
834 texstate->border_color);
835
836 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
837 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
838 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
839
840 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
841 OUT_CS_TEX_RELOC(r300_texture(allstate->sampler_views[i]->base.texture),
842 texstate->format.tile_config,
843 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
844 }
845 }
846 END_CS;
847 }
848
849 void r300_emit_aos(struct r300_context* r300, unsigned offset)
850 {
851 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
852 struct pipe_vertex_element *velem = r300->velems->velem;
853 int i;
854 unsigned size1, size2, aos_count = r300->velems->count;
855 unsigned packet_size = (aos_count * 3 + 1) / 2;
856 CS_LOCALS(r300);
857
858 BEGIN_CS(2 + packet_size + aos_count * 2);
859 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
860 OUT_CS(aos_count);
861
862 for (i = 0; i < aos_count - 1; i += 2) {
863 vb1 = &vbuf[velem[i].vertex_buffer_index];
864 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
865 size1 = util_format_get_blocksize(velem[i].src_format);
866 size2 = util_format_get_blocksize(velem[i+1].src_format);
867
868 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
869 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
870 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
871 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
872 }
873
874 if (aos_count & 1) {
875 vb1 = &vbuf[velem[i].vertex_buffer_index];
876 size1 = util_format_get_blocksize(velem[i].src_format);
877
878 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
879 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
880 }
881
882 for (i = 0; i < aos_count; i++) {
883 OUT_CS_BUF_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
884 RADEON_GEM_DOMAIN_GTT, 0, 0);
885 }
886 END_CS;
887 }
888
889 void r300_emit_vertex_buffer(struct r300_context* r300)
890 {
891 CS_LOCALS(r300);
892
893 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
894 "vertex size %d\n", r300->vbo,
895 r300->vertex_info.size);
896 /* Set the pointer to our vertex buffer. The emitted values are this:
897 * PACKET3 [3D_LOAD_VBPNTR]
898 * COUNT [1]
899 * FORMAT [size | stride << 8]
900 * OFFSET [offset into BO]
901 * VBPNTR [relocated BO]
902 */
903 BEGIN_CS(7);
904 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
905 OUT_CS(1);
906 OUT_CS(r300->vertex_info.size |
907 (r300->vertex_info.size << 8));
908 OUT_CS(r300->vbo_offset);
909 OUT_CS_BUF_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
910 END_CS;
911 }
912
913 void r300_emit_vertex_stream_state(struct r300_context* r300,
914 unsigned size, void* state)
915 {
916 struct r300_vertex_stream_state *streams =
917 (struct r300_vertex_stream_state*)state;
918 unsigned i;
919 CS_LOCALS(r300);
920
921 DBG(r300, DBG_DRAW, "r300: PSC emit:\n");
922
923 BEGIN_CS(size);
924 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
925 for (i = 0; i < streams->count; i++) {
926 OUT_CS(streams->vap_prog_stream_cntl[i]);
927 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
928 streams->vap_prog_stream_cntl[i]);
929 }
930 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
931 for (i = 0; i < streams->count; i++) {
932 OUT_CS(streams->vap_prog_stream_cntl_ext[i]);
933 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
934 streams->vap_prog_stream_cntl_ext[i]);
935 }
936 END_CS;
937 }
938
939 void r300_emit_vap_output_state(struct r300_context* r300,
940 unsigned size, void* state)
941 {
942 struct r300_vap_output_state *vap_out_state =
943 (struct r300_vap_output_state*)state;
944 CS_LOCALS(r300);
945
946 DBG(r300, DBG_DRAW, "r300: VAP emit:\n");
947
948 BEGIN_CS(size);
949 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
950 OUT_CS(vap_out_state->vap_vtx_state_cntl);
951 OUT_CS(vap_out_state->vap_vsm_vtx_assm);
952 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
953 OUT_CS(vap_out_state->vap_out_vtx_fmt[0]);
954 OUT_CS(vap_out_state->vap_out_vtx_fmt[1]);
955 END_CS;
956 }
957
958 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
959 {
960 CS_LOCALS(r300);
961
962 BEGIN_CS(size);
963 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
964 END_CS;
965 }
966
967 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
968 {
969 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
970 struct r300_vertex_program_code* code = &vs->code;
971 struct r300_screen* r300screen = r300->screen;
972 unsigned instruction_count = code->length / 4;
973 unsigned i;
974
975 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
976 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
977 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
978 unsigned temp_count = MAX2(code->num_temporaries, 1);
979
980 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
981 vtx_mem_size / output_count, 10);
982 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
983
984 CS_LOCALS(r300);
985
986 BEGIN_CS(size);
987 /* R300_VAP_PVS_CODE_CNTL_0
988 * R300_VAP_PVS_CONST_CNTL
989 * R300_VAP_PVS_CODE_CNTL_1
990 * See the r5xx docs for instructions on how to use these. */
991 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
992 OUT_CS(R300_PVS_FIRST_INST(0) |
993 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
994 R300_PVS_LAST_INST(instruction_count - 1));
995 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
996 OUT_CS(instruction_count - 1);
997
998 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
999 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
1000 for (i = 0; i < code->length; i++) {
1001 OUT_CS(code->body.d[i]);
1002 }
1003
1004 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
1005 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
1006 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
1007 R300_PVS_VF_MAX_VTX_NUM(12) |
1008 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
1009 END_CS;
1010 }
1011
1012 void r300_emit_vs_constant_buffer(struct r300_context* r300,
1013 struct rc_constant_list* constants)
1014 {
1015 unsigned i;
1016 CS_LOCALS(r300);
1017
1018 BEGIN_CS(constants->Count * 4 + 3);
1019 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1020 (r300->screen->caps.is_r500 ?
1021 R500_PVS_CONST_START : R300_PVS_CONST_START));
1022 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
1023 for (i = 0; i < constants->Count; i++) {
1024 const float *data = get_shader_constant(r300,
1025 &constants->Constants[i],
1026 &r300->shader_constants[PIPE_SHADER_VERTEX]);
1027 OUT_CS_32F(data[0]);
1028 OUT_CS_32F(data[1]);
1029 OUT_CS_32F(data[2]);
1030 OUT_CS_32F(data[3]);
1031 }
1032 END_CS;
1033 }
1034
1035 void r300_emit_viewport_state(struct r300_context* r300,
1036 unsigned size, void* state)
1037 {
1038 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1039 CS_LOCALS(r300);
1040
1041 BEGIN_CS(size);
1042 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1043 OUT_CS_32F(viewport->xscale);
1044 OUT_CS_32F(viewport->xoffset);
1045 OUT_CS_32F(viewport->yscale);
1046 OUT_CS_32F(viewport->yoffset);
1047 OUT_CS_32F(viewport->zscale);
1048 OUT_CS_32F(viewport->zoffset);
1049 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1050 END_CS;
1051 }
1052
1053 void r300_emit_ztop_state(struct r300_context* r300,
1054 unsigned size, void* state)
1055 {
1056 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1057 CS_LOCALS(r300);
1058
1059 BEGIN_CS(size);
1060 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1061 END_CS;
1062 }
1063
1064 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1065 {
1066 CS_LOCALS(r300);
1067
1068 BEGIN_CS(size);
1069 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1070 END_CS;
1071 }
1072
1073 void r300_emit_buffer_validate(struct r300_context *r300,
1074 boolean do_validate_vertex_buffers,
1075 struct pipe_resource *index_buffer)
1076 {
1077 struct pipe_framebuffer_state* fb =
1078 (struct pipe_framebuffer_state*)r300->fb_state.state;
1079 struct r300_textures_state *texstate =
1080 (struct r300_textures_state*)r300->textures_state.state;
1081 struct r300_texture* tex;
1082 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1083 struct pipe_vertex_element *velem = r300->velems->velem;
1084 struct pipe_resource *pbuf;
1085 unsigned i;
1086 boolean invalid = FALSE;
1087
1088 /* upload buffers first */
1089 if (r300->any_user_vbs) {
1090 r300_upload_user_buffers(r300);
1091 r300->any_user_vbs = false;
1092 }
1093
1094 /* Clean out BOs. */
1095 r300->rws->reset_bos(r300->rws);
1096
1097 validate:
1098 /* Color buffers... */
1099 for (i = 0; i < fb->nr_cbufs; i++) {
1100 tex = r300_texture(fb->cbufs[i]->texture);
1101 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1102 if (!r300_add_texture(r300->rws, tex,
1103 0, RADEON_GEM_DOMAIN_VRAM)) {
1104 r300->context.flush(&r300->context, 0, NULL);
1105 goto validate;
1106 }
1107 }
1108 /* ...depth buffer... */
1109 if (fb->zsbuf) {
1110 tex = r300_texture(fb->zsbuf->texture);
1111 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1112 if (!r300_add_texture(r300->rws, tex,
1113 0, RADEON_GEM_DOMAIN_VRAM)) {
1114 r300->context.flush(&r300->context, 0, NULL);
1115 goto validate;
1116 }
1117 }
1118 /* ...textures... */
1119 for (i = 0; i < texstate->count; i++) {
1120 if (!(texstate->tx_enable & (1 << i))) {
1121 continue;
1122 }
1123
1124 tex = r300_texture(texstate->sampler_views[i]->base.texture);
1125 if (!r300_add_texture(r300->rws, tex,
1126 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1127 r300->context.flush(&r300->context, 0, NULL);
1128 goto validate;
1129 }
1130 }
1131 /* ...occlusion query buffer... */
1132 if (r300->dirty_state & R300_NEW_QUERY) {
1133 if (!r300_add_buffer(r300->rws, r300->oqbo,
1134 0, RADEON_GEM_DOMAIN_GTT)) {
1135 r300->context.flush(&r300->context, 0, NULL);
1136 goto validate;
1137 }
1138 }
1139 /* ...vertex buffer for SWTCL path... */
1140 if (r300->vbo) {
1141 if (!r300_add_buffer(r300->rws, r300->vbo,
1142 RADEON_GEM_DOMAIN_GTT, 0)) {
1143 r300->context.flush(&r300->context, 0, NULL);
1144 goto validate;
1145 }
1146 }
1147 /* ...vertex buffers for HWTCL path... */
1148 if (do_validate_vertex_buffers) {
1149 for (i = 0; i < r300->velems->count; i++) {
1150 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1151
1152 if (!r300_add_buffer(r300->rws, pbuf,
1153 RADEON_GEM_DOMAIN_GTT, 0)) {
1154 r300->context.flush(&r300->context, 0, NULL);
1155 goto validate;
1156 }
1157 }
1158 }
1159 /* ...and index buffer for HWTCL path. */
1160 if (index_buffer) {
1161 if (!r300_add_buffer(r300->rws, index_buffer,
1162 RADEON_GEM_DOMAIN_GTT, 0)) {
1163 r300->context.flush(&r300->context, 0, NULL);
1164 goto validate;
1165 }
1166 }
1167 if (!r300->rws->validate(r300->rws)) {
1168 r300->context.flush(&r300->context, 0, NULL);
1169 if (invalid) {
1170 /* Well, hell. */
1171 fprintf(stderr, "r300: Stuck in validation loop, gonna quit now.\n");
1172 abort();
1173 }
1174 invalid = TRUE;
1175 goto validate;
1176 }
1177 }
1178
1179 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1180 {
1181 struct r300_atom* atom;
1182 unsigned dwords = 0;
1183
1184 foreach(atom, &r300->atom_list) {
1185 if (atom->dirty || atom->always_dirty) {
1186 dwords += atom->size;
1187 }
1188 }
1189
1190 /* XXX This is the compensation for the non-atomized states. */
1191 dwords += 1024;
1192
1193 return dwords;
1194 }
1195
1196 /* Emit all dirty state. */
1197 void r300_emit_dirty_state(struct r300_context* r300)
1198 {
1199 struct r300_screen* r300screen = r300->screen;
1200 struct r300_atom* atom;
1201
1202 if (r300->dirty_state & R300_NEW_QUERY) {
1203 r300_emit_query_start(r300);
1204 r300->dirty_state &= ~R300_NEW_QUERY;
1205 }
1206
1207 foreach(atom, &r300->atom_list) {
1208 if (atom->dirty || atom->always_dirty) {
1209 atom->emit(r300, atom->size, atom->state);
1210 atom->dirty = FALSE;
1211 }
1212 }
1213
1214 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1215 if (r300screen->caps.is_r500) {
1216 r500_emit_fs_constant_buffer(r300,
1217 &r300_fs(r300)->shader->code.constants);
1218 r500_emit_fs_constant_rc_state(r300,
1219 &r300_fs(r300)->shader->code.constants);
1220 } else {
1221 r300_emit_fs_constant_buffer(r300,
1222 &r300_fs(r300)->shader->code.constants);
1223 r300_emit_fs_constant_rc_state(r300,
1224 &r300_fs(r300)->shader->code.constants);
1225 }
1226 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1227 }
1228
1229 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1230 struct r300_vertex_shader* vs = r300->vs_state.state;
1231 if (vs->code.constants.Count) {
1232 r300_emit_vs_constant_buffer(r300, &vs->code.constants);
1233 }
1234 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1235 }
1236
1237 /* Emit the VBO for SWTCL. */
1238 if (!r300screen->caps.has_tcl) {
1239 r300_emit_vertex_buffer(r300);
1240 }
1241
1242 r300->dirty_hw++;
1243 }