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r300g: add WPOS
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28
29 #include "r300_context.h"
30 #include "r300_cs.h"
31 #include "r300_emit.h"
32 #include "r300_fs.h"
33 #include "r300_screen.h"
34 #include "r300_state_derived.h"
35 #include "r300_state_inlines.h"
36 #include "r300_texture.h"
37 #include "r300_vs.h"
38
39 void r300_emit_blend_state(struct r300_context* r300,
40 struct r300_blend_state* blend)
41 {
42 CS_LOCALS(r300);
43 BEGIN_CS(8);
44 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
45 if (r300->framebuffer_state.nr_cbufs) {
46 OUT_CS(blend->blend_control);
47 OUT_CS(blend->alpha_blend_control);
48 OUT_CS(blend->color_channel_mask);
49 } else {
50 OUT_CS(0);
51 OUT_CS(0);
52 OUT_CS(0);
53 /* XXX also disable fastfill here once it's supported */
54 }
55 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
56 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
57 END_CS;
58 }
59
60 void r300_emit_blend_color_state(struct r300_context* r300,
61 struct r300_blend_color_state* bc)
62 {
63 struct r300_screen* r300screen = r300_screen(r300->context.screen);
64 CS_LOCALS(r300);
65
66 if (r300screen->caps->is_r500) {
67 BEGIN_CS(3);
68 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
69 OUT_CS(bc->blend_color_red_alpha);
70 OUT_CS(bc->blend_color_green_blue);
71 END_CS;
72 } else {
73 BEGIN_CS(2);
74 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
75 END_CS;
76 }
77 }
78
79 void r300_emit_clip_state(struct r300_context* r300,
80 struct pipe_clip_state* clip)
81 {
82 int i;
83 struct r300_screen* r300screen = r300_screen(r300->context.screen);
84 CS_LOCALS(r300);
85
86 if (r300screen->caps->has_tcl) {
87 BEGIN_CS(5 + (6 * 4));
88 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
89 (r300screen->caps->is_r500 ?
90 R500_PVS_UCP_START : R300_PVS_UCP_START));
91 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
92 for (i = 0; i < 6; i++) {
93 OUT_CS_32F(clip->ucp[i][0]);
94 OUT_CS_32F(clip->ucp[i][1]);
95 OUT_CS_32F(clip->ucp[i][2]);
96 OUT_CS_32F(clip->ucp[i][3]);
97 }
98 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
99 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
100 END_CS;
101 } else {
102 BEGIN_CS(2);
103 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
104 END_CS;
105 }
106
107 }
108
109 void r300_emit_dsa_state(struct r300_context* r300,
110 struct r300_dsa_state* dsa)
111 {
112 struct r300_screen* r300screen = r300_screen(r300->context.screen);
113 CS_LOCALS(r300);
114
115 BEGIN_CS(r300screen->caps->is_r500 ? 10 : 8);
116 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
117
118 /* not needed since we use the 8bit alpha ref */
119 /*if (r300screen->caps->is_r500) {
120 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
121 }*/
122
123 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
124 OUT_CS(dsa->z_buffer_control);
125 OUT_CS(dsa->z_stencil_control);
126 OUT_CS(dsa->stencil_ref_mask);
127 OUT_CS_REG(R300_ZB_ZTOP, r300->ztop_state.z_buffer_top);
128
129 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
130 if (r300screen->caps->is_r500) {
131 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
132 }
133 END_CS;
134 }
135
136 static const float * get_shader_constant(
137 struct r300_context * r300,
138 struct rc_constant * constant,
139 struct r300_constant_buffer * externals)
140 {
141 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
142 struct pipe_texture *tex;
143
144 switch(constant->Type) {
145 case RC_CONSTANT_EXTERNAL:
146 return externals->constants[constant->u.External];
147
148 case RC_CONSTANT_IMMEDIATE:
149 return constant->u.Immediate;
150
151 case RC_CONSTANT_STATE:
152 switch (constant->u.State[0]) {
153 /* Factor for converting rectangle coords to
154 * normalized coords. Should only show up on non-r500. */
155 case RC_STATE_R300_TEXRECT_FACTOR:
156 tex = &r300->textures[constant->u.State[1]]->tex;
157 vec[0] = 1.0 / tex->width0;
158 vec[1] = 1.0 / tex->height0;
159 break;
160
161 /* Texture compare-fail value. */
162 /* XXX Since Gallium doesn't support GL_ARB_shadow_ambient,
163 * this is always (0,0,0,0). */
164 case RC_STATE_SHADOW_AMBIENT:
165 vec[3] = 0;
166 break;
167
168 case RC_STATE_R300_VIEWPORT_SCALE:
169 if (r300->rs_state->enable_vte) {
170 vec[0] = r300->viewport_state->xscale;
171 vec[1] = r300->viewport_state->yscale;
172 vec[2] = r300->viewport_state->zscale;
173 } else {
174 vec[0] = 1;
175 vec[1] = 1;
176 vec[2] = 1;
177 }
178 break;
179
180 case RC_STATE_R300_VIEWPORT_OFFSET:
181 if (r300->rs_state->enable_vte) {
182 vec[0] = r300->viewport_state->xoffset;
183 vec[1] = r300->viewport_state->yoffset;
184 vec[2] = r300->viewport_state->zoffset;
185 } else {
186 /* Zeros. */
187 }
188 break;
189
190 default:
191 debug_printf("r300: Implementation error: "
192 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
193 }
194 break;
195
196 default:
197 debug_printf("r300: Implementation error: "
198 "Unhandled constant type %d\n", constant->Type);
199 }
200
201 /* This should either be (0, 0, 0, 1), which should be a relatively safe
202 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
203 * state factors. */
204 return vec;
205 }
206
207 /* Convert a normal single-precision float into the 7.16 format
208 * used by the R300 fragment shader.
209 */
210 static uint32_t pack_float24(float f)
211 {
212 union {
213 float fl;
214 uint32_t u;
215 } u;
216 float mantissa;
217 int exponent;
218 uint32_t float24 = 0;
219
220 if (f == 0.0)
221 return 0;
222
223 u.fl = f;
224
225 mantissa = frexpf(f, &exponent);
226
227 /* Handle -ve */
228 if (mantissa < 0) {
229 float24 |= (1 << 23);
230 mantissa = mantissa * -1.0;
231 }
232 /* Handle exponent, bias of 63 */
233 exponent += 62;
234 float24 |= (exponent << 16);
235 /* Kill 7 LSB of mantissa */
236 float24 |= (u.u & 0x7FFFFF) >> 7;
237
238 return float24;
239 }
240
241 void r300_emit_fragment_program_code(struct r300_context* r300,
242 struct rX00_fragment_program_code* generic_code)
243 {
244 struct r300_fragment_program_code * code = &generic_code->code.r300;
245 int i;
246 CS_LOCALS(r300);
247
248 BEGIN_CS(15 +
249 code->alu.length * 4 +
250 (code->tex.length ? (1 + code->tex.length) : 0));
251
252 OUT_CS_REG(R300_US_CONFIG, code->config);
253 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
254 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
255
256 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
257 for(i = 0; i < 4; ++i)
258 OUT_CS(code->code_addr[i]);
259
260 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
261 for (i = 0; i < code->alu.length; i++)
262 OUT_CS(code->alu.inst[i].rgb_inst);
263
264 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
265 for (i = 0; i < code->alu.length; i++)
266 OUT_CS(code->alu.inst[i].rgb_addr);
267
268 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
269 for (i = 0; i < code->alu.length; i++)
270 OUT_CS(code->alu.inst[i].alpha_inst);
271
272 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
273 for (i = 0; i < code->alu.length; i++)
274 OUT_CS(code->alu.inst[i].alpha_addr);
275
276 if (code->tex.length) {
277 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
278 for(i = 0; i < code->tex.length; ++i)
279 OUT_CS(code->tex.inst[i]);
280 }
281
282 END_CS;
283 }
284
285 void r300_emit_fs_constant_buffer(struct r300_context* r300,
286 struct rc_constant_list* constants)
287 {
288 int i;
289 CS_LOCALS(r300);
290
291 if (constants->Count == 0)
292 return;
293
294 BEGIN_CS(constants->Count * 4 + 1);
295 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
296 for(i = 0; i < constants->Count; ++i) {
297 const float * data = get_shader_constant(r300,
298 &constants->Constants[i],
299 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
300 OUT_CS(pack_float24(data[0]));
301 OUT_CS(pack_float24(data[1]));
302 OUT_CS(pack_float24(data[2]));
303 OUT_CS(pack_float24(data[3]));
304 }
305 END_CS;
306 }
307
308 static void r300_emit_fragment_depth_config(struct r300_context* r300,
309 struct r300_fragment_shader* fs)
310 {
311 CS_LOCALS(r300);
312
313 BEGIN_CS(4);
314 if (r300_fragment_shader_writes_depth(fs)) {
315 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
316 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
317 } else {
318 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
319 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
320 }
321 END_CS;
322 }
323
324 void r500_emit_fragment_program_code(struct r300_context* r300,
325 struct rX00_fragment_program_code* generic_code)
326 {
327 struct r500_fragment_program_code * code = &generic_code->code.r500;
328 int i;
329 CS_LOCALS(r300);
330
331 BEGIN_CS(13 +
332 ((code->inst_end + 1) * 6));
333 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
334 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
335 OUT_CS_REG(R500_US_CODE_RANGE,
336 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
337 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
338 OUT_CS_REG(R500_US_CODE_ADDR,
339 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
340
341 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
342 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
343 for (i = 0; i <= code->inst_end; i++) {
344 OUT_CS(code->inst[i].inst0);
345 OUT_CS(code->inst[i].inst1);
346 OUT_CS(code->inst[i].inst2);
347 OUT_CS(code->inst[i].inst3);
348 OUT_CS(code->inst[i].inst4);
349 OUT_CS(code->inst[i].inst5);
350 }
351
352 END_CS;
353 }
354
355 void r500_emit_fs_constant_buffer(struct r300_context* r300,
356 struct rc_constant_list* constants)
357 {
358 int i;
359 CS_LOCALS(r300);
360
361 if (constants->Count == 0)
362 return;
363
364 BEGIN_CS(constants->Count * 4 + 3);
365 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
366 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
367 for (i = 0; i < constants->Count; i++) {
368 const float * data = get_shader_constant(r300,
369 &constants->Constants[i],
370 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
371 OUT_CS_32F(data[0]);
372 OUT_CS_32F(data[1]);
373 OUT_CS_32F(data[2]);
374 OUT_CS_32F(data[3]);
375 }
376 END_CS;
377 }
378
379 void r300_emit_fb_state(struct r300_context* r300,
380 struct pipe_framebuffer_state* fb)
381 {
382 struct r300_texture* tex;
383 struct pipe_surface* surf;
384 int i;
385 CS_LOCALS(r300);
386
387 /* Shouldn't fail unless there is a bug in the state tracker. */
388 assert(fb->nr_cbufs <= 4);
389
390 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
391 (fb->zsbuf ? 10 : 0) + 6);
392
393 /* Flush and free renderbuffer caches. */
394 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
395 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
396 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
397 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
398 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
399 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
400
401 /* Set the number of colorbuffers. */
402 OUT_CS_REG(R300_RB3D_CCTL, R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
403
404 /* Set up colorbuffers. */
405 for (i = 0; i < fb->nr_cbufs; i++) {
406 surf = fb->cbufs[i];
407 tex = (struct r300_texture*)surf->texture;
408 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
409
410 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
411 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
412
413 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
414 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
415 r300_translate_colorformat(tex->tex.format), 0,
416 RADEON_GEM_DOMAIN_VRAM, 0);
417
418 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
419 r300_translate_out_fmt(surf->format));
420 }
421
422 /* Disable unused colorbuffers. */
423 for (; i < 4; i++) {
424 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
425 }
426
427 /* Set up a zbuffer. */
428 if (fb->zsbuf) {
429 surf = fb->zsbuf;
430 tex = (struct r300_texture*)surf->texture;
431 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
432
433 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
434 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
435
436 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
437
438 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
439 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level], 0,
440 RADEON_GEM_DOMAIN_VRAM, 0);
441 }
442
443 END_CS;
444 }
445
446 static void r300_emit_query_start(struct r300_context *r300)
447 {
448 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
449 struct r300_query *query = r300->query_current;
450 CS_LOCALS(r300);
451
452 if (!query)
453 return;
454
455 BEGIN_CS(4);
456 if (caps->family == CHIP_FAMILY_RV530) {
457 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
458 } else {
459 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
460 }
461 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
462 END_CS;
463 query->begin_emitted = TRUE;
464 }
465
466
467 static void r300_emit_query_finish(struct r300_context *r300,
468 struct r300_query *query)
469 {
470 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
471 CS_LOCALS(r300);
472
473 assert(caps->num_frag_pipes);
474
475 BEGIN_CS(6 * caps->num_frag_pipes + 2);
476 /* I'm not so sure I like this switch, but it's hard to be elegant
477 * when there's so many special cases...
478 *
479 * So here's the basic idea. For each pipe, enable writes to it only,
480 * then put out the relocation for ZPASS_ADDR, taking into account a
481 * 4-byte offset for each pipe. RV380 and older are special; they have
482 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
483 * so there's a chipset cap for that. */
484 switch (caps->num_frag_pipes) {
485 case 4:
486 /* pipe 3 only */
487 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
488 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
489 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
490 0, RADEON_GEM_DOMAIN_GTT, 0);
491 case 3:
492 /* pipe 2 only */
493 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
494 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
495 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
496 0, RADEON_GEM_DOMAIN_GTT, 0);
497 case 2:
498 /* pipe 1 only */
499 /* As mentioned above, accomodate RV380 and older. */
500 OUT_CS_REG(R300_SU_REG_DEST,
501 1 << (caps->high_second_pipe ? 3 : 1));
502 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
503 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
504 0, RADEON_GEM_DOMAIN_GTT, 0);
505 case 1:
506 /* pipe 0 only */
507 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
508 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
509 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
510 0, RADEON_GEM_DOMAIN_GTT, 0);
511 break;
512 default:
513 debug_printf("r300: Implementation error: Chipset reports %d"
514 " pixel pipes!\n", caps->num_frag_pipes);
515 assert(0);
516 }
517
518 /* And, finally, reset it to normal... */
519 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
520 END_CS;
521 }
522
523 static void rv530_emit_query_single(struct r300_context *r300,
524 struct r300_query *query)
525 {
526 CS_LOCALS(r300);
527
528 BEGIN_CS(8);
529 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
530 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
531 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
532 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
533 END_CS;
534 }
535
536 static void rv530_emit_query_double(struct r300_context *r300,
537 struct r300_query *query)
538 {
539 CS_LOCALS(r300);
540
541 BEGIN_CS(14);
542 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
543 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
544 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
545 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
546 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
547 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
548 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
549 END_CS;
550 }
551
552 void r300_emit_query_end(struct r300_context* r300)
553 {
554 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
555 struct r300_query *query = r300->query_current;
556
557 if (!query)
558 return;
559
560 if (query->begin_emitted == FALSE)
561 return;
562
563 if (caps->family == CHIP_FAMILY_RV530) {
564 if (caps->num_z_pipes == 2)
565 rv530_emit_query_double(r300, query);
566 else
567 rv530_emit_query_single(r300, query);
568 } else
569 r300_emit_query_finish(r300, query);
570 }
571
572 void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs)
573 {
574 CS_LOCALS(r300);
575
576 BEGIN_CS(22);
577 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
578 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
579 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
580 OUT_CS(rs->point_minmax);
581 OUT_CS(rs->line_control);
582 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
583 OUT_CS(rs->depth_scale_front);
584 OUT_CS(rs->depth_offset_front);
585 OUT_CS(rs->depth_scale_back);
586 OUT_CS(rs->depth_offset_back);
587 OUT_CS(rs->polygon_offset_enable);
588 OUT_CS(rs->cull_mode);
589 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
590 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
591 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
592 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
593 END_CS;
594 }
595
596 void r300_emit_rs_block_state(struct r300_context* r300,
597 struct r300_rs_block* rs)
598 {
599 int i;
600 struct r300_screen* r300screen = r300_screen(r300->context.screen);
601 CS_LOCALS(r300);
602
603 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
604
605 BEGIN_CS(21);
606 if (r300screen->caps->is_r500) {
607 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
608 } else {
609 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
610 }
611 for (i = 0; i < 8; i++) {
612 OUT_CS(rs->ip[i]);
613 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
614 }
615
616 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
617 OUT_CS(rs->count);
618 OUT_CS(rs->inst_count);
619
620 if (r300screen->caps->is_r500) {
621 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
622 } else {
623 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
624 }
625 for (i = 0; i < 8; i++) {
626 OUT_CS(rs->inst[i]);
627 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
628 }
629
630 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
631 rs->count, rs->inst_count);
632
633 END_CS;
634 }
635
636 static void r300_emit_scissor_regs(struct r300_context* r300,
637 struct r300_scissor_regs* scissor)
638 {
639 CS_LOCALS(r300);
640
641 BEGIN_CS(3);
642 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
643 OUT_CS(scissor->top_left);
644 OUT_CS(scissor->bottom_right);
645 END_CS;
646 }
647
648 void r300_emit_scissor_state(struct r300_context* r300,
649 struct r300_scissor_state* scissor)
650 {
651 if (r300->rs_state->rs.scissor) {
652 r300_emit_scissor_regs(r300, &scissor->scissor);
653 } else {
654 r300_emit_scissor_regs(r300, &scissor->framebuffer);
655 }
656 }
657
658 void r300_emit_texture(struct r300_context* r300,
659 struct r300_sampler_state* sampler,
660 struct r300_texture* tex,
661 unsigned offset)
662 {
663 uint32_t filter0 = sampler->filter0;
664 uint32_t format0 = tex->state.format0;
665 unsigned min_level, max_level;
666 CS_LOCALS(r300);
667
668 /* to emulate 1D textures through 2D ones correctly */
669 if (tex->tex.target == PIPE_TEXTURE_1D) {
670 filter0 &= ~R300_TX_WRAP_T_MASK;
671 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
672 }
673
674 /* determine min/max levels */
675 /* the MAX_MIP level is the largest (finest) one */
676 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
677 min_level = MIN2(sampler->min_lod, max_level);
678 format0 |= R300_TX_NUM_LEVELS(max_level);
679 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
680
681 BEGIN_CS(16);
682 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
683 (offset << 28));
684 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
685 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
686
687 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
688 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
689 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
690 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
691 OUT_CS_RELOC(tex->buffer, 0,
692 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
693 END_CS;
694 }
695
696 static boolean r300_validate_aos(struct r300_context *r300)
697 {
698 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
699 struct pipe_vertex_element *velem = r300->vertex_element;
700 int i;
701
702 /* Check if formats and strides are aligned to the size of DWORD. */
703 for (i = 0; i < r300->vertex_element_count; i++) {
704 if (vbuf[velem[i].vertex_buffer_index].stride % 4 != 0 ||
705 util_format_get_blocksize(velem[i].src_format) % 4 != 0) {
706 return FALSE;
707 }
708 }
709 return TRUE;
710 }
711
712 void r300_emit_aos(struct r300_context* r300, unsigned offset)
713 {
714 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
715 struct pipe_vertex_element *velem = r300->vertex_element;
716 int i;
717 unsigned size1, size2, aos_count = r300->vertex_element_count;
718 unsigned packet_size = (aos_count * 3 + 1) / 2;
719 CS_LOCALS(r300);
720
721 /* XXX Move this checking to a more approriate place. */
722 if (!r300_validate_aos(r300)) {
723 /* XXX We should fallback using Draw. */
724 assert(0);
725 }
726
727 BEGIN_CS(2 + packet_size + aos_count * 2);
728 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
729 OUT_CS(aos_count);
730
731 for (i = 0; i < aos_count - 1; i += 2) {
732 vb1 = &vbuf[velem[i].vertex_buffer_index];
733 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
734 size1 = util_format_get_blocksize(velem[i].src_format);
735 size2 = util_format_get_blocksize(velem[i+1].src_format);
736
737 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
738 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
739 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
740 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
741 }
742
743 if (aos_count & 1) {
744 vb1 = &vbuf[velem[i].vertex_buffer_index];
745 size1 = util_format_get_blocksize(velem[i].src_format);
746
747 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
748 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
749 }
750
751 for (i = 0; i < aos_count; i++) {
752 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
753 RADEON_GEM_DOMAIN_GTT, 0, 0);
754 }
755 END_CS;
756 }
757
758 #if 0
759 void r300_emit_draw_packet(struct r300_context* r300)
760 {
761 CS_LOCALS(r300);
762
763 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
764 "vertex size %d\n", r300->vbo,
765 r300->vertex_info->vinfo.size);
766 /* Set the pointer to our vertex buffer. The emitted values are this:
767 * PACKET3 [3D_LOAD_VBPNTR]
768 * COUNT [1]
769 * FORMAT [size | stride << 8]
770 * OFFSET [offset into BO]
771 * VBPNTR [relocated BO]
772 */
773 BEGIN_CS(7);
774 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
775 OUT_CS(1);
776 OUT_CS(r300->vertex_info->vinfo.size |
777 (r300->vertex_info->vinfo.size << 8));
778 OUT_CS(r300->vbo_offset);
779 OUT_CS_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
780 END_CS;
781 }
782 #endif
783
784 void r300_emit_vertex_format_state(struct r300_context* r300)
785 {
786 int i;
787 CS_LOCALS(r300);
788
789 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
790
791 BEGIN_CS(26);
792 OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info->vinfo.size);
793
794 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
795 OUT_CS(r300->vertex_info->vinfo.hwfmt[0]);
796 OUT_CS(r300->vertex_info->vinfo.hwfmt[1]);
797 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
798 OUT_CS(r300->vertex_info->vinfo.hwfmt[2]);
799 OUT_CS(r300->vertex_info->vinfo.hwfmt[3]);
800 for (i = 0; i < 4; i++) {
801 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
802 r300->vertex_info->vinfo.hwfmt[i]);
803 }
804
805 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
806 for (i = 0; i < 8; i++) {
807 OUT_CS(r300->vertex_info->vap_prog_stream_cntl[i]);
808 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
809 r300->vertex_info->vap_prog_stream_cntl[i]);
810 }
811 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
812 for (i = 0; i < 8; i++) {
813 OUT_CS(r300->vertex_info->vap_prog_stream_cntl_ext[i]);
814 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
815 r300->vertex_info->vap_prog_stream_cntl_ext[i]);
816 }
817 END_CS;
818 }
819
820
821 void r300_emit_vertex_program_code(struct r300_context* r300,
822 struct r300_vertex_program_code* code)
823 {
824 int i;
825 struct r300_screen* r300screen = r300_screen(r300->context.screen);
826 unsigned instruction_count = code->length / 4;
827
828 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
829 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
830 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
831 int temp_count = MAX2(code->num_temporaries, 1);
832 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
833 vtx_mem_size / output_count, 10);
834 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
835
836 CS_LOCALS(r300);
837
838 if (!r300screen->caps->has_tcl) {
839 debug_printf("r300: Implementation error: emit_vertex_shader called,"
840 " but has_tcl is FALSE!\n");
841 return;
842 }
843
844 BEGIN_CS(9 + code->length);
845 /* R300_VAP_PVS_CODE_CNTL_0
846 * R300_VAP_PVS_CONST_CNTL
847 * R300_VAP_PVS_CODE_CNTL_1
848 * See the r5xx docs for instructions on how to use these. */
849 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
850 OUT_CS(R300_PVS_FIRST_INST(0) |
851 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
852 R300_PVS_LAST_INST(instruction_count - 1));
853 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
854 OUT_CS(instruction_count - 1);
855
856 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
857 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
858 for (i = 0; i < code->length; i++)
859 OUT_CS(code->body.d[i]);
860
861 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
862 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
863 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
864 R300_PVS_VF_MAX_VTX_NUM(12) |
865 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
866 END_CS;
867 }
868
869 void r300_emit_vertex_shader(struct r300_context* r300,
870 struct r300_vertex_shader* vs)
871 {
872 r300_emit_vertex_program_code(r300, &vs->code);
873 }
874
875 void r300_emit_vs_constant_buffer(struct r300_context* r300,
876 struct rc_constant_list* constants)
877 {
878 int i;
879 struct r300_screen* r300screen = r300_screen(r300->context.screen);
880 CS_LOCALS(r300);
881
882 if (!r300screen->caps->has_tcl) {
883 debug_printf("r300: Implementation error: emit_vertex_shader called,"
884 " but has_tcl is FALSE!\n");
885 return;
886 }
887
888 if (constants->Count == 0)
889 return;
890
891 BEGIN_CS(constants->Count * 4 + 3);
892 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
893 (r300screen->caps->is_r500 ?
894 R500_PVS_CONST_START : R300_PVS_CONST_START));
895 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
896 for (i = 0; i < constants->Count; i++) {
897 const float * data = get_shader_constant(r300,
898 &constants->Constants[i],
899 &r300->shader_constants[PIPE_SHADER_VERTEX]);
900 OUT_CS_32F(data[0]);
901 OUT_CS_32F(data[1]);
902 OUT_CS_32F(data[2]);
903 OUT_CS_32F(data[3]);
904 }
905 END_CS;
906 }
907
908 void r300_emit_viewport_state(struct r300_context* r300,
909 struct r300_viewport_state* viewport)
910 {
911 CS_LOCALS(r300);
912
913 BEGIN_CS(9);
914 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
915 OUT_CS_32F(viewport->xscale);
916 OUT_CS_32F(viewport->xoffset);
917 OUT_CS_32F(viewport->yscale);
918 OUT_CS_32F(viewport->yoffset);
919 OUT_CS_32F(viewport->zscale);
920 OUT_CS_32F(viewport->zoffset);
921
922 if (r300->rs_state->enable_vte) {
923 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
924 } else {
925 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
926 }
927 END_CS;
928 }
929
930 void r300_emit_texture_count(struct r300_context* r300)
931 {
932 uint32_t tx_enable = 0;
933 int i;
934 CS_LOCALS(r300);
935
936 /* Notice that texture_count and sampler_count are just sizes
937 * of the respective arrays. We still have to check for the individual
938 * elements. */
939 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
940 if (r300->textures[i]) {
941 tx_enable |= 1 << i;
942 }
943 }
944
945 BEGIN_CS(2);
946 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
947 END_CS;
948
949 }
950
951 void r300_flush_textures(struct r300_context* r300)
952 {
953 CS_LOCALS(r300);
954
955 BEGIN_CS(2);
956 OUT_CS_REG(R300_TX_INVALTAGS, 0);
957 END_CS;
958 }
959
960 static void r300_flush_pvs(struct r300_context* r300)
961 {
962 CS_LOCALS(r300);
963
964 BEGIN_CS(2);
965 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
966 END_CS;
967 }
968
969 /* Emit all dirty state. */
970 void r300_emit_dirty_state(struct r300_context* r300)
971 {
972 struct r300_screen* r300screen = r300_screen(r300->context.screen);
973 struct r300_texture* tex;
974 int i, dirty_tex = 0;
975 boolean invalid = FALSE;
976
977 if (!(r300->dirty_state)) {
978 return;
979 }
980
981 /* Check size of CS. */
982 /* Make sure we have at least 8*1024 spare dwords. */
983 /* XXX It would be nice to know the number of dwords we really need to
984 * XXX emit. */
985 if (!r300->winsys->check_cs(r300->winsys, 8*1024)) {
986 r300->context.flush(&r300->context, 0, NULL);
987 }
988
989 /* Clean out BOs. */
990 r300->winsys->reset_bos(r300->winsys);
991
992 validate:
993 /* Color buffers... */
994 for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
995 tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
996 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
997 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
998 0, RADEON_GEM_DOMAIN_VRAM)) {
999 r300->context.flush(&r300->context, 0, NULL);
1000 goto validate;
1001 }
1002 }
1003 /* ...depth buffer... */
1004 if (r300->framebuffer_state.zsbuf) {
1005 tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
1006 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1007 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1008 0, RADEON_GEM_DOMAIN_VRAM)) {
1009 r300->context.flush(&r300->context, 0, NULL);
1010 goto validate;
1011 }
1012 }
1013 /* ...textures... */
1014 for (i = 0; i < r300->texture_count; i++) {
1015 tex = r300->textures[i];
1016 if (!tex)
1017 continue;
1018 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1019 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1020 r300->context.flush(&r300->context, 0, NULL);
1021 goto validate;
1022 }
1023 }
1024 /* ...occlusion query buffer... */
1025 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1026 0, RADEON_GEM_DOMAIN_GTT)) {
1027 r300->context.flush(&r300->context, 0, NULL);
1028 goto validate;
1029 }
1030 /* ...and vertex buffer. */
1031 if (r300->vbo) {
1032 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1033 RADEON_GEM_DOMAIN_GTT, 0)) {
1034 r300->context.flush(&r300->context, 0, NULL);
1035 goto validate;
1036 }
1037 } else {
1038 /* debug_printf("No VBO while emitting dirty state!\n"); */
1039 }
1040 if (!r300->winsys->validate(r300->winsys)) {
1041 r300->context.flush(&r300->context, 0, NULL);
1042 if (invalid) {
1043 /* Well, hell. */
1044 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1045 exit(1);
1046 }
1047 invalid = TRUE;
1048 goto validate;
1049 }
1050
1051 if (r300->dirty_state & R300_NEW_QUERY) {
1052 r300_emit_query_start(r300);
1053 r300->dirty_state &= ~R300_NEW_QUERY;
1054 }
1055
1056 if (r300->dirty_state & R300_NEW_BLEND) {
1057 r300_emit_blend_state(r300, r300->blend_state);
1058 r300->dirty_state &= ~R300_NEW_BLEND;
1059 }
1060
1061 if (r300->dirty_state & R300_NEW_BLEND_COLOR) {
1062 r300_emit_blend_color_state(r300, r300->blend_color_state);
1063 r300->dirty_state &= ~R300_NEW_BLEND_COLOR;
1064 }
1065
1066 if (r300->dirty_state & R300_NEW_CLIP) {
1067 r300_emit_clip_state(r300, &r300->clip_state);
1068 r300->dirty_state &= ~R300_NEW_CLIP;
1069 }
1070
1071 if (r300->dirty_state & R300_NEW_DSA) {
1072 r300_emit_dsa_state(r300, r300->dsa_state);
1073 r300->dirty_state &= ~R300_NEW_DSA;
1074 }
1075
1076 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1077 r300_emit_fragment_depth_config(r300, r300->fs);
1078 if (r300screen->caps->is_r500) {
1079 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1080 } else {
1081 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1082 }
1083 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1084 }
1085
1086 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1087 if (r300screen->caps->is_r500) {
1088 r500_emit_fs_constant_buffer(r300,
1089 &r300->fs->shader->code.constants);
1090 } else {
1091 r300_emit_fs_constant_buffer(r300,
1092 &r300->fs->shader->code.constants);
1093 }
1094 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1095 }
1096
1097 if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
1098 r300_emit_fb_state(r300, &r300->framebuffer_state);
1099 r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
1100 }
1101
1102 if (r300->dirty_state & R300_NEW_RASTERIZER) {
1103 r300_emit_rs_state(r300, r300->rs_state);
1104 r300->dirty_state &= ~R300_NEW_RASTERIZER;
1105 }
1106
1107 if (r300->dirty_state & R300_NEW_RS_BLOCK) {
1108 r300_emit_rs_block_state(r300, r300->rs_block);
1109 r300->dirty_state &= ~R300_NEW_RS_BLOCK;
1110 }
1111
1112 if (r300->dirty_state & R300_NEW_SCISSOR) {
1113 r300_emit_scissor_state(r300, r300->scissor_state);
1114 r300->dirty_state &= ~R300_NEW_SCISSOR;
1115 }
1116
1117 /* Samplers and textures are tracked separately but emitted together. */
1118 if (r300->dirty_state &
1119 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1120 r300_emit_texture_count(r300);
1121
1122 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1123 if (r300->dirty_state &
1124 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1125 if (r300->textures[i])
1126 r300_emit_texture(r300,
1127 r300->sampler_states[i],
1128 r300->textures[i],
1129 i);
1130 r300->dirty_state &=
1131 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1132 dirty_tex++;
1133 }
1134 }
1135 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1136 }
1137
1138 if (r300->dirty_state & R300_NEW_VIEWPORT) {
1139 r300_emit_viewport_state(r300, r300->viewport_state);
1140 r300->dirty_state &= ~R300_NEW_VIEWPORT;
1141 }
1142
1143 if (dirty_tex) {
1144 r300_flush_textures(r300);
1145 }
1146
1147 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
1148 r300_emit_vertex_format_state(r300);
1149 r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
1150 }
1151
1152 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1153 r300_flush_pvs(r300);
1154 }
1155
1156 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1157 r300_emit_vertex_shader(r300, r300->vs);
1158 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1159 }
1160
1161 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1162 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1163 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1164 }
1165
1166 /* XXX
1167 assert(r300->dirty_state == 0);
1168 */
1169
1170 /* Finally, emit the VBO. */
1171 /* r300_emit_vertex_buffer(r300); */
1172
1173 r300->dirty_hw++;
1174 }