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37ebe6c49df3913229cc318428fc95638d72d8ff
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_vs.h"
36
37 void r300_emit_blend_state(struct r300_context* r300, void* state)
38 {
39 struct r300_blend_state* blend = (struct r300_blend_state*)state;
40 struct pipe_framebuffer_state* fb =
41 (struct pipe_framebuffer_state*)r300->fb_state.state;
42 CS_LOCALS(r300);
43
44 BEGIN_CS(8);
45 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
46 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
47 if (fb->nr_cbufs) {
48 OUT_CS(blend->blend_control);
49 OUT_CS(blend->alpha_blend_control);
50 OUT_CS(blend->color_channel_mask);
51 } else {
52 OUT_CS(0);
53 OUT_CS(0);
54 OUT_CS(0);
55 /* XXX also disable fastfill here once it's supported */
56 }
57 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
58 END_CS;
59 }
60
61 void r300_emit_blend_color_state(struct r300_context* r300, void* state)
62 {
63 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
64 struct r300_screen* r300screen = r300_screen(r300->context.screen);
65 CS_LOCALS(r300);
66
67 if (r300screen->caps->is_r500) {
68 BEGIN_CS(3);
69 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
70 OUT_CS(bc->blend_color_red_alpha);
71 OUT_CS(bc->blend_color_green_blue);
72 END_CS;
73 } else {
74 BEGIN_CS(2);
75 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
76 END_CS;
77 }
78 }
79
80 void r300_emit_clip_state(struct r300_context* r300, void* state)
81 {
82 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
83 int i;
84 struct r300_screen* r300screen = r300_screen(r300->context.screen);
85 CS_LOCALS(r300);
86
87 if (r300screen->caps->has_tcl) {
88 BEGIN_CS(5 + (6 * 4));
89 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
90 (r300screen->caps->is_r500 ?
91 R500_PVS_UCP_START : R300_PVS_UCP_START));
92 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
93 for (i = 0; i < 6; i++) {
94 OUT_CS_32F(clip->ucp[i][0]);
95 OUT_CS_32F(clip->ucp[i][1]);
96 OUT_CS_32F(clip->ucp[i][2]);
97 OUT_CS_32F(clip->ucp[i][3]);
98 }
99 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
100 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
101 END_CS;
102 } else {
103 BEGIN_CS(2);
104 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
105 END_CS;
106 }
107
108 }
109
110 void r300_emit_dsa_state(struct r300_context* r300, void* state)
111 {
112 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
113 struct r300_screen* r300screen = r300_screen(r300->context.screen);
114 struct pipe_framebuffer_state* fb =
115 (struct pipe_framebuffer_state*)r300->fb_state.state;
116 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
117 CS_LOCALS(r300);
118
119 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 6);
120 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
121 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
122
123 if (fb->zsbuf) {
124 OUT_CS(dsa->z_buffer_control);
125 OUT_CS(dsa->z_stencil_control);
126 } else {
127 OUT_CS(0);
128 OUT_CS(0);
129 }
130
131 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
132
133 if (r300screen->caps->is_r500) {
134 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
135 }
136 END_CS;
137 }
138
139 static const float * get_shader_constant(
140 struct r300_context * r300,
141 struct rc_constant * constant,
142 struct r300_constant_buffer * externals)
143 {
144 struct r300_viewport_state* viewport =
145 (struct r300_viewport_state*)r300->viewport_state.state;
146 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
147 struct pipe_texture *tex;
148
149 switch(constant->Type) {
150 case RC_CONSTANT_EXTERNAL:
151 return externals->constants[constant->u.External];
152
153 case RC_CONSTANT_IMMEDIATE:
154 return constant->u.Immediate;
155
156 case RC_CONSTANT_STATE:
157 switch (constant->u.State[0]) {
158 /* Factor for converting rectangle coords to
159 * normalized coords. Should only show up on non-r500. */
160 case RC_STATE_R300_TEXRECT_FACTOR:
161 tex = &r300->textures[constant->u.State[1]]->tex;
162 vec[0] = 1.0 / tex->width0;
163 vec[1] = 1.0 / tex->height0;
164 break;
165
166 /* Texture compare-fail value. Shouldn't ever show up, but if
167 * it does, we'll be ready. */
168 case RC_STATE_SHADOW_AMBIENT:
169 vec[3] = 0;
170 break;
171
172 case RC_STATE_R300_VIEWPORT_SCALE:
173 vec[0] = viewport->xscale;
174 vec[1] = viewport->yscale;
175 vec[2] = viewport->zscale;
176 break;
177
178 case RC_STATE_R300_VIEWPORT_OFFSET:
179 vec[0] = viewport->xoffset;
180 vec[1] = viewport->yoffset;
181 vec[2] = viewport->zoffset;
182 break;
183
184 default:
185 debug_printf("r300: Implementation error: "
186 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
187 }
188 break;
189
190 default:
191 debug_printf("r300: Implementation error: "
192 "Unhandled constant type %d\n", constant->Type);
193 }
194
195 /* This should either be (0, 0, 0, 1), which should be a relatively safe
196 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
197 * state factors. */
198 return vec;
199 }
200
201 /* Convert a normal single-precision float into the 7.16 format
202 * used by the R300 fragment shader.
203 */
204 static uint32_t pack_float24(float f)
205 {
206 union {
207 float fl;
208 uint32_t u;
209 } u;
210 float mantissa;
211 int exponent;
212 uint32_t float24 = 0;
213
214 if (f == 0.0)
215 return 0;
216
217 u.fl = f;
218
219 mantissa = frexpf(f, &exponent);
220
221 /* Handle -ve */
222 if (mantissa < 0) {
223 float24 |= (1 << 23);
224 mantissa = mantissa * -1.0;
225 }
226 /* Handle exponent, bias of 63 */
227 exponent += 62;
228 float24 |= (exponent << 16);
229 /* Kill 7 LSB of mantissa */
230 float24 |= (u.u & 0x7FFFFF) >> 7;
231
232 return float24;
233 }
234
235 void r300_emit_fragment_program_code(struct r300_context* r300,
236 struct rX00_fragment_program_code* generic_code)
237 {
238 struct r300_fragment_program_code * code = &generic_code->code.r300;
239 int i;
240 CS_LOCALS(r300);
241
242 BEGIN_CS(15 +
243 code->alu.length * 4 +
244 (code->tex.length ? (1 + code->tex.length) : 0));
245
246 OUT_CS_REG(R300_US_CONFIG, code->config);
247 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
248 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
249
250 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
251 for(i = 0; i < 4; ++i)
252 OUT_CS(code->code_addr[i]);
253
254 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
255 for (i = 0; i < code->alu.length; i++)
256 OUT_CS(code->alu.inst[i].rgb_inst);
257
258 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
259 for (i = 0; i < code->alu.length; i++)
260 OUT_CS(code->alu.inst[i].rgb_addr);
261
262 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
263 for (i = 0; i < code->alu.length; i++)
264 OUT_CS(code->alu.inst[i].alpha_inst);
265
266 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
267 for (i = 0; i < code->alu.length; i++)
268 OUT_CS(code->alu.inst[i].alpha_addr);
269
270 if (code->tex.length) {
271 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
272 for(i = 0; i < code->tex.length; ++i)
273 OUT_CS(code->tex.inst[i]);
274 }
275
276 END_CS;
277 }
278
279 void r300_emit_fs_constant_buffer(struct r300_context* r300,
280 struct rc_constant_list* constants)
281 {
282 int i;
283 CS_LOCALS(r300);
284
285 if (constants->Count == 0)
286 return;
287
288 BEGIN_CS(constants->Count * 4 + 1);
289 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
290 for(i = 0; i < constants->Count; ++i) {
291 const float * data = get_shader_constant(r300,
292 &constants->Constants[i],
293 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
294 OUT_CS(pack_float24(data[0]));
295 OUT_CS(pack_float24(data[1]));
296 OUT_CS(pack_float24(data[2]));
297 OUT_CS(pack_float24(data[3]));
298 }
299 END_CS;
300 }
301
302 static void r300_emit_fragment_depth_config(struct r300_context* r300,
303 struct r300_fragment_shader* fs)
304 {
305 CS_LOCALS(r300);
306
307 BEGIN_CS(4);
308 if (r300_fragment_shader_writes_depth(fs)) {
309 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
310 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
311 } else {
312 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
313 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
314 }
315 END_CS;
316 }
317
318 void r500_emit_fragment_program_code(struct r300_context* r300,
319 struct rX00_fragment_program_code* generic_code)
320 {
321 struct r500_fragment_program_code * code = &generic_code->code.r500;
322 int i;
323 CS_LOCALS(r300);
324
325 BEGIN_CS(13 +
326 ((code->inst_end + 1) * 6));
327 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
328 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
329 OUT_CS_REG(R500_US_CODE_RANGE,
330 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
331 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
332 OUT_CS_REG(R500_US_CODE_ADDR,
333 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
334
335 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
336 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
337 for (i = 0; i <= code->inst_end; i++) {
338 OUT_CS(code->inst[i].inst0);
339 OUT_CS(code->inst[i].inst1);
340 OUT_CS(code->inst[i].inst2);
341 OUT_CS(code->inst[i].inst3);
342 OUT_CS(code->inst[i].inst4);
343 OUT_CS(code->inst[i].inst5);
344 }
345
346 END_CS;
347 }
348
349 void r500_emit_fs_constant_buffer(struct r300_context* r300,
350 struct rc_constant_list* constants)
351 {
352 int i;
353 CS_LOCALS(r300);
354
355 if (constants->Count == 0)
356 return;
357
358 BEGIN_CS(constants->Count * 4 + 3);
359 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
360 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
361 for (i = 0; i < constants->Count; i++) {
362 const float * data = get_shader_constant(r300,
363 &constants->Constants[i],
364 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
365 OUT_CS_32F(data[0]);
366 OUT_CS_32F(data[1]);
367 OUT_CS_32F(data[2]);
368 OUT_CS_32F(data[3]);
369 }
370 END_CS;
371 }
372
373 void r300_emit_fb_state(struct r300_context* r300, void* state)
374 {
375 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
376 struct r300_screen* r300screen = r300_screen(r300->context.screen);
377 struct r300_texture* tex;
378 struct pipe_surface* surf;
379 int i;
380 CS_LOCALS(r300);
381
382 BEGIN_CS((10 * fb->nr_cbufs) + (fb->zsbuf ? 10 : 0) + 6);
383
384 /* Flush and free renderbuffer caches. */
385 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
386 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
387 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
388 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
389 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
390 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
391
392 /* Set the number of colorbuffers. */
393 if (fb->nr_cbufs > 1) {
394 if (r300screen->caps->is_r500) {
395 OUT_CS_REG(R300_RB3D_CCTL,
396 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
397 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
398 } else {
399 OUT_CS_REG(R300_RB3D_CCTL,
400 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
401 }
402 } else {
403 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
404 }
405
406 /* Set up colorbuffers. */
407 for (i = 0; i < fb->nr_cbufs; i++) {
408 surf = fb->cbufs[i];
409 tex = (struct r300_texture*)surf->texture;
410 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
411
412 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
413 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
414
415 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
416 OUT_CS_RELOC(tex->buffer, tex->fb_state.colorpitch[surf->level],
417 0, RADEON_GEM_DOMAIN_VRAM, 0);
418
419 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
420 }
421
422 /* Set up a zbuffer. */
423 if (fb->zsbuf) {
424 surf = fb->zsbuf;
425 tex = (struct r300_texture*)surf->texture;
426 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
427
428 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
429 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
430
431 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
432
433 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
434 OUT_CS_RELOC(tex->buffer, tex->fb_state.depthpitch[surf->level],
435 0, RADEON_GEM_DOMAIN_VRAM, 0);
436 }
437
438 END_CS;
439 }
440
441 static void r300_emit_query_start(struct r300_context *r300)
442 {
443 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
444 struct r300_query *query = r300->query_current;
445 CS_LOCALS(r300);
446
447 if (!query)
448 return;
449
450 BEGIN_CS(4);
451 if (caps->family == CHIP_FAMILY_RV530) {
452 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
453 } else {
454 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
455 }
456 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
457 END_CS;
458 query->begin_emitted = TRUE;
459 }
460
461
462 static void r300_emit_query_finish(struct r300_context *r300,
463 struct r300_query *query)
464 {
465 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
466 CS_LOCALS(r300);
467
468 assert(caps->num_frag_pipes);
469
470 BEGIN_CS(6 * caps->num_frag_pipes + 2);
471 /* I'm not so sure I like this switch, but it's hard to be elegant
472 * when there's so many special cases...
473 *
474 * So here's the basic idea. For each pipe, enable writes to it only,
475 * then put out the relocation for ZPASS_ADDR, taking into account a
476 * 4-byte offset for each pipe. RV380 and older are special; they have
477 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
478 * so there's a chipset cap for that. */
479 switch (caps->num_frag_pipes) {
480 case 4:
481 /* pipe 3 only */
482 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
483 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
484 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
485 0, RADEON_GEM_DOMAIN_GTT, 0);
486 case 3:
487 /* pipe 2 only */
488 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
489 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
490 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
491 0, RADEON_GEM_DOMAIN_GTT, 0);
492 case 2:
493 /* pipe 1 only */
494 /* As mentioned above, accomodate RV380 and older. */
495 OUT_CS_REG(R300_SU_REG_DEST,
496 1 << (caps->high_second_pipe ? 3 : 1));
497 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
498 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
499 0, RADEON_GEM_DOMAIN_GTT, 0);
500 case 1:
501 /* pipe 0 only */
502 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
503 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
504 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
505 0, RADEON_GEM_DOMAIN_GTT, 0);
506 break;
507 default:
508 debug_printf("r300: Implementation error: Chipset reports %d"
509 " pixel pipes!\n", caps->num_frag_pipes);
510 assert(0);
511 }
512
513 /* And, finally, reset it to normal... */
514 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
515 END_CS;
516 }
517
518 static void rv530_emit_query_single(struct r300_context *r300,
519 struct r300_query *query)
520 {
521 CS_LOCALS(r300);
522
523 BEGIN_CS(8);
524 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
525 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
526 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
527 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
528 END_CS;
529 }
530
531 static void rv530_emit_query_double(struct r300_context *r300,
532 struct r300_query *query)
533 {
534 CS_LOCALS(r300);
535
536 BEGIN_CS(14);
537 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
538 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
539 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
540 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
541 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
542 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
543 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
544 END_CS;
545 }
546
547 void r300_emit_query_end(struct r300_context* r300)
548 {
549 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
550 struct r300_query *query = r300->query_current;
551
552 if (!query)
553 return;
554
555 if (query->begin_emitted == FALSE)
556 return;
557
558 if (caps->family == CHIP_FAMILY_RV530) {
559 if (caps->num_z_pipes == 2)
560 rv530_emit_query_double(r300, query);
561 else
562 rv530_emit_query_single(r300, query);
563 } else
564 r300_emit_query_finish(r300, query);
565 }
566
567 void r300_emit_rs_state(struct r300_context* r300, void* state)
568 {
569 struct r300_rs_state* rs = (struct r300_rs_state*)state;
570 float scale, offset;
571 CS_LOCALS(r300);
572
573 BEGIN_CS(18 + (rs->polygon_offset_enable ? 5 : 0));
574 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
575
576 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
577
578 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
579 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
580 OUT_CS(rs->point_minmax);
581 OUT_CS(rs->line_control);
582
583 if (rs->polygon_offset_enable) {
584 scale = rs->depth_scale * 12;
585 offset = rs->depth_offset;
586
587 switch (r300->zbuffer_bpp) {
588 case 16:
589 offset *= 4;
590 break;
591 case 24:
592 offset *= 2;
593 break;
594 }
595
596 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
597 OUT_CS_32F(scale);
598 OUT_CS_32F(offset);
599 OUT_CS_32F(scale);
600 OUT_CS_32F(offset);
601 }
602
603 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
604 OUT_CS(rs->polygon_offset_enable);
605 OUT_CS(rs->cull_mode);
606 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
607 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
608 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
609 END_CS;
610 }
611
612 void r300_emit_rs_block_state(struct r300_context* r300, void* state)
613 {
614 struct r300_rs_block* rs = (struct r300_rs_block*)state;
615 unsigned i;
616 struct r300_screen* r300screen = r300_screen(r300->context.screen);
617 /* It's the same for both INST and IP tables */
618 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
619 CS_LOCALS(r300);
620
621 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
622
623 BEGIN_CS(5 + count*2);
624 if (r300screen->caps->is_r500) {
625 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
626 } else {
627 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
628 }
629 for (i = 0; i < count; i++) {
630 OUT_CS(rs->ip[i]);
631 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
632 }
633
634 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
635 OUT_CS(rs->count);
636 OUT_CS(rs->inst_count);
637
638 if (r300screen->caps->is_r500) {
639 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
640 } else {
641 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
642 }
643 for (i = 0; i < count; i++) {
644 OUT_CS(rs->inst[i]);
645 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
646 }
647
648 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
649 rs->count, rs->inst_count);
650
651 END_CS;
652 }
653
654 void r300_emit_scissor_state(struct r300_context* r300, void* state)
655 {
656 unsigned minx, miny, maxx, maxy;
657 uint32_t top_left, bottom_right;
658 struct r300_screen* r300screen = r300_screen(r300->context.screen);
659 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
660 struct pipe_framebuffer_state* fb =
661 (struct pipe_framebuffer_state*)r300->fb_state.state;
662 CS_LOCALS(r300);
663
664 minx = miny = 0;
665 maxx = fb->width;
666 maxy = fb->height;
667
668 if (((struct r300_rs_state*)r300->rs_state.state)->rs.scissor) {
669 minx = MAX2(minx, scissor->minx);
670 miny = MAX2(miny, scissor->miny);
671 maxx = MIN2(maxx, scissor->maxx);
672 maxy = MIN2(maxy, scissor->maxy);
673 }
674
675 /* Special case for zero-area scissor.
676 *
677 * We can't allow the variables maxx and maxy to be zero because they are
678 * subtracted from later in the code, which would cause emitting ~0 and
679 * making the kernel checker angry.
680 *
681 * Let's consider we change maxx and maxy to 1, which is effectively
682 * a one-pixel area. We must then change minx and miny to a number which is
683 * greater than 1 to get the zero area back. */
684 if (!maxx || !maxy) {
685 minx = 2;
686 miny = 2;
687 maxx = 1;
688 maxy = 1;
689 }
690
691 if (r300screen->caps->is_r500) {
692 top_left =
693 (minx << R300_SCISSORS_X_SHIFT) |
694 (miny << R300_SCISSORS_Y_SHIFT);
695 bottom_right =
696 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
697 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
698 } else {
699 /* Offset of 1440 in non-R500 chipsets. */
700 top_left =
701 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
702 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
703 bottom_right =
704 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
705 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
706 }
707
708 BEGIN_CS(3);
709 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
710 OUT_CS(top_left);
711 OUT_CS(bottom_right);
712 END_CS;
713 }
714
715 void r300_emit_texture(struct r300_context* r300,
716 struct r300_sampler_state* sampler,
717 struct r300_texture* tex,
718 unsigned offset)
719 {
720 uint32_t filter0 = sampler->filter0;
721 uint32_t format0 = tex->state.format0;
722 unsigned min_level, max_level;
723 CS_LOCALS(r300);
724
725 /* to emulate 1D textures through 2D ones correctly */
726 if (tex->tex.target == PIPE_TEXTURE_1D) {
727 filter0 &= ~R300_TX_WRAP_T_MASK;
728 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
729 }
730
731 if (tex->is_npot) {
732 /* NPOT textures don't support mip filter, unfortunately.
733 * This prevents incorrect rendering. */
734 filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK;
735 } else {
736 /* determine min/max levels */
737 /* the MAX_MIP level is the largest (finest) one */
738 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
739 min_level = MIN2(sampler->min_lod, max_level);
740 format0 |= R300_TX_NUM_LEVELS(max_level);
741 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
742 }
743
744 BEGIN_CS(16);
745 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
746 (offset << 28));
747 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
748 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
749
750 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
751 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
752 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
753 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
754 OUT_CS_RELOC(tex->buffer,
755 R300_TXO_MACRO_TILE(tex->macrotile) |
756 R300_TXO_MICRO_TILE(tex->microtile),
757 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
758 END_CS;
759 }
760
761 void r300_emit_aos(struct r300_context* r300, unsigned offset)
762 {
763 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
764 struct pipe_vertex_element *velem = r300->vertex_element;
765 int i;
766 unsigned size1, size2, aos_count = r300->vertex_element_count;
767 unsigned packet_size = (aos_count * 3 + 1) / 2;
768 CS_LOCALS(r300);
769
770 BEGIN_CS(2 + packet_size + aos_count * 2);
771 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
772 OUT_CS(aos_count);
773
774 for (i = 0; i < aos_count - 1; i += 2) {
775 vb1 = &vbuf[velem[i].vertex_buffer_index];
776 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
777 size1 = util_format_get_blocksize(velem[i].src_format);
778 size2 = util_format_get_blocksize(velem[i+1].src_format);
779
780 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
781 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
782 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
783 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
784 }
785
786 if (aos_count & 1) {
787 vb1 = &vbuf[velem[i].vertex_buffer_index];
788 size1 = util_format_get_blocksize(velem[i].src_format);
789
790 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
791 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
792 }
793
794 for (i = 0; i < aos_count; i++) {
795 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
796 RADEON_GEM_DOMAIN_GTT, 0, 0);
797 }
798 END_CS;
799 }
800
801 void r300_emit_vertex_format_state(struct r300_context* r300, void* state)
802 {
803 struct r300_vertex_info* vertex_info = (struct r300_vertex_info*)state;
804 unsigned i;
805 CS_LOCALS(r300);
806
807 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
808
809 BEGIN_CS(26);
810 OUT_CS_REG(R300_VAP_VTX_SIZE, vertex_info->vinfo.size);
811
812 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
813 OUT_CS(vertex_info->vinfo.hwfmt[0]);
814 OUT_CS(vertex_info->vinfo.hwfmt[1]);
815 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
816 OUT_CS(vertex_info->vinfo.hwfmt[2]);
817 OUT_CS(vertex_info->vinfo.hwfmt[3]);
818 for (i = 0; i < 4; i++) {
819 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
820 vertex_info->vinfo.hwfmt[i]);
821 }
822
823 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
824 for (i = 0; i < 8; i++) {
825 OUT_CS(vertex_info->vap_prog_stream_cntl[i]);
826 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
827 vertex_info->vap_prog_stream_cntl[i]);
828 }
829 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
830 for (i = 0; i < 8; i++) {
831 OUT_CS(vertex_info->vap_prog_stream_cntl_ext[i]);
832 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
833 vertex_info->vap_prog_stream_cntl_ext[i]);
834 }
835 END_CS;
836 }
837
838
839 void r300_emit_vertex_program_code(struct r300_context* r300,
840 struct r300_vertex_program_code* code)
841 {
842 int i;
843 struct r300_screen* r300screen = r300_screen(r300->context.screen);
844 unsigned instruction_count = code->length / 4;
845
846 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
847 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
848 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
849 int temp_count = MAX2(code->num_temporaries, 1);
850 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
851 vtx_mem_size / output_count, 10);
852 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
853
854 CS_LOCALS(r300);
855
856 if (!r300screen->caps->has_tcl) {
857 debug_printf("r300: Implementation error: emit_vertex_shader called,"
858 " but has_tcl is FALSE!\n");
859 return;
860 }
861
862 BEGIN_CS(9 + code->length);
863 /* R300_VAP_PVS_CODE_CNTL_0
864 * R300_VAP_PVS_CONST_CNTL
865 * R300_VAP_PVS_CODE_CNTL_1
866 * See the r5xx docs for instructions on how to use these. */
867 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
868 OUT_CS(R300_PVS_FIRST_INST(0) |
869 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
870 R300_PVS_LAST_INST(instruction_count - 1));
871 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
872 OUT_CS(instruction_count - 1);
873
874 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
875 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
876 for (i = 0; i < code->length; i++)
877 OUT_CS(code->body.d[i]);
878
879 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
880 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
881 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
882 R300_PVS_VF_MAX_VTX_NUM(12) |
883 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
884 END_CS;
885 }
886
887 void r300_emit_vertex_shader(struct r300_context* r300,
888 struct r300_vertex_shader* vs)
889 {
890 r300_emit_vertex_program_code(r300, &vs->code);
891 }
892
893 void r300_emit_vs_constant_buffer(struct r300_context* r300,
894 struct rc_constant_list* constants)
895 {
896 int i;
897 struct r300_screen* r300screen = r300_screen(r300->context.screen);
898 CS_LOCALS(r300);
899
900 if (!r300screen->caps->has_tcl) {
901 debug_printf("r300: Implementation error: emit_vertex_shader called,"
902 " but has_tcl is FALSE!\n");
903 return;
904 }
905
906 if (constants->Count == 0)
907 return;
908
909 BEGIN_CS(constants->Count * 4 + 3);
910 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
911 (r300screen->caps->is_r500 ?
912 R500_PVS_CONST_START : R300_PVS_CONST_START));
913 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
914 for (i = 0; i < constants->Count; i++) {
915 const float * data = get_shader_constant(r300,
916 &constants->Constants[i],
917 &r300->shader_constants[PIPE_SHADER_VERTEX]);
918 OUT_CS_32F(data[0]);
919 OUT_CS_32F(data[1]);
920 OUT_CS_32F(data[2]);
921 OUT_CS_32F(data[3]);
922 }
923 END_CS;
924 }
925
926 void r300_emit_viewport_state(struct r300_context* r300, void* state)
927 {
928 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
929 CS_LOCALS(r300);
930
931 BEGIN_CS(9);
932 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
933 OUT_CS_32F(viewport->xscale);
934 OUT_CS_32F(viewport->xoffset);
935 OUT_CS_32F(viewport->yscale);
936 OUT_CS_32F(viewport->yoffset);
937 OUT_CS_32F(viewport->zscale);
938 OUT_CS_32F(viewport->zoffset);
939 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
940 END_CS;
941 }
942
943 void r300_emit_texture_count(struct r300_context* r300)
944 {
945 uint32_t tx_enable = 0;
946 int i;
947 CS_LOCALS(r300);
948
949 /* Notice that texture_count and sampler_count are just sizes
950 * of the respective arrays. We still have to check for the individual
951 * elements. */
952 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
953 if (r300->textures[i]) {
954 tx_enable |= 1 << i;
955 }
956 }
957
958 BEGIN_CS(2);
959 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
960 END_CS;
961
962 }
963
964 void r300_emit_ztop_state(struct r300_context* r300, void* state)
965 {
966 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
967 CS_LOCALS(r300);
968
969 BEGIN_CS(2);
970 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
971 END_CS;
972 }
973
974 void r300_flush_textures(struct r300_context* r300)
975 {
976 CS_LOCALS(r300);
977
978 BEGIN_CS(2);
979 OUT_CS_REG(R300_TX_INVALTAGS, 0);
980 END_CS;
981 }
982
983 static void r300_flush_pvs(struct r300_context* r300)
984 {
985 CS_LOCALS(r300);
986
987 BEGIN_CS(2);
988 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
989 END_CS;
990 }
991
992 void r300_emit_buffer_validate(struct r300_context *r300)
993 {
994 struct pipe_framebuffer_state* fb =
995 (struct pipe_framebuffer_state*)r300->fb_state.state;
996 struct r300_texture* tex;
997 unsigned i;
998 boolean invalid = FALSE;
999
1000 /* Clean out BOs. */
1001 r300->winsys->reset_bos(r300->winsys);
1002
1003 validate:
1004 /* Color buffers... */
1005 for (i = 0; i < fb->nr_cbufs; i++) {
1006 tex = (struct r300_texture*)fb->cbufs[i]->texture;
1007 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1008 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1009 0, RADEON_GEM_DOMAIN_VRAM)) {
1010 r300->context.flush(&r300->context, 0, NULL);
1011 goto validate;
1012 }
1013 }
1014 /* ...depth buffer... */
1015 if (fb->zsbuf) {
1016 tex = (struct r300_texture*)fb->zsbuf->texture;
1017 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1018 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1019 0, RADEON_GEM_DOMAIN_VRAM)) {
1020 r300->context.flush(&r300->context, 0, NULL);
1021 goto validate;
1022 }
1023 }
1024 /* ...textures... */
1025 for (i = 0; i < r300->texture_count; i++) {
1026 tex = r300->textures[i];
1027 if (!tex)
1028 continue;
1029 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1030 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1031 r300->context.flush(&r300->context, 0, NULL);
1032 goto validate;
1033 }
1034 }
1035 /* ...occlusion query buffer... */
1036 if (r300->dirty_state & R300_NEW_QUERY) {
1037 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1038 0, RADEON_GEM_DOMAIN_GTT)) {
1039 r300->context.flush(&r300->context, 0, NULL);
1040 goto validate;
1041 }
1042 }
1043 /* ...and vertex buffer. */
1044 if (r300->vbo) {
1045 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1046 RADEON_GEM_DOMAIN_GTT, 0)) {
1047 r300->context.flush(&r300->context, 0, NULL);
1048 goto validate;
1049 }
1050 } else {
1051 /* debug_printf("No VBO while emitting dirty state!\n"); */
1052 }
1053 if (!r300->winsys->validate(r300->winsys)) {
1054 r300->context.flush(&r300->context, 0, NULL);
1055 if (invalid) {
1056 /* Well, hell. */
1057 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1058 exit(1);
1059 }
1060 invalid = TRUE;
1061 goto validate;
1062 }
1063 }
1064
1065 /* Emit all dirty state. */
1066 void r300_emit_dirty_state(struct r300_context* r300)
1067 {
1068 struct r300_screen* r300screen = r300_screen(r300->context.screen);
1069 struct r300_atom* atom;
1070 unsigned i, dwords = 1024;
1071 int dirty_tex = 0;
1072
1073 /* Check the required number of dwords against the space remaining in the
1074 * current CS object. If we need more, then flush. */
1075
1076 foreach(atom, &r300->atom_list) {
1077 if (atom->dirty || atom->always_dirty) {
1078 dwords += atom->size;
1079 }
1080 }
1081
1082 /* Make sure we have at least 2*1024 spare dwords. */
1083 /* XXX It would be nice to know the number of dwords we really need to
1084 * XXX emit. */
1085 while (!r300->winsys->check_cs(r300->winsys, dwords)) {
1086 r300->context.flush(&r300->context, 0, NULL);
1087 }
1088
1089 if (r300->dirty_state & R300_NEW_QUERY) {
1090 r300_emit_query_start(r300);
1091 r300->dirty_state &= ~R300_NEW_QUERY;
1092 }
1093
1094 foreach(atom, &r300->atom_list) {
1095 if (atom->dirty || atom->always_dirty) {
1096 atom->emit(r300, atom->state);
1097 atom->dirty = FALSE;
1098 }
1099 }
1100
1101 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1102 r300_emit_fragment_depth_config(r300, r300->fs);
1103 if (r300screen->caps->is_r500) {
1104 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1105 } else {
1106 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1107 }
1108 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1109 }
1110
1111 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1112 if (r300screen->caps->is_r500) {
1113 r500_emit_fs_constant_buffer(r300,
1114 &r300->fs->shader->code.constants);
1115 } else {
1116 r300_emit_fs_constant_buffer(r300,
1117 &r300->fs->shader->code.constants);
1118 }
1119 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1120 }
1121
1122 /* Samplers and textures are tracked separately but emitted together. */
1123 if (r300->dirty_state &
1124 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1125 r300_emit_texture_count(r300);
1126
1127 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1128 if (r300->dirty_state &
1129 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1130 if (r300->textures[i]) {
1131 r300_emit_texture(r300,
1132 r300->sampler_states[i],
1133 r300->textures[i],
1134 i);
1135 dirty_tex |= r300->dirty_state & (R300_NEW_TEXTURE << i);
1136 }
1137 r300->dirty_state &=
1138 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1139 }
1140 }
1141 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1142 }
1143
1144 if (dirty_tex) {
1145 r300_flush_textures(r300);
1146 }
1147
1148 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1149 r300_flush_pvs(r300);
1150 }
1151
1152 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1153 r300_emit_vertex_shader(r300, r300->vs);
1154 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1155 }
1156
1157 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1158 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1159 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1160 }
1161
1162 /* XXX
1163 assert(r300->dirty_state == 0);
1164 */
1165
1166 /* Finally, emit the VBO. */
1167 /* r300_emit_vertex_buffer(r300); */
1168
1169 r300->dirty_hw++;
1170 }