2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
30 #include "r300_context.h"
33 #include "r300_emit.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
39 void r300_emit_blend_state(struct r300_context
* r300
,
40 unsigned size
, void* state
)
42 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
43 struct pipe_framebuffer_state
* fb
=
44 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
48 if (fb
->cbufs
[0]->format
== PIPE_FORMAT_R16G16B16A16_FLOAT
) {
49 WRITE_CS_TABLE(blend
->cb_noclamp
, size
);
51 unsigned swz
= r300_surface(fb
->cbufs
[0])->colormask_swizzle
;
52 WRITE_CS_TABLE(blend
->cb_clamp
[swz
], size
);
55 WRITE_CS_TABLE(blend
->cb_no_readwrite
, size
);
59 void r300_emit_blend_color_state(struct r300_context
* r300
,
60 unsigned size
, void* state
)
62 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
65 WRITE_CS_TABLE(bc
->cb
, size
);
68 void r300_emit_clip_state(struct r300_context
* r300
,
69 unsigned size
, void* state
)
71 struct r300_clip_state
* clip
= (struct r300_clip_state
*)state
;
74 WRITE_CS_TABLE(clip
->cb
, size
);
77 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
79 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
80 struct pipe_framebuffer_state
* fb
=
81 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
82 boolean is_r500
= r300
->screen
->caps
.is_r500
;
84 uint32_t alpha_func
= dsa
->alpha_function
;
86 /* Choose the alpha ref value between 8-bit (FG_ALPHA_FUNC.AM_VAL) and
87 * 16-bit (FG_ALPHA_VALUE). */
88 if (is_r500
&& (alpha_func
& R300_FG_ALPHA_FUNC_ENABLE
)) {
89 if (fb
->nr_cbufs
&& fb
->cbufs
[0]->format
== PIPE_FORMAT_R16G16B16A16_FLOAT
) {
90 alpha_func
|= R500_FG_ALPHA_FUNC_FP16_ENABLE
;
92 alpha_func
|= R500_FG_ALPHA_FUNC_8BIT
;
96 /* Setup alpha-to-coverage. */
97 if (r300
->alpha_to_coverage
&& r300
->msaa_enable
) {
98 /* Always set 3/6, it improves precision even for 2x and 4x MSAA. */
99 alpha_func
|= R300_FG_ALPHA_FUNC_MASK_ENABLE
|
100 R300_FG_ALPHA_FUNC_CFG_3_OF_6
;
103 OUT_CS_REG(R300_FG_ALPHA_FUNC
, alpha_func
);
104 WRITE_CS_TABLE(fb
->zsbuf
? &dsa
->cb_begin
: dsa
->cb_zb_no_readwrite
, size
-2);
107 static void get_rc_constant_state(
109 struct r300_context
* r300
,
110 struct rc_constant
* constant
)
112 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
113 struct r300_resource
*tex
;
115 assert(constant
->Type
== RC_CONSTANT_STATE
);
117 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
118 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
121 switch (constant
->u
.State
[0]) {
122 /* Factor for converting rectangle coords to
123 * normalized coords. Should only show up on non-r500. */
124 case RC_STATE_R300_TEXRECT_FACTOR
:
125 tex
= r300_resource(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
126 vec
[0] = 1.0 / tex
->tex
.width0
;
127 vec
[1] = 1.0 / tex
->tex
.height0
;
132 case RC_STATE_R300_TEXSCALE_FACTOR
:
133 tex
= r300_resource(texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
);
134 /* Add a small number to the texture size to work around rounding errors in hw. */
135 vec
[0] = tex
->b
.b
.width0
/ (tex
->tex
.width0
+ 0.001f
);
136 vec
[1] = tex
->b
.b
.height0
/ (tex
->tex
.height0
+ 0.001f
);
137 vec
[2] = tex
->b
.b
.depth0
/ (tex
->tex
.depth0
+ 0.001f
);
141 case RC_STATE_R300_VIEWPORT_SCALE
:
142 vec
[0] = r300
->viewport
.scale
[0];
143 vec
[1] = r300
->viewport
.scale
[1];
144 vec
[2] = r300
->viewport
.scale
[2];
148 case RC_STATE_R300_VIEWPORT_OFFSET
:
149 vec
[0] = r300
->viewport
.translate
[0];
150 vec
[1] = r300
->viewport
.translate
[1];
151 vec
[2] = r300
->viewport
.translate
[2];
156 fprintf(stderr
, "r300: Implementation error: "
157 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
165 /* Convert a normal single-precision float into the 7.16 format
166 * used by the R300 fragment shader.
168 uint32_t pack_float24(float f
)
176 uint32_t float24
= 0;
183 mantissa
= frexpf(f
, &exponent
);
187 float24
|= (1 << 23);
188 mantissa
= mantissa
* -1.0;
190 /* Handle exponent, bias of 63 */
192 float24
|= (exponent
<< 16);
193 /* Kill 7 LSB of mantissa */
194 float24
|= (u
.u
& 0x7FFFFF) >> 7;
199 void r300_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
201 struct r300_fragment_shader
*fs
= r300_fs(r300
);
204 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
207 void r300_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
209 struct r300_fragment_shader
*fs
= r300_fs(r300
);
210 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
211 unsigned count
= fs
->shader
->externals_count
;
219 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, count
* 4);
220 if (buf
->remap_table
){
221 for (i
= 0; i
< count
; i
++) {
222 float *data
= (float*)&buf
->ptr
[buf
->remap_table
[i
]*4];
223 for (j
= 0; j
< 4; j
++)
224 OUT_CS(pack_float24(data
[j
]));
227 for (i
= 0; i
< count
; i
++)
228 for (j
= 0; j
< 4; j
++)
229 OUT_CS(pack_float24(*(float*)&buf
->ptr
[i
*4+j
]));
235 void r300_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
237 struct r300_fragment_shader
*fs
= r300_fs(r300
);
238 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
240 unsigned count
= fs
->shader
->rc_state_count
;
241 unsigned first
= fs
->shader
->externals_count
;
242 unsigned end
= constants
->Count
;
250 for(i
= first
; i
< end
; ++i
) {
251 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
254 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
256 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
257 for (j
= 0; j
< 4; j
++)
258 OUT_CS(pack_float24(data
[j
]));
264 void r500_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
266 struct r300_fragment_shader
*fs
= r300_fs(r300
);
269 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
272 void r500_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
274 struct r300_fragment_shader
*fs
= r300_fs(r300
);
275 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
276 unsigned count
= fs
->shader
->externals_count
;
283 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
284 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, count
* 4);
285 if (buf
->remap_table
){
286 for (unsigned i
= 0; i
< count
; i
++) {
287 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
288 OUT_CS_TABLE(data
, 4);
291 OUT_CS_TABLE(buf
->ptr
, count
* 4);
296 void r500_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
298 struct r300_fragment_shader
*fs
= r300_fs(r300
);
299 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
301 unsigned count
= fs
->shader
->rc_state_count
;
302 unsigned first
= fs
->shader
->externals_count
;
303 unsigned end
= constants
->Count
;
310 for(i
= first
; i
< end
; ++i
) {
311 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
314 get_rc_constant_state(data
, r300
, &constants
->Constants
[i
]);
316 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
317 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
318 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
319 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
320 OUT_CS_TABLE(data
, 4);
326 void r300_emit_gpu_flush(struct r300_context
*r300
, unsigned size
, void *state
)
328 struct r300_gpu_flush
*gpuflush
= (struct r300_gpu_flush
*)state
;
329 struct pipe_framebuffer_state
* fb
=
330 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
331 uint32_t height
= fb
->height
;
332 uint32_t width
= fb
->width
;
335 if (r300
->cbzb_clear
) {
336 struct r300_surface
*surf
= r300_surface(fb
->cbufs
[0]);
338 height
= surf
->cbzb_height
;
339 width
= surf
->cbzb_width
;
342 DBG(r300
, DBG_SCISSOR
,
343 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
344 width
, height
, r300
->cbzb_clear
? "YES" : "NO");
349 * By writing to the SC registers, SC & US assert idle. */
350 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
351 if (r300
->screen
->caps
.is_r500
) {
353 OUT_CS(((width
- 1) << R300_SCISSORS_X_SHIFT
) |
354 ((height
- 1) << R300_SCISSORS_Y_SHIFT
));
356 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
357 (1440 << R300_SCISSORS_Y_SHIFT
));
358 OUT_CS(((width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
359 ((height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
362 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
363 OUT_CS_TABLE(gpuflush
->cb_flush_clean
, 6);
367 void r300_emit_aa_state(struct r300_context
*r300
, unsigned size
, void *state
)
369 struct r300_aa_state
*aa
= (struct r300_aa_state
*)state
;
373 OUT_CS_REG(R300_GB_AA_CONFIG
, aa
->aa_config
);
376 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET
, 3);
377 OUT_CS(aa
->dest
->offset
);
378 OUT_CS(aa
->dest
->pitch
& R300_RB3D_AARESOLVE_PITCH_MASK
);
379 OUT_CS(R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE
|
380 R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE
);
381 OUT_CS_RELOC(aa
->dest
);
383 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL
, 0);
389 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
391 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
392 struct r300_surface
* surf
;
394 uint32_t rb3d_cctl
= 0;
400 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
401 * what we usually want. */
402 if (r300
->screen
->caps
.is_r500
) {
403 rb3d_cctl
= R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
;
405 if (fb
->nr_cbufs
&& r300
->fb_multiwrite
) {
406 rb3d_cctl
|= R300_RB3D_CCTL_NUM_MULTIWRITES(fb
->nr_cbufs
);
409 OUT_CS_REG(R300_RB3D_CCTL
, rb3d_cctl
);
411 /* Set up colorbuffers. */
412 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
413 surf
= r300_surface(fb
->cbufs
[i
]);
415 OUT_CS_REG(R300_RB3D_COLOROFFSET0
+ (4 * i
), surf
->offset
);
418 OUT_CS_REG(R300_RB3D_COLORPITCH0
+ (4 * i
), surf
->pitch
);
422 /* Set up the ZB part of the CBZB clear. */
423 if (r300
->cbzb_clear
) {
424 surf
= r300_surface(fb
->cbufs
[0]);
426 OUT_CS_REG(R300_ZB_FORMAT
, surf
->cbzb_format
);
428 OUT_CS_REG(R300_ZB_DEPTHOFFSET
, surf
->cbzb_midpoint_offset
);
431 OUT_CS_REG(R300_ZB_DEPTHPITCH
, surf
->cbzb_pitch
);
435 "CBZB clearing cbuf %08x %08x\n", surf
->cbzb_format
,
438 /* Set up a zbuffer. */
439 else if (fb
->zsbuf
) {
440 surf
= r300_surface(fb
->zsbuf
);
442 OUT_CS_REG(R300_ZB_FORMAT
, surf
->format
);
444 OUT_CS_REG(R300_ZB_DEPTHOFFSET
, surf
->offset
);
447 OUT_CS_REG(R300_ZB_DEPTHPITCH
, surf
->pitch
);
450 if (r300
->hyperz_enabled
) {
452 OUT_CS_REG(R300_ZB_HIZ_OFFSET
, 0);
453 OUT_CS_REG(R300_ZB_HIZ_PITCH
, surf
->pitch_hiz
);
454 /* Z Mask RAM. (compressed zbuffer) */
455 OUT_CS_REG(R300_ZB_ZMASK_OFFSET
, 0);
456 OUT_CS_REG(R300_ZB_ZMASK_PITCH
, surf
->pitch_zmask
);
463 void r300_emit_hyperz_state(struct r300_context
*r300
,
464 unsigned size
, void *state
)
466 struct r300_hyperz_state
*z
= state
;
470 WRITE_CS_TABLE(&z
->cb_flush_begin
, size
);
472 WRITE_CS_TABLE(&z
->cb_begin
, size
- 2);
475 void r300_emit_hyperz_end(struct r300_context
*r300
)
477 struct r300_hyperz_state z
=
478 *(struct r300_hyperz_state
*)r300
->hyperz_state
.state
;
482 z
.zb_depthclearvalue
= 0;
483 z
.sc_hyperz
= R300_SC_HYPERZ_ADJ_2
;
484 z
.gb_z_peq_config
= 0;
486 r300_emit_hyperz_state(r300
, r300
->hyperz_state
.size
, &z
);
489 #define R300_NIBBLES(x0, y0, x1, y1, x2, y2, d0y, d0x) \
490 (((x0) & 0xf) | (((y0) & 0xf) << 4) | \
491 (((x1) & 0xf) << 8) | (((y1) & 0xf) << 12) | \
492 (((x2) & 0xf) << 16) | (((y2) & 0xf) << 20) | \
493 (((d0y) & 0xf) << 24) | (((d0x) & 0xf) << 28))
495 static unsigned r300_get_mspos(int index
, unsigned *p
)
497 unsigned reg
, i
, distx
, disty
, dist
;
500 /* MSPOS0 contains positions for samples 0,1,2 as (X,Y) pairs of nibbles,
501 * followed by a (Y,X) pair containing the minimum distance from the pixel
503 * X0, Y0, X1, Y1, X2, Y2, D0_Y, D0_X
505 * There is a quirk when setting D0_X. The value represents the distance
506 * from the left edge of the pixel quad to the first sample in subpixels.
507 * All values less than eight should use the actual value, but „7‟ should
508 * be used for the distance „8‟. The hardware will convert 7 into 8 internally.
511 for (i
= 0; i
< 12; i
+= 2) {
517 for (i
= 1; i
< 12; i
+= 2) {
525 reg
= R300_NIBBLES(p
[0], p
[1], p
[2], p
[3], p
[4], p
[5], disty
, distx
);
527 /* MSPOS1 contains positions for samples 3,4,5 as (X,Y) pairs of nibbles,
528 * followed by the minimum distance from the pixel edge (not sure if X or Y):
529 * X3, Y3, X4, Y4, X5, Y5, D1
532 for (i
= 0; i
< 12; i
++) {
537 reg
= R300_NIBBLES(p
[6], p
[7], p
[8], p
[9], p
[10], p
[11], dist
, 0);
542 void r300_emit_fb_state_pipelined(struct r300_context
*r300
,
543 unsigned size
, void *state
)
545 /* The sample coordinates are in the range [0,11], because
546 * GB_TILE_CONFIG.SUBPIXEL is set to the 1/12 subpixel precision.
548 * Some sample coordinates reach to neighboring pixels and should not be used.
551 * The unused samples must be set to the positions of other valid samples. */
552 static unsigned sample_locs_1x
[12] = {
553 6,6, 6,6, 6,6, 6,6, 6,6, 6,6
555 static unsigned sample_locs_2x
[12] = {
556 3,9, 9,3, 9,3, 9,3, 9,3, 9,3
558 static unsigned sample_locs_4x
[12] = {
559 4,4, 8,8, 2,10, 10,2, 10,2, 10,2
561 static unsigned sample_locs_6x
[12] = {
562 3,1, 7,3, 11,5, 1,7, 5,9, 9,10
565 struct pipe_framebuffer_state
* fb
=
566 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
567 unsigned i
, num_samples
, num_cbufs
= fb
->nr_cbufs
;
568 unsigned mspos0
, mspos1
;
571 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
572 * marked as UNUSED in the US block. */
573 if (r300
->fb_multiwrite
) {
574 num_cbufs
= MIN2(num_cbufs
, 1);
579 /* Colorbuffer format in the US block.
580 * (must be written after unpipelined regs) */
581 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0
, 4);
582 for (i
= 0; i
< num_cbufs
; i
++) {
583 OUT_CS(r300_surface(fb
->cbufs
[i
])->format
);
586 OUT_CS(R300_US_OUT_FMT_C4_8
|
587 R300_C0_SEL_B
| R300_C1_SEL_G
|
588 R300_C2_SEL_R
| R300_C3_SEL_A
);
591 OUT_CS(R300_US_OUT_FMT_UNUSED
);
594 /* Multisampling. Depends on framebuffer sample count.
595 * These are pipelined regs and as such cannot be moved
598 num_samples
= r300
->msaa_enable
? r300
->num_samples
: 1;
600 /* Sample positions. */
601 switch (num_samples
) {
603 mspos0
= r300_get_mspos(0, sample_locs_1x
);
604 mspos1
= r300_get_mspos(1, sample_locs_1x
);
607 mspos0
= r300_get_mspos(0, sample_locs_2x
);
608 mspos1
= r300_get_mspos(1, sample_locs_2x
);
611 mspos0
= r300_get_mspos(0, sample_locs_4x
);
612 mspos1
= r300_get_mspos(1, sample_locs_4x
);
615 mspos0
= r300_get_mspos(0, sample_locs_6x
);
616 mspos1
= r300_get_mspos(1, sample_locs_6x
);
620 OUT_CS_REG_SEQ(R300_GB_MSPOS0
, 2);
626 void r300_emit_query_start(struct r300_context
*r300
, unsigned size
, void*state
)
628 struct r300_query
*query
= r300
->query_current
;
635 if (r300
->screen
->caps
.family
== CHIP_RV530
) {
636 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
638 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
640 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
642 query
->begin_emitted
= TRUE
;
645 static void r300_emit_query_end_frag_pipes(struct r300_context
*r300
,
646 struct r300_query
*query
)
648 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
649 uint32_t gb_pipes
= r300
->screen
->info
.r300_num_gb_pipes
;
654 BEGIN_CS(6 * gb_pipes
+ 2);
655 /* I'm not so sure I like this switch, but it's hard to be elegant
656 * when there's so many special cases...
658 * So here's the basic idea. For each pipe, enable writes to it only,
659 * then put out the relocation for ZPASS_ADDR, taking into account a
660 * 4-byte offset for each pipe. RV380 and older are special; they have
661 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
662 * so there's a chipset cap for that. */
666 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
667 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 3) * 4);
668 OUT_CS_RELOC(r300
->query_current
);
671 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
672 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 2) * 4);
673 OUT_CS_RELOC(r300
->query_current
);
676 /* As mentioned above, accomodate RV380 and older. */
677 OUT_CS_REG(R300_SU_REG_DEST
,
678 1 << (caps
->high_second_pipe
? 3 : 1));
679 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 1) * 4);
680 OUT_CS_RELOC(r300
->query_current
);
683 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
684 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 0) * 4);
685 OUT_CS_RELOC(r300
->query_current
);
688 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
689 " pixel pipes!\n", gb_pipes
);
693 /* And, finally, reset it to normal... */
694 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
698 static void rv530_emit_query_end_single_z(struct r300_context
*r300
,
699 struct r300_query
*query
)
704 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
705 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, query
->num_results
* 4);
706 OUT_CS_RELOC(r300
->query_current
);
707 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
711 static void rv530_emit_query_end_double_z(struct r300_context
*r300
,
712 struct r300_query
*query
)
717 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
718 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 0) * 4);
719 OUT_CS_RELOC(r300
->query_current
);
720 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
721 OUT_CS_REG(R300_ZB_ZPASS_ADDR
, (query
->num_results
+ 1) * 4);
722 OUT_CS_RELOC(r300
->query_current
);
723 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
727 void r300_emit_query_end(struct r300_context
* r300
)
729 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
730 struct r300_query
*query
= r300
->query_current
;
735 if (query
->begin_emitted
== FALSE
)
738 if (caps
->family
== CHIP_RV530
) {
739 if (r300
->screen
->info
.r300_num_z_pipes
== 2)
740 rv530_emit_query_end_double_z(r300
, query
);
742 rv530_emit_query_end_single_z(r300
, query
);
744 r300_emit_query_end_frag_pipes(r300
, query
);
746 query
->begin_emitted
= FALSE
;
747 query
->num_results
+= query
->num_pipes
;
749 /* XXX grab all the results and reset the counter. */
750 if (query
->num_results
>= query
->buf
->size
/ 4 - 4) {
751 query
->num_results
= (query
->buf
->size
/ 4) / 2;
752 fprintf(stderr
, "r300: Rewinding OQBO...\n");
756 void r300_emit_invariant_state(struct r300_context
*r300
,
757 unsigned size
, void *state
)
760 WRITE_CS_TABLE(state
, size
);
763 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
765 struct r300_rs_state
* rs
= state
;
769 OUT_CS_TABLE(rs
->cb_main
, RS_STATE_MAIN_SIZE
);
770 if (rs
->polygon_offset_enable
) {
771 if (r300
->zbuffer_bpp
== 16) {
772 OUT_CS_TABLE(rs
->cb_poly_offset_zb16
, 5);
774 OUT_CS_TABLE(rs
->cb_poly_offset_zb24
, 5);
780 void r300_emit_rs_block_state(struct r300_context
* r300
,
781 unsigned size
, void* state
)
783 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
785 /* It's the same for both INST and IP tables */
786 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
789 if (DBG_ON(r300
, DBG_RS_BLOCK
)) {
790 r500_dump_rs_block(rs
);
792 fprintf(stderr
, "r300: RS emit:\n");
794 for (i
= 0; i
< count
; i
++)
795 fprintf(stderr
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
797 for (i
= 0; i
< count
; i
++)
798 fprintf(stderr
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
800 fprintf(stderr
, " : count: 0x%08x inst_count: 0x%08x\n",
801 rs
->count
, rs
->inst_count
);
805 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
806 OUT_CS(rs
->vap_vtx_state_cntl
);
807 OUT_CS(rs
->vap_vsm_vtx_assm
);
808 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
809 OUT_CS(rs
->vap_out_vtx_fmt
[0]);
810 OUT_CS(rs
->vap_out_vtx_fmt
[1]);
811 OUT_CS_REG_SEQ(R300_GB_ENABLE
, 1);
812 OUT_CS(rs
->gb_enable
);
814 if (r300
->screen
->caps
.is_r500
) {
815 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
817 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
819 OUT_CS_TABLE(rs
->ip
, count
);
821 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
823 OUT_CS(rs
->inst_count
);
825 if (r300
->screen
->caps
.is_r500
) {
826 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
828 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
830 OUT_CS_TABLE(rs
->inst
, count
);
834 void r300_emit_sample_mask(struct r300_context
*r300
,
835 unsigned size
, void *state
)
837 unsigned mask
= (*(unsigned*)state
) & ((1 << 6)-1);
841 OUT_CS_REG(R300_SC_SCREENDOOR
,
842 mask
| (mask
<< 6) | (mask
<< 12) | (mask
<< 18));
846 void r300_emit_scissor_state(struct r300_context
* r300
,
847 unsigned size
, void* state
)
849 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
853 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
854 if (r300
->screen
->caps
.is_r500
) {
855 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
856 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
857 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
858 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
860 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
861 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
862 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
863 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
868 void r300_emit_textures_state(struct r300_context
*r300
,
869 unsigned size
, void *state
)
871 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
872 struct r300_texture_sampler_state
*texstate
;
873 struct r300_resource
*tex
;
875 boolean has_us_format
= r300
->screen
->caps
.has_us_format
;
879 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
881 for (i
= 0; i
< allstate
->count
; i
++) {
882 if ((1 << i
) & allstate
->tx_enable
) {
883 texstate
= &allstate
->regs
[i
];
884 tex
= r300_resource(allstate
->sampler_views
[i
]->base
.texture
);
886 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
887 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
888 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
889 texstate
->border_color
);
891 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
892 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
893 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
895 OUT_CS_REG(R300_TX_OFFSET_0
+ (i
* 4), texstate
->format
.tile_config
);
899 OUT_CS_REG(R500_US_FORMAT0_0
+ (i
* 4),
900 texstate
->format
.us_format0
);
907 void r300_emit_vertex_arrays(struct r300_context
* r300
, int offset
,
908 boolean indexed
, int instance_id
)
910 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
911 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
912 struct r300_resource
*buf
;
914 unsigned vertex_array_count
= r300
->velems
->count
;
915 unsigned packet_size
= (vertex_array_count
* 3 + 1) / 2;
916 struct pipe_vertex_buffer
*vb1
, *vb2
;
917 unsigned *hw_format_size
= r300
->velems
->format_size
;
918 unsigned size1
, size2
, offset1
, offset2
, stride1
, stride2
;
921 BEGIN_CS(2 + packet_size
+ vertex_array_count
* 2);
922 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
923 OUT_CS(vertex_array_count
| (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
925 if (instance_id
== -1) {
926 /* Non-instanced arrays. This ignores instance_divisor and instance_id. */
927 for (i
= 0; i
< vertex_array_count
- 1; i
+= 2) {
928 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
929 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
930 size1
= hw_format_size
[i
];
931 size2
= hw_format_size
[i
+1];
933 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
934 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
935 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
936 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
939 if (vertex_array_count
& 1) {
940 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
941 size1
= hw_format_size
[i
];
943 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
944 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
947 for (i
= 0; i
< vertex_array_count
; i
++) {
948 buf
= r300_resource(vbuf
[velem
[i
].vertex_buffer_index
].buffer
);
952 /* Instanced arrays. */
953 for (i
= 0; i
< vertex_array_count
- 1; i
+= 2) {
954 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
955 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
956 size1
= hw_format_size
[i
];
957 size2
= hw_format_size
[i
+1];
959 if (velem
[i
].instance_divisor
) {
961 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+
962 (instance_id
/ velem
[i
].instance_divisor
) * vb1
->stride
;
964 stride1
= vb1
->stride
;
965 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
;
967 if (velem
[i
+1].instance_divisor
) {
969 offset2
= vb2
->buffer_offset
+ velem
[i
+1].src_offset
+
970 (instance_id
/ velem
[i
+1].instance_divisor
) * vb2
->stride
;
972 stride2
= vb2
->stride
;
973 offset2
= vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
;
976 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(stride1
) |
977 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(stride2
));
982 if (vertex_array_count
& 1) {
983 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
984 size1
= hw_format_size
[i
];
986 if (velem
[i
].instance_divisor
) {
988 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+
989 (instance_id
/ velem
[i
].instance_divisor
) * vb1
->stride
;
991 stride1
= vb1
->stride
;
992 offset1
= vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
;
995 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(stride1
));
999 for (i
= 0; i
< vertex_array_count
; i
++) {
1000 buf
= r300_resource(vbuf
[velem
[i
].vertex_buffer_index
].buffer
);
1007 void r300_emit_vertex_arrays_swtcl(struct r300_context
*r300
, boolean indexed
)
1011 DBG(r300
, DBG_SWTCL
, "r300: Preparing vertex buffer %p for render, "
1012 "vertex size %d\n", r300
->vbo
,
1013 r300
->vertex_info
.size
);
1014 /* Set the pointer to our vertex buffer. The emitted values are this:
1015 * PACKET3 [3D_LOAD_VBPNTR]
1017 * FORMAT [size | stride << 8]
1018 * OFFSET [offset into BO]
1019 * VBPNTR [relocated BO]
1022 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
1023 OUT_CS(1 | (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
1024 OUT_CS(r300
->vertex_info
.size
|
1025 (r300
->vertex_info
.size
<< 8));
1026 OUT_CS(r300
->draw_vbo_offset
);
1029 assert(r300
->vbo_cs
);
1030 cs_winsys
->cs_write_reloc(cs_copy
, r300
->vbo_cs
);
1035 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
1036 unsigned size
, void* state
)
1038 struct r300_vertex_stream_state
*streams
=
1039 (struct r300_vertex_stream_state
*)state
;
1043 if (DBG_ON(r300
, DBG_PSC
)) {
1044 fprintf(stderr
, "r300: PSC emit:\n");
1046 for (i
= 0; i
< streams
->count
; i
++) {
1047 fprintf(stderr
, " : prog_stream_cntl%d: 0x%08x\n", i
,
1048 streams
->vap_prog_stream_cntl
[i
]);
1051 for (i
= 0; i
< streams
->count
; i
++) {
1052 fprintf(stderr
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
1053 streams
->vap_prog_stream_cntl_ext
[i
]);
1058 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
1059 OUT_CS_TABLE(streams
->vap_prog_stream_cntl
, streams
->count
);
1060 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
1061 OUT_CS_TABLE(streams
->vap_prog_stream_cntl_ext
, streams
->count
);
1065 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
1070 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
1074 void r300_emit_vap_invariant_state(struct r300_context
*r300
,
1075 unsigned size
, void *state
)
1078 WRITE_CS_TABLE(state
, size
);
1081 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
1083 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
1084 struct r300_vertex_program_code
* code
= &vs
->code
;
1085 struct r300_screen
* r300screen
= r300
->screen
;
1086 unsigned instruction_count
= code
->length
/ 4;
1088 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
1089 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
1090 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
1091 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
1093 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
1094 vtx_mem_size
/ output_count
, 10);
1095 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 5);
1101 /* R300_VAP_PVS_CODE_CNTL_0
1102 * R300_VAP_PVS_CONST_CNTL
1103 * R300_VAP_PVS_CODE_CNTL_1
1104 * See the r5xx docs for instructions on how to use these. */
1105 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0
, R300_PVS_FIRST_INST(0) |
1106 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
1107 R300_PVS_LAST_INST(instruction_count
- 1));
1108 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1
, instruction_count
- 1);
1110 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
1111 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
1112 OUT_CS_TABLE(code
->body
.d
, code
->length
);
1114 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
1115 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
1116 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
1117 R300_PVS_VF_MAX_VTX_NUM(12) |
1118 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
1120 /* Emit flow control instructions. Even if there are no fc instructions,
1121 * we still need to write the registers to make sure they are cleared. */
1122 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC
, code
->fc_ops
);
1123 if (r300screen
->caps
.is_r500
) {
1124 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0
, R300_VS_MAX_FC_OPS
* 2);
1125 OUT_CS_TABLE(code
->fc_op_addrs
.r500
, R300_VS_MAX_FC_OPS
* 2);
1127 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0
, R300_VS_MAX_FC_OPS
);
1128 OUT_CS_TABLE(code
->fc_op_addrs
.r300
, R300_VS_MAX_FC_OPS
);
1130 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
, R300_VS_MAX_FC_OPS
);
1131 OUT_CS_TABLE(code
->fc_loop_index
, R300_VS_MAX_FC_OPS
);
1136 void r300_emit_vs_constants(struct r300_context
* r300
,
1137 unsigned size
, void *state
)
1140 ((struct r300_vertex_shader
*)r300
->vs_state
.state
)->externals_count
;
1141 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
1142 struct r300_vertex_shader
*vs
= (struct r300_vertex_shader
*)r300
->vs_state
.state
;
1144 int imm_first
= vs
->externals_count
;
1145 int imm_end
= vs
->code
.constants
.Count
;
1146 int imm_count
= vs
->immediates_count
;
1150 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL
,
1151 R300_PVS_CONST_BASE_OFFSET(buf
->buffer_base
) |
1152 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end
- 1, 0)));
1153 if (vs
->externals_count
) {
1154 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1155 (r300
->screen
->caps
.is_r500
?
1156 R500_PVS_CONST_START
: R300_PVS_CONST_START
) + buf
->buffer_base
);
1157 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, count
* 4);
1158 if (buf
->remap_table
){
1159 for (i
= 0; i
< count
; i
++) {
1160 uint32_t *data
= &buf
->ptr
[buf
->remap_table
[i
]*4];
1161 OUT_CS_TABLE(data
, 4);
1164 OUT_CS_TABLE(buf
->ptr
, count
* 4);
1168 /* Emit immediates. */
1170 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
1171 (r300
->screen
->caps
.is_r500
?
1172 R500_PVS_CONST_START
: R300_PVS_CONST_START
) +
1173 buf
->buffer_base
+ imm_first
);
1174 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, imm_count
* 4);
1175 for (i
= imm_first
; i
< imm_end
; i
++) {
1176 const float *data
= vs
->code
.constants
.Constants
[i
].u
.Immediate
;
1177 OUT_CS_TABLE(data
, 4);
1183 void r300_emit_viewport_state(struct r300_context
* r300
,
1184 unsigned size
, void* state
)
1186 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
1190 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
1191 OUT_CS_TABLE(&viewport
->xscale
, 6);
1192 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
1196 void r300_emit_hiz_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1198 struct pipe_framebuffer_state
*fb
=
1199 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1200 struct r300_resource
* tex
;
1203 tex
= r300_resource(fb
->zsbuf
->texture
);
1206 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
,
1207 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
1208 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
1209 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ
, 2);
1211 OUT_CS(tex
->tex
.hiz_dwords
[fb
->zsbuf
->u
.tex
.level
]);
1212 OUT_CS(r300
->hiz_clear_value
);
1215 /* Mark the current zbuffer's hiz ram as in use. */
1216 r300
->hiz_in_use
= TRUE
;
1217 r300
->hiz_func
= HIZ_FUNC_NONE
;
1218 r300_mark_atom_dirty(r300
, &r300
->hyperz_state
);
1221 void r300_emit_zmask_clear(struct r300_context
*r300
, unsigned size
, void *state
)
1223 struct pipe_framebuffer_state
*fb
=
1224 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1225 struct r300_resource
*tex
;
1228 tex
= r300_resource(fb
->zsbuf
->texture
);
1231 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
,
1232 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
1233 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
1234 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK
, 2);
1236 OUT_CS(tex
->tex
.zmask_dwords
[fb
->zsbuf
->u
.tex
.level
]);
1240 /* Mark the current zbuffer's zmask as in use. */
1241 r300
->zmask_in_use
= TRUE
;
1242 r300_mark_atom_dirty(r300
, &r300
->hyperz_state
);
1245 void r300_emit_ztop_state(struct r300_context
* r300
,
1246 unsigned size
, void* state
)
1248 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
1252 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
1256 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
1261 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
1265 boolean
r300_emit_buffer_validate(struct r300_context
*r300
,
1266 boolean do_validate_vertex_buffers
,
1267 struct pipe_resource
*index_buffer
)
1269 struct pipe_framebuffer_state
*fb
=
1270 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1271 struct r300_aa_state
*aa
= (struct r300_aa_state
*)r300
->aa_state
.state
;
1272 struct r300_textures_state
*texstate
=
1273 (struct r300_textures_state
*)r300
->textures_state
.state
;
1274 struct r300_resource
*tex
;
1276 boolean flushed
= FALSE
;
1279 if (r300
->fb_state
.dirty
) {
1280 /* Color buffers... */
1281 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1282 tex
= r300_resource(fb
->cbufs
[i
]->texture
);
1283 assert(tex
&& tex
->buf
&& "cbuf is marked, but NULL!");
1284 r300
->rws
->cs_add_reloc(r300
->cs
, tex
->cs_buf
,
1285 RADEON_USAGE_READWRITE
,
1286 r300_surface(fb
->cbufs
[i
])->domain
);
1288 /* ...depth buffer... */
1290 tex
= r300_resource(fb
->zsbuf
->texture
);
1291 assert(tex
&& tex
->buf
&& "zsbuf is marked, but NULL!");
1292 r300
->rws
->cs_add_reloc(r300
->cs
, tex
->cs_buf
,
1293 RADEON_USAGE_READWRITE
,
1294 r300_surface(fb
->zsbuf
)->domain
);
1297 /* The AA resolve buffer. */
1298 if (r300
->aa_state
.dirty
) {
1300 r300
->rws
->cs_add_reloc(r300
->cs
, aa
->dest
->cs_buf
,
1305 if (r300
->textures_state
.dirty
) {
1306 /* ...textures... */
1307 for (i
= 0; i
< texstate
->count
; i
++) {
1308 if (!(texstate
->tx_enable
& (1 << i
))) {
1312 tex
= r300_resource(texstate
->sampler_views
[i
]->base
.texture
);
1313 r300
->rws
->cs_add_reloc(r300
->cs
, tex
->cs_buf
, RADEON_USAGE_READ
,
1317 /* ...occlusion query buffer... */
1318 if (r300
->query_current
)
1319 r300
->rws
->cs_add_reloc(r300
->cs
, r300
->query_current
->cs_buf
,
1320 RADEON_USAGE_WRITE
, RADEON_DOMAIN_GTT
);
1321 /* ...vertex buffer for SWTCL path... */
1323 r300
->rws
->cs_add_reloc(r300
->cs
, r300
->vbo_cs
,
1324 RADEON_USAGE_READ
, RADEON_DOMAIN_GTT
);
1325 /* ...vertex buffers for HWTCL path... */
1326 if (do_validate_vertex_buffers
&& r300
->vertex_arrays_dirty
) {
1327 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
1328 struct pipe_vertex_buffer
*last
= r300
->vertex_buffer
+
1329 r300
->nr_vertex_buffers
;
1330 struct pipe_resource
*buf
;
1332 for (; vbuf
!= last
; vbuf
++) {
1337 r300
->rws
->cs_add_reloc(r300
->cs
, r300_resource(buf
)->cs_buf
,
1339 r300_resource(buf
)->domain
);
1342 /* ...and index buffer for HWTCL path. */
1344 r300
->rws
->cs_add_reloc(r300
->cs
, r300_resource(index_buffer
)->cs_buf
,
1346 r300_resource(index_buffer
)->domain
);
1348 /* Now do the validation (flush is called inside cs_validate on failure). */
1349 if (!r300
->rws
->cs_validate(r300
->cs
)) {
1350 /* Ooops, an infinite loop, give up. */
1361 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1363 struct r300_atom
* atom
;
1364 unsigned dwords
= 0;
1366 foreach_dirty_atom(r300
, atom
) {
1368 dwords
+= atom
->size
;
1372 /* let's reserve some more, just in case */
1378 unsigned r300_get_num_cs_end_dwords(struct r300_context
*r300
)
1380 unsigned dwords
= 0;
1382 /* Emitted in flush. */
1383 dwords
+= 26; /* emit_query_end */
1384 dwords
+= r300
->hyperz_state
.size
+ 2; /* emit_hyperz_end + zcache flush */
1385 if (r300
->screen
->caps
.is_r500
)
1386 dwords
+= 2; /* emit_index_bias */
1387 if (r300
->screen
->info
.drm_minor
>= 6)
1388 dwords
+= 3; /* MSPOS */
1393 /* Emit all dirty state. */
1394 void r300_emit_dirty_state(struct r300_context
* r300
)
1396 struct r300_atom
*atom
;
1398 foreach_dirty_atom(r300
, atom
) {
1400 atom
->emit(r300
, atom
->size
, atom
->state
);
1401 atom
->dirty
= FALSE
;
1405 r300
->first_dirty
= NULL
;
1406 r300
->last_dirty
= NULL
;