r300-gallium: Fix CS size mismatch
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 /* r300_emit: Functions for emitting state. */
24
25 #include "r300_emit.h"
26
27 void r300_emit_blend_state(struct r300_context* r300,
28 struct r300_blend_state* blend)
29 {
30 CS_LOCALS(r300);
31 BEGIN_CS(7);
32 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 2);
33 OUT_CS(blend->blend_control);
34 OUT_CS(blend->alpha_blend_control);
35 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
36 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
37 END_CS;
38 }
39
40 void r300_emit_blend_color_state(struct r300_context* r300,
41 struct r300_blend_color_state* bc)
42 {
43 struct r300_screen* r300screen = r300_screen(r300->context.screen);
44 CS_LOCALS(r300);
45
46 if (r300screen->caps->is_r500) {
47 BEGIN_CS(3);
48 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
49 OUT_CS(bc->blend_color_red_alpha);
50 OUT_CS(bc->blend_color_green_blue);
51 END_CS;
52 } else {
53 BEGIN_CS(2);
54 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
55 END_CS;
56 }
57 }
58
59 void r300_emit_dsa_state(struct r300_context* r300,
60 struct r300_dsa_state* dsa)
61 {
62 struct r300_screen* r300screen = r300_screen(r300->context.screen);
63 CS_LOCALS(r300);
64
65 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 8);
66 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
67 /* XXX figure out the r300 counterpart for this */
68 if (r300screen->caps->is_r500) {
69 /* OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference); */
70 }
71 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
72 OUT_CS(dsa->z_buffer_control);
73 OUT_CS(dsa->z_stencil_control);
74 OUT_CS(dsa->stencil_ref_mask);
75 OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top);
76 if (r300screen->caps->is_r500) {
77 /* OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); */
78 }
79 END_CS;
80 }
81
82 void r300_emit_fragment_shader(struct r300_context* r300,
83 struct r300_fragment_shader* fs)
84 {
85 int i;
86 CS_LOCALS(r300);
87
88 BEGIN_CS(22);
89
90 OUT_CS_REG(R300_US_CONFIG, fs->indirections);
91 OUT_CS_REG(R300_US_PIXSIZE, fs->shader.stack_size);
92 /* XXX figure out exactly how big the sizes are on this reg */
93 OUT_CS_REG(R300_US_CODE_OFFSET, 0x40);
94 /* XXX figure these ones out a bit better kthnx */
95 OUT_CS_REG(R300_US_CODE_ADDR_0, 0x0);
96 OUT_CS_REG(R300_US_CODE_ADDR_1, 0x0);
97 OUT_CS_REG(R300_US_CODE_ADDR_2, 0x0);
98 OUT_CS_REG(R300_US_CODE_ADDR_3, 0x40 | R300_RGBA_OUT);
99
100 for (i = 0; i < fs->alu_instruction_count; i++) {
101 OUT_CS_REG(R300_US_ALU_RGB_INST_0 + (4 * i),
102 fs->instructions[i].alu_rgb_inst);
103 OUT_CS_REG(R300_US_ALU_RGB_ADDR_0 + (4 * i),
104 fs->instructions[i].alu_rgb_addr);
105 OUT_CS_REG(R300_US_ALU_ALPHA_INST_0 + (4 * i),
106 fs->instructions[i].alu_alpha_inst);
107 OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0 + (4 * i),
108 fs->instructions[i].alu_alpha_addr);
109 }
110
111 END_CS;
112 }
113
114 void r500_emit_fragment_shader(struct r300_context* r300,
115 struct r500_fragment_shader* fs)
116 {
117 int i;
118 struct r300_constant_buffer* constants =
119 &r300->shader_constants[PIPE_SHADER_FRAGMENT];
120 CS_LOCALS(r300);
121
122 BEGIN_CS(9 + (fs->instruction_count * 6) + (constants->count ? 3 : 0) +
123 (constants->count * 4));
124 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
125 OUT_CS_REG(R500_US_PIXSIZE, fs->shader.stack_size);
126 OUT_CS_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) |
127 R500_US_CODE_END_ADDR(fs->instruction_count));
128
129 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
130 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, fs->instruction_count * 6);
131 for (i = 0; i < fs->instruction_count; i++) {
132 OUT_CS(fs->instructions[i].inst0);
133 OUT_CS(fs->instructions[i].inst1);
134 OUT_CS(fs->instructions[i].inst2);
135 OUT_CS(fs->instructions[i].inst3);
136 OUT_CS(fs->instructions[i].inst4);
137 OUT_CS(fs->instructions[i].inst5);
138 }
139
140 if (constants->count) {
141 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
142 R500_GA_US_VECTOR_INDEX_TYPE_CONST);
143 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->count * 4);
144 for (i = 0; i < constants->count; i++) {
145 OUT_CS_32F(constants->constants[i][0]);
146 OUT_CS_32F(constants->constants[i][1]);
147 OUT_CS_32F(constants->constants[i][2]);
148 OUT_CS_32F(constants->constants[i][3]);
149 }
150 }
151
152 END_CS;
153 }
154
155 /* XXX add pitch, stride, clean up */
156 void r300_emit_fb_state(struct r300_context* r300,
157 struct pipe_framebuffer_state* fb)
158 {
159 int i;
160 struct r300_texture* tex;
161 CS_LOCALS(r300);
162
163 BEGIN_CS((6 * fb->nr_cbufs) + (fb->zsbuf ? 6 : 0) + 4);
164 for (i = 0; i < fb->nr_cbufs; i++) {
165 tex = (struct r300_texture*)fb->cbufs[i]->texture;
166 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
167 OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
168
169 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
170 r300_translate_out_fmt(fb->cbufs[i]->format));
171 }
172
173 if (fb->zsbuf) {
174 tex = (struct r300_texture*)fb->zsbuf->texture;
175 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
176 OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
177 if (fb->zsbuf->format == PIPE_FORMAT_Z24S8_UNORM) {
178 OUT_CS_REG(R300_ZB_FORMAT,
179 R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL);
180 } else {
181 OUT_CS_REG(R300_ZB_FORMAT, 0x0);
182 }
183 }
184
185 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
186 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
187 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
188 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
189 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
190 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
191 END_CS;
192 }
193
194 void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs)
195 {
196 CS_LOCALS(r300);
197
198 BEGIN_CS(20);
199 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
200 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
201 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
202 OUT_CS(rs->point_minmax);
203 OUT_CS(rs->line_control);
204 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
205 OUT_CS(rs->depth_scale_front);
206 OUT_CS(rs->depth_offset_front);
207 OUT_CS(rs->depth_scale_back);
208 OUT_CS(rs->depth_offset_back);
209 OUT_CS(rs->polygon_offset_enable);
210 OUT_CS(rs->cull_mode);
211 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
212 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
213 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
214 END_CS;
215 }
216
217 void r300_emit_rs_block_state(struct r300_context* r300,
218 struct r300_rs_block* rs)
219 {
220 int i;
221 struct r300_screen* r300screen = r300_screen(r300->context.screen);
222 CS_LOCALS(r300);
223
224 BEGIN_CS(21);
225 if (r300screen->caps->is_r500) {
226 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
227 } else {
228 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
229 }
230 for (i = 0; i < 8; i++) {
231 OUT_CS(rs->ip[i]);
232 debug_printf("ip %d: 0x%08x\n", i, rs->ip[i]);
233 }
234
235 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
236 OUT_CS(rs->count);
237 OUT_CS(rs->inst_count);
238
239 if (r300screen->caps->is_r500) {
240 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
241 } else {
242 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
243 }
244 for (i = 0; i < 8; i++) {
245 OUT_CS(rs->inst[i]);
246 debug_printf("inst %d: 0x%08x\n", i, rs->inst[i]);
247 }
248
249 debug_printf("count: 0x%08x inst_count: 0x%08x\n", rs->count,
250 rs->inst_count);
251
252 END_CS;
253 }
254
255 void r300_emit_sampler(struct r300_context* r300,
256 struct r300_sampler_state* sampler, unsigned offset)
257 {
258 CS_LOCALS(r300);
259
260 BEGIN_CS(6);
261 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), sampler->filter0);
262 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
263 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
264 END_CS;
265 }
266
267 void r300_emit_scissor_state(struct r300_context* r300,
268 struct r300_scissor_state* scissor)
269 {
270 CS_LOCALS(r300);
271
272 BEGIN_CS(3);
273 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
274 OUT_CS(scissor->scissor_top_left);
275 OUT_CS(scissor->scissor_bottom_right);
276 END_CS;
277 }
278
279 void r300_emit_texture(struct r300_context* r300,
280 struct r300_texture* tex, unsigned offset)
281 {
282 CS_LOCALS(r300);
283
284 BEGIN_CS(10);
285 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), tex->state.format0);
286 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
287 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
288 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
289 OUT_CS_RELOC(tex->buffer, 0,
290 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
291 END_CS;
292 }
293
294 void r300_emit_vertex_format_state(struct r300_context* r300)
295 {
296 int i;
297 CS_LOCALS(r300);
298
299 BEGIN_CS(26);
300 OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info.vinfo.size);
301
302 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
303 OUT_CS(r300->vertex_info.vinfo.hwfmt[0]);
304 OUT_CS(r300->vertex_info.vinfo.hwfmt[1]);
305 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
306 OUT_CS(r300->vertex_info.vinfo.hwfmt[2]);
307 OUT_CS(r300->vertex_info.vinfo.hwfmt[3]);
308 for (i = 0; i < 4; i++) {
309 debug_printf("hwfmt%d: 0x%08x\n", i,
310 r300->vertex_info.vinfo.hwfmt[i]);
311 }
312
313 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
314 for (i = 0; i < 8; i++) {
315 OUT_CS(r300->vertex_info.vap_prog_stream_cntl[i]);
316 debug_printf("prog_stream_cntl%d: 0x%08x\n", i,
317 r300->vertex_info.vap_prog_stream_cntl[i]);
318 }
319 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
320 for (i = 0; i < 8; i++) {
321 OUT_CS(r300->vertex_info.vap_prog_stream_cntl_ext[i]);
322 debug_printf("prog_stream_cntl_ext%d: 0x%08x\n", i,
323 r300->vertex_info.vap_prog_stream_cntl_ext[i]);
324 }
325 END_CS;
326 }
327
328 void r300_emit_vertex_shader(struct r300_context* r300,
329 struct r300_vertex_shader* vs)
330 {
331 int i;
332 struct r300_screen* r300screen = r300_screen(r300->context.screen);
333 struct r300_constant_buffer* constants =
334 &r300->shader_constants[PIPE_SHADER_VERTEX];
335 CS_LOCALS(r300);
336
337 if (!r300screen->caps->has_tcl) {
338 debug_printf("r300: Implementation error: emit_vertex_shader called,"
339 " but has_tcl is FALSE!\n");
340 return;
341 }
342
343 if (constants->count) {
344 BEGIN_CS(16 + (vs->instruction_count * 4) + (constants->count * 4));
345 } else {
346 BEGIN_CS(13 + (vs->instruction_count * 4) + (constants->count * 4));
347 }
348
349 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) |
350 R300_PVS_LAST_INST(vs->instruction_count - 1));
351 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, vs->instruction_count - 1);
352
353 /* XXX */
354 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x0);
355
356 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
357 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, vs->instruction_count * 4);
358 for (i = 0; i < vs->instruction_count; i++) {
359 OUT_CS(vs->instructions[i].inst0);
360 OUT_CS(vs->instructions[i].inst1);
361 OUT_CS(vs->instructions[i].inst2);
362 OUT_CS(vs->instructions[i].inst3);
363 }
364
365 if (constants->count) {
366 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
367 (r300screen->caps->is_r500 ?
368 R500_PVS_CONST_START : R300_PVS_CONST_START));
369 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->count * 4);
370 for (i = 0; i < constants->count; i++) {
371 OUT_CS_32F(constants->constants[i][0]);
372 OUT_CS_32F(constants->constants[i][1]);
373 OUT_CS_32F(constants->constants[i][2]);
374 OUT_CS_32F(constants->constants[i][3]);
375 }
376 }
377
378 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(10) |
379 R300_PVS_NUM_CNTLRS(5) |
380 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
381 R300_PVS_VF_MAX_VTX_NUM(12));
382 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
383 END_CS;
384
385 }
386
387 void r300_emit_viewport_state(struct r300_context* r300,
388 struct r300_viewport_state* viewport)
389 {
390 CS_LOCALS(r300);
391
392 BEGIN_CS(9);
393 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
394 OUT_CS_32F(viewport->xscale);
395 OUT_CS_32F(viewport->xoffset);
396 OUT_CS_32F(viewport->yscale);
397 OUT_CS_32F(viewport->yoffset);
398 OUT_CS_32F(viewport->zscale);
399 OUT_CS_32F(viewport->zoffset);
400
401 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
402 END_CS;
403 }
404
405 void r300_flush_textures(struct r300_context* r300)
406 {
407 CS_LOCALS(r300);
408
409 BEGIN_CS(4);
410 OUT_CS_REG(R300_TX_INVALTAGS, 0);
411 OUT_CS_REG(R300_TX_ENABLE, (1 << r300->texture_count) - 1);
412 END_CS;
413 }
414
415 /* Emit all dirty state. */
416 void r300_emit_dirty_state(struct r300_context* r300)
417 {
418 struct r300_screen* r300screen = r300_screen(r300->context.screen);
419 int i;
420 int dirty_tex = 0;
421
422 if (!(r300->dirty_state) && !(r300->dirty_hw)) {
423 return;
424 }
425
426 r300_update_derived_state(r300);
427
428 /* XXX check size */
429
430 if (r300->dirty_state & R300_NEW_BLEND) {
431 r300_emit_blend_state(r300, r300->blend_state);
432 r300->dirty_state &= ~R300_NEW_BLEND;
433 }
434
435 if (r300->dirty_state & R300_NEW_BLEND_COLOR) {
436 r300_emit_blend_color_state(r300, r300->blend_color_state);
437 r300->dirty_state &= ~R300_NEW_BLEND_COLOR;
438 }
439
440 if (r300->dirty_state & R300_NEW_DSA) {
441 r300_emit_dsa_state(r300, r300->dsa_state);
442 r300->dirty_state &= ~R300_NEW_DSA;
443 }
444
445 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
446 if (r300screen->caps->is_r500) {
447 r500_emit_fragment_shader(r300,
448 (struct r500_fragment_shader*)r300->fs);
449 } else {
450 r300_emit_fragment_shader(r300,
451 (struct r300_fragment_shader*)r300->fs);
452 }
453 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
454 }
455
456 if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
457 r300_emit_fb_state(r300, &r300->framebuffer_state);
458 r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
459 }
460
461 if (r300->dirty_state & R300_NEW_RASTERIZER) {
462 r300_emit_rs_state(r300, r300->rs_state);
463 r300->dirty_state &= ~R300_NEW_RASTERIZER;
464 }
465
466 if (r300->dirty_state & R300_NEW_RS_BLOCK) {
467 r300_emit_rs_block_state(r300, r300->rs_block);
468 r300->dirty_state &= ~R300_NEW_RS_BLOCK;
469 }
470
471 if (r300->dirty_state & R300_ANY_NEW_SAMPLERS) {
472 for (i = 0; i < r300->sampler_count; i++) {
473 if (r300->dirty_state & (R300_NEW_SAMPLER << i)) {
474 r300_emit_sampler(r300, r300->sampler_states[i], i);
475 r300->dirty_state &= ~(R300_NEW_SAMPLER << i);
476 dirty_tex++;
477 }
478 }
479 }
480
481 if (r300->dirty_state & R300_NEW_SCISSOR) {
482 r300_emit_scissor_state(r300, r300->scissor_state);
483 r300->dirty_state &= ~R300_NEW_SCISSOR;
484 }
485
486 if (r300->dirty_state & R300_ANY_NEW_TEXTURES) {
487 for (i = 0; i < r300->texture_count; i++) {
488 if (r300->dirty_state & (R300_NEW_TEXTURE << i)) {
489 r300_emit_texture(r300, r300->textures[i], i);
490 r300->dirty_state &= ~(R300_NEW_TEXTURE << i);
491 dirty_tex++;
492 }
493 }
494 }
495
496 if (r300->dirty_state & R300_NEW_VIEWPORT) {
497 r300_emit_viewport_state(r300, r300->viewport_state);
498 r300->dirty_state &= ~R300_NEW_VIEWPORT;
499 }
500
501 if (dirty_tex) {
502 r300_flush_textures(r300);
503 }
504
505 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
506 r300_emit_vertex_format_state(r300);
507 r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
508 }
509 }