41a12708ceeb079364bf99e867a7c53d062b19db
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29
30 #include "r300_context.h"
31 #include "r300_cb.h"
32 #include "r300_cs.h"
33 #include "r300_emit.h"
34 #include "r300_fs.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
37 #include "r300_vs.h"
38
39 void r300_emit_blend_state(struct r300_context* r300,
40 unsigned size, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 struct pipe_framebuffer_state* fb =
44 (struct pipe_framebuffer_state*)r300->fb_state.state;
45 CS_LOCALS(r300);
46
47 if (fb->nr_cbufs) {
48 WRITE_CS_TABLE(blend->cb, size);
49 } else {
50 WRITE_CS_TABLE(blend->cb_no_readwrite, size);
51 }
52 }
53
54 void r300_emit_blend_color_state(struct r300_context* r300,
55 unsigned size, void* state)
56 {
57 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
58 CS_LOCALS(r300);
59
60 WRITE_CS_TABLE(bc->cb, size);
61 }
62
63 void r300_emit_clip_state(struct r300_context* r300,
64 unsigned size, void* state)
65 {
66 struct r300_clip_state* clip = (struct r300_clip_state*)state;
67 CS_LOCALS(r300);
68
69 WRITE_CS_TABLE(clip->cb, size);
70 }
71
72 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
73 {
74 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
75 struct pipe_framebuffer_state* fb =
76 (struct pipe_framebuffer_state*)r300->fb_state.state;
77 CS_LOCALS(r300);
78
79 if (fb->zsbuf) {
80 WRITE_CS_TABLE(&dsa->cb_begin, size);
81 } else {
82 WRITE_CS_TABLE(dsa->cb_no_readwrite, size);
83 }
84 }
85
86 static void get_rc_constant_state(
87 float vec[4],
88 struct r300_context * r300,
89 struct rc_constant * constant)
90 {
91 struct r300_textures_state* texstate = r300->textures_state.state;
92 struct r300_texture *tex;
93
94 assert(constant->Type == RC_CONSTANT_STATE);
95
96 /* vec should either be (0, 0, 0, 1), which should be a relatively safe
97 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
98 * state factors. */
99
100 switch (constant->u.State[0]) {
101 /* Factor for converting rectangle coords to
102 * normalized coords. Should only show up on non-r500. */
103 case RC_STATE_R300_TEXRECT_FACTOR:
104 tex = r300_texture(texstate->sampler_views[constant->u.State[1]]->base.texture);
105 vec[0] = 1.0 / tex->desc.width0;
106 vec[1] = 1.0 / tex->desc.height0;
107 vec[2] = 0;
108 vec[3] = 1;
109 break;
110
111 case RC_STATE_R300_TEXSCALE_FACTOR:
112 tex = r300_texture(texstate->sampler_views[constant->u.State[1]]->base.texture);
113 /* Add a small number to the texture size to work around rounding errors in hw. */
114 vec[0] = tex->desc.b.b.width0 / (tex->desc.width0 + 0.001f);
115 vec[1] = tex->desc.b.b.height0 / (tex->desc.height0 + 0.001f);
116 vec[2] = tex->desc.b.b.depth0 / (tex->desc.depth0 + 0.001f);
117 vec[3] = 1;
118 break;
119
120 case RC_STATE_R300_VIEWPORT_SCALE:
121 vec[0] = r300->viewport.scale[0];
122 vec[1] = r300->viewport.scale[1];
123 vec[2] = r300->viewport.scale[2];
124 vec[3] = 1;
125 break;
126
127 case RC_STATE_R300_VIEWPORT_OFFSET:
128 vec[0] = r300->viewport.translate[0];
129 vec[1] = r300->viewport.translate[1];
130 vec[2] = r300->viewport.translate[2];
131 vec[3] = 1;
132 break;
133
134 default:
135 fprintf(stderr, "r300: Implementation error: "
136 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
137 vec[0] = 0;
138 vec[1] = 0;
139 vec[2] = 0;
140 vec[3] = 1;
141 }
142 }
143
144 /* Convert a normal single-precision float into the 7.16 format
145 * used by the R300 fragment shader.
146 */
147 uint32_t pack_float24(float f)
148 {
149 union {
150 float fl;
151 uint32_t u;
152 } u;
153 float mantissa;
154 int exponent;
155 uint32_t float24 = 0;
156
157 if (f == 0.0)
158 return 0;
159
160 u.fl = f;
161
162 mantissa = frexpf(f, &exponent);
163
164 /* Handle -ve */
165 if (mantissa < 0) {
166 float24 |= (1 << 23);
167 mantissa = mantissa * -1.0;
168 }
169 /* Handle exponent, bias of 63 */
170 exponent += 62;
171 float24 |= (exponent << 16);
172 /* Kill 7 LSB of mantissa */
173 float24 |= (u.u & 0x7FFFFF) >> 7;
174
175 return float24;
176 }
177
178 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
179 {
180 struct r300_fragment_shader *fs = r300_fs(r300);
181 CS_LOCALS(r300);
182
183 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
184 }
185
186 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
187 {
188 struct r300_fragment_shader *fs = r300_fs(r300);
189 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
190 unsigned count = fs->shader->externals_count;
191 unsigned i, j;
192 CS_LOCALS(r300);
193
194 if (count == 0)
195 return;
196
197 BEGIN_CS(size);
198 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
199 if (buf->remap_table){
200 for (i = 0; i < count; i++) {
201 float *data = (float*)&buf->ptr[buf->remap_table[i]*4];
202 for (j = 0; j < 4; j++)
203 OUT_CS(pack_float24(data[j]));
204 }
205 } else {
206 for (i = 0; i < count; i++)
207 for (j = 0; j < 4; j++)
208 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
209 }
210
211 END_CS;
212 }
213
214 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
215 {
216 struct r300_fragment_shader *fs = r300_fs(r300);
217 struct rc_constant_list *constants = &fs->shader->code.constants;
218 unsigned i;
219 unsigned count = fs->shader->rc_state_count;
220 unsigned first = fs->shader->externals_count;
221 unsigned end = constants->Count;
222 unsigned j;
223 CS_LOCALS(r300);
224
225 if (count == 0)
226 return;
227
228 BEGIN_CS(size);
229 for(i = first; i < end; ++i) {
230 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
231 float data[4];
232
233 get_rc_constant_state(data, r300, &constants->Constants[i]);
234
235 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
236 for (j = 0; j < 4; j++)
237 OUT_CS(pack_float24(data[j]));
238 }
239 }
240 END_CS;
241 }
242
243 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
244 {
245 struct r300_fragment_shader *fs = r300_fs(r300);
246 CS_LOCALS(r300);
247
248 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
249 }
250
251 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
252 {
253 struct r300_fragment_shader *fs = r300_fs(r300);
254 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
255 unsigned count = fs->shader->externals_count;
256 CS_LOCALS(r300);
257
258 if (count == 0)
259 return;
260
261 BEGIN_CS(size);
262 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
263 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
264 if (buf->remap_table){
265 for (unsigned i = 0; i < count; i++) {
266 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
267 OUT_CS_TABLE(data, 4);
268 }
269 } else {
270 OUT_CS_TABLE(buf->ptr, count * 4);
271 }
272 END_CS;
273 }
274
275 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
276 {
277 struct r300_fragment_shader *fs = r300_fs(r300);
278 struct rc_constant_list *constants = &fs->shader->code.constants;
279 unsigned i;
280 unsigned count = fs->shader->rc_state_count;
281 unsigned first = fs->shader->externals_count;
282 unsigned end = constants->Count;
283 CS_LOCALS(r300);
284
285 if (count == 0)
286 return;
287
288 BEGIN_CS(size);
289 for(i = first; i < end; ++i) {
290 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
291 float data[4];
292
293 get_rc_constant_state(data, r300, &constants->Constants[i]);
294
295 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
296 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
297 (i & R500_GA_US_VECTOR_INDEX_MASK));
298 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
299 OUT_CS_TABLE(data, 4);
300 }
301 }
302 END_CS;
303 }
304
305 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
306 {
307 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
308 struct pipe_framebuffer_state* fb =
309 (struct pipe_framebuffer_state*)r300->fb_state.state;
310 uint32_t height = fb->height;
311 uint32_t width = fb->width;
312 CS_LOCALS(r300);
313
314 if (r300->cbzb_clear) {
315 struct r300_surface *surf = r300_surface(fb->cbufs[0]);
316
317 height = surf->cbzb_height;
318 width = surf->cbzb_width;
319 }
320
321 DBG(r300, DBG_SCISSOR,
322 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
323 width, height, r300->cbzb_clear ? "YES" : "NO");
324
325 BEGIN_CS(size);
326
327 /* Set up scissors.
328 * By writing to the SC registers, SC & US assert idle. */
329 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
330 if (r300->screen->caps.is_r500) {
331 OUT_CS(0);
332 OUT_CS(((width - 1) << R300_SCISSORS_X_SHIFT) |
333 ((height - 1) << R300_SCISSORS_Y_SHIFT));
334 } else {
335 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
336 (1440 << R300_SCISSORS_Y_SHIFT));
337 OUT_CS(((width + 1440-1) << R300_SCISSORS_X_SHIFT) |
338 ((height + 1440-1) << R300_SCISSORS_Y_SHIFT));
339 }
340
341 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
342 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
343 END_CS;
344 }
345
346 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
347 {
348 struct r300_aa_state *aa = (struct r300_aa_state*)state;
349 CS_LOCALS(r300);
350
351 BEGIN_CS(size);
352 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
353
354 if (aa->dest) {
355 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 1);
356 OUT_CS_RELOC(aa->dest->cs_buffer, aa->dest->offset, 0, aa->dest->domain);
357
358 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_PITCH, 1);
359 OUT_CS_RELOC(aa->dest->cs_buffer, aa->dest->pitch, 0, aa->dest->domain);
360 }
361
362 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, aa->aaresolve_ctl);
363 END_CS;
364 }
365
366 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
367 {
368 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
369 struct r300_surface* surf;
370 unsigned i;
371 boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
372 uint32_t rb3d_cctl = 0;
373
374 CS_LOCALS(r300);
375
376 BEGIN_CS(size);
377
378 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
379 * what we usually want. */
380 if (r300->screen->caps.is_r500) {
381 rb3d_cctl = R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE;
382 }
383 if (fb->nr_cbufs &&
384 r300_fragment_shader_writes_all(r300_fs(r300))) {
385 rb3d_cctl |= R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs);
386 }
387
388 OUT_CS_REG(R300_RB3D_CCTL, rb3d_cctl);
389
390 /* Set up colorbuffers. */
391 for (i = 0; i < fb->nr_cbufs; i++) {
392 surf = r300_surface(fb->cbufs[i]);
393
394 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
395 OUT_CS_RELOC(surf->cs_buffer, surf->offset, 0, surf->domain);
396
397 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
398 OUT_CS_RELOC(surf->cs_buffer, surf->pitch, 0, surf->domain);
399 }
400
401 /* Set up the ZB part of the CBZB clear. */
402 if (r300->cbzb_clear) {
403 surf = r300_surface(fb->cbufs[0]);
404
405 OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format);
406
407 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
408 OUT_CS_RELOC(surf->cs_buffer, surf->cbzb_midpoint_offset, 0, surf->domain);
409
410 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
411 OUT_CS_RELOC(surf->cs_buffer, surf->cbzb_pitch, 0, surf->domain);
412
413 DBG(r300, DBG_CBZB,
414 "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format,
415 surf->cbzb_pitch);
416 }
417 /* Set up a zbuffer. */
418 else if (fb->zsbuf) {
419 surf = r300_surface(fb->zsbuf);
420
421 OUT_CS_REG(R300_ZB_FORMAT, surf->format);
422
423 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
424 OUT_CS_RELOC(surf->cs_buffer, surf->offset, 0, surf->domain);
425
426 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
427 OUT_CS_RELOC(surf->cs_buffer, surf->pitch, 0, surf->domain);
428
429 if (can_hyperz) {
430 uint32_t surf_pitch;
431 struct r300_texture *tex;
432 int level = surf->base.u.tex.level;
433 tex = r300_texture(surf->base.texture);
434
435 surf_pitch = surf->pitch & R300_DEPTHPITCH_MASK;
436 /* HiZ RAM. */
437 if (r300->screen->caps.hiz_ram) {
438 if (tex->hiz_mem[level]) {
439 OUT_CS_REG(R300_ZB_HIZ_OFFSET, tex->hiz_mem[level]->ofs << 2);
440 OUT_CS_REG(R300_ZB_HIZ_PITCH, surf_pitch);
441 } else {
442 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
443 OUT_CS_REG(R300_ZB_HIZ_PITCH, 0);
444 }
445 }
446 /* Z Mask RAM. (compressed zbuffer) */
447 if (tex->zmask_mem[level]) {
448 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, tex->zmask_mem[level]->ofs << 2);
449 OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf_pitch);
450 } else {
451 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
452 OUT_CS_REG(R300_ZB_ZMASK_PITCH, 0);
453 }
454 }
455 }
456
457 END_CS;
458 }
459
460 void r300_emit_hyperz_state(struct r300_context *r300,
461 unsigned size, void *state)
462 {
463 struct r300_hyperz_state *z = state;
464 CS_LOCALS(r300);
465 if (z->flush)
466 WRITE_CS_TABLE(&z->cb_flush_begin, size);
467 else
468 WRITE_CS_TABLE(&z->cb_begin, size - 2);
469 }
470
471 void r300_emit_hyperz_end(struct r300_context *r300)
472 {
473 struct r300_hyperz_state z =
474 *(struct r300_hyperz_state*)r300->hyperz_state.state;
475
476 z.flush = 1;
477 z.zb_bw_cntl = 0;
478 z.zb_depthclearvalue = 0;
479 z.sc_hyperz = R300_SC_HYPERZ_ADJ_2;
480 z.gb_z_peq_config = 0;
481
482 r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z);
483 }
484
485 void r300_emit_fb_state_pipelined(struct r300_context *r300,
486 unsigned size, void *state)
487 {
488 struct pipe_framebuffer_state* fb =
489 (struct pipe_framebuffer_state*)r300->fb_state.state;
490 unsigned i, num_cbufs = fb->nr_cbufs;
491 CS_LOCALS(r300);
492
493 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
494 * marked as UNUSED in the US block. */
495 if (r300_fragment_shader_writes_all(r300_fs(r300))) {
496 num_cbufs = MIN2(num_cbufs, 1);
497 }
498
499 BEGIN_CS(size);
500
501 /* Colorbuffer format in the US block.
502 * (must be written after unpipelined regs) */
503 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
504 for (i = 0; i < num_cbufs; i++) {
505 OUT_CS(r300_surface(fb->cbufs[i])->format);
506 }
507 for (; i < 4; i++) {
508 OUT_CS(R300_US_OUT_FMT_UNUSED);
509 }
510
511 /* Multisampling. Depends on framebuffer sample count.
512 * These are pipelined regs and as such cannot be moved
513 * to the AA state. */
514 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
515 unsigned mspos0 = 0x66666666;
516 unsigned mspos1 = 0x6666666;
517
518 if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) {
519 /* Subsample placement. These may not be optimal. */
520 switch (fb->cbufs[0]->texture->nr_samples) {
521 case 2:
522 mspos0 = 0x33996633;
523 mspos1 = 0x6666663;
524 break;
525 case 3:
526 mspos0 = 0x33936933;
527 mspos1 = 0x6666663;
528 break;
529 case 4:
530 mspos0 = 0x33939933;
531 mspos1 = 0x3966663;
532 break;
533 case 6:
534 mspos0 = 0x22a2aa22;
535 mspos1 = 0x2a65672;
536 break;
537 default:
538 debug_printf("r300: Bad number of multisamples!\n");
539 }
540 }
541
542 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
543 OUT_CS(mspos0);
544 OUT_CS(mspos1);
545 }
546 END_CS;
547 }
548
549 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
550 {
551 struct r300_query *query = r300->query_current;
552 CS_LOCALS(r300);
553
554 if (!query)
555 return;
556
557 BEGIN_CS(size);
558 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
559 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
560 } else {
561 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
562 }
563 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
564 END_CS;
565 query->begin_emitted = TRUE;
566 query->flushed = FALSE;
567 }
568
569 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
570 struct r300_query *query)
571 {
572 struct r300_capabilities* caps = &r300->screen->caps;
573 struct r300_winsys_cs_buffer *buf = r300->query_current->cs_buffer;
574 CS_LOCALS(r300);
575
576 assert(caps->num_frag_pipes);
577
578 BEGIN_CS(6 * caps->num_frag_pipes + 2);
579 /* I'm not so sure I like this switch, but it's hard to be elegant
580 * when there's so many special cases...
581 *
582 * So here's the basic idea. For each pipe, enable writes to it only,
583 * then put out the relocation for ZPASS_ADDR, taking into account a
584 * 4-byte offset for each pipe. RV380 and older are special; they have
585 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
586 * so there's a chipset cap for that. */
587 switch (caps->num_frag_pipes) {
588 case 4:
589 /* pipe 3 only */
590 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
591 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
592 OUT_CS_RELOC(buf, (query->num_results + 3) * 4,
593 0, query->domain);
594 case 3:
595 /* pipe 2 only */
596 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
597 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
598 OUT_CS_RELOC(buf, (query->num_results + 2) * 4,
599 0, query->domain);
600 case 2:
601 /* pipe 1 only */
602 /* As mentioned above, accomodate RV380 and older. */
603 OUT_CS_REG(R300_SU_REG_DEST,
604 1 << (caps->high_second_pipe ? 3 : 1));
605 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
606 OUT_CS_RELOC(buf, (query->num_results + 1) * 4,
607 0, query->domain);
608 case 1:
609 /* pipe 0 only */
610 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
611 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
612 OUT_CS_RELOC(buf, (query->num_results + 0) * 4,
613 0, query->domain);
614 break;
615 default:
616 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
617 " pixel pipes!\n", caps->num_frag_pipes);
618 abort();
619 }
620
621 /* And, finally, reset it to normal... */
622 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
623 END_CS;
624 }
625
626 static void rv530_emit_query_end_single_z(struct r300_context *r300,
627 struct r300_query *query)
628 {
629 struct r300_winsys_cs_buffer *buf = r300->query_current->cs_buffer;
630 CS_LOCALS(r300);
631
632 BEGIN_CS(8);
633 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
634 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
635 OUT_CS_RELOC(buf, query->num_results * 4, 0, query->domain);
636 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
637 END_CS;
638 }
639
640 static void rv530_emit_query_end_double_z(struct r300_context *r300,
641 struct r300_query *query)
642 {
643 struct r300_winsys_cs_buffer *buf = r300->query_current->cs_buffer;
644 CS_LOCALS(r300);
645
646 BEGIN_CS(14);
647 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
648 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
649 OUT_CS_RELOC(buf, (query->num_results + 0) * 4, 0, query->domain);
650 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
651 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
652 OUT_CS_RELOC(buf, (query->num_results + 1) * 4, 0, query->domain);
653 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
654 END_CS;
655 }
656
657 void r300_emit_query_end(struct r300_context* r300)
658 {
659 struct r300_capabilities *caps = &r300->screen->caps;
660 struct r300_query *query = r300->query_current;
661
662 if (!query)
663 return;
664
665 if (query->begin_emitted == FALSE)
666 return;
667
668 if (caps->family == CHIP_FAMILY_RV530) {
669 if (caps->num_z_pipes == 2)
670 rv530_emit_query_end_double_z(r300, query);
671 else
672 rv530_emit_query_end_single_z(r300, query);
673 } else
674 r300_emit_query_end_frag_pipes(r300, query);
675
676 query->begin_emitted = FALSE;
677 query->num_results += query->num_pipes;
678
679 /* XXX grab all the results and reset the counter. */
680 if (query->num_results >= query->buffer_size / 4 - 4) {
681 query->num_results = (query->buffer_size / 4) / 2;
682 fprintf(stderr, "r300: Rewinding OQBO...\n");
683 }
684 }
685
686 void r300_emit_invariant_state(struct r300_context *r300,
687 unsigned size, void *state)
688 {
689 CS_LOCALS(r300);
690 WRITE_CS_TABLE(state, size);
691 }
692
693 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
694 {
695 struct r300_rs_state* rs = state;
696 CS_LOCALS(r300);
697
698 BEGIN_CS(size);
699 OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE);
700 if (rs->polygon_offset_enable) {
701 if (r300->zbuffer_bpp == 16) {
702 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
703 } else {
704 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
705 }
706 }
707 END_CS;
708 }
709
710 void r300_emit_rs_block_state(struct r300_context* r300,
711 unsigned size, void* state)
712 {
713 struct r300_rs_block* rs = (struct r300_rs_block*)state;
714 unsigned i;
715 /* It's the same for both INST and IP tables */
716 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
717 CS_LOCALS(r300);
718
719 if (DBG_ON(r300, DBG_RS_BLOCK)) {
720 r500_dump_rs_block(rs);
721
722 fprintf(stderr, "r300: RS emit:\n");
723
724 for (i = 0; i < count; i++)
725 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]);
726
727 for (i = 0; i < count; i++)
728 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]);
729
730 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n",
731 rs->count, rs->inst_count);
732 }
733
734 BEGIN_CS(size);
735 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
736 OUT_CS(rs->vap_vtx_state_cntl);
737 OUT_CS(rs->vap_vsm_vtx_assm);
738 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
739 OUT_CS(rs->vap_out_vtx_fmt[0]);
740 OUT_CS(rs->vap_out_vtx_fmt[1]);
741 OUT_CS_REG_SEQ(R300_GB_ENABLE, 1);
742 OUT_CS(rs->gb_enable);
743
744 if (r300->screen->caps.is_r500) {
745 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
746 } else {
747 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
748 }
749 OUT_CS_TABLE(rs->ip, count);
750
751 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
752 OUT_CS(rs->count);
753 OUT_CS(rs->inst_count);
754
755 if (r300->screen->caps.is_r500) {
756 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
757 } else {
758 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
759 }
760 OUT_CS_TABLE(rs->inst, count);
761 END_CS;
762 }
763
764 void r300_emit_scissor_state(struct r300_context* r300,
765 unsigned size, void* state)
766 {
767 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
768 CS_LOCALS(r300);
769
770 BEGIN_CS(size);
771 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
772 if (r300->screen->caps.is_r500) {
773 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
774 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
775 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
776 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
777 } else {
778 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
779 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
780 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
781 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
782 }
783 END_CS;
784 }
785
786 void r300_emit_textures_state(struct r300_context *r300,
787 unsigned size, void *state)
788 {
789 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
790 struct r300_texture_sampler_state *texstate;
791 struct r300_texture *tex;
792 unsigned i;
793 CS_LOCALS(r300);
794
795 BEGIN_CS(size);
796 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
797
798 for (i = 0; i < allstate->count; i++) {
799 if ((1 << i) & allstate->tx_enable) {
800 texstate = &allstate->regs[i];
801 tex = r300_texture(allstate->sampler_views[i]->base.texture);
802
803 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
804 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
805 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
806 texstate->border_color);
807
808 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
809 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
810 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
811
812 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
813 OUT_CS_TEX_RELOC(tex, texstate->format.tile_config, tex->domain,
814 0);
815 }
816 }
817 END_CS;
818 }
819
820 static void r300_update_vertex_arrays_cb(struct r300_context *r300, unsigned packet_size)
821 {
822 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
823 struct pipe_vertex_element *velem = r300->velems->velem;
824 unsigned *hw_format_size = r300->velems->hw_format_size;
825 unsigned size1, size2, vertex_array_count = r300->velems->count;
826 int i;
827 CB_LOCALS;
828
829 BEGIN_CB(r300->vertex_arrays_cb, packet_size);
830 for (i = 0; i < vertex_array_count - 1; i += 2) {
831 vb1 = &vbuf[velem[i].vertex_buffer_index];
832 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
833 size1 = hw_format_size[i];
834 size2 = hw_format_size[i+1];
835
836 OUT_CB(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
837 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
838 OUT_CB(vb1->buffer_offset + velem[i].src_offset);
839 OUT_CB(vb2->buffer_offset + velem[i+1].src_offset);
840 }
841
842 if (vertex_array_count & 1) {
843 vb1 = &vbuf[velem[i].vertex_buffer_index];
844 size1 = hw_format_size[i];
845
846 OUT_CB(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
847 OUT_CB(vb1->buffer_offset + velem[i].src_offset);
848 }
849 END_CB;
850
851 r300->vertex_arrays_dirty = FALSE;
852 }
853
854 void r300_emit_vertex_arrays(struct r300_context* r300, int offset, boolean indexed)
855 {
856 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
857 struct pipe_resource **valid_vbuf = r300->valid_vertex_buffer;
858 struct pipe_vertex_element *velem = r300->velems->velem;
859 struct r300_buffer *buf;
860 int i;
861 unsigned vertex_array_count = r300->velems->count;
862 unsigned packet_size = (vertex_array_count * 3 + 1) / 2;
863 CS_LOCALS(r300);
864
865 BEGIN_CS(2 + packet_size + vertex_array_count * 2);
866 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
867 OUT_CS(vertex_array_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
868
869 if (!offset) {
870 if (r300->vertex_arrays_dirty) {
871 r300_update_vertex_arrays_cb(r300, packet_size);
872 }
873 OUT_CS_TABLE(r300->vertex_arrays_cb, packet_size);
874 } else {
875 struct pipe_vertex_buffer *vb1, *vb2;
876 unsigned *hw_format_size = r300->velems->hw_format_size;
877 unsigned size1, size2;
878
879 for (i = 0; i < vertex_array_count - 1; i += 2) {
880 vb1 = &vbuf[velem[i].vertex_buffer_index];
881 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
882 size1 = hw_format_size[i];
883 size2 = hw_format_size[i+1];
884
885 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
886 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
887 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
888 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
889 }
890
891 if (vertex_array_count & 1) {
892 vb1 = &vbuf[velem[i].vertex_buffer_index];
893 size1 = hw_format_size[i];
894
895 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
896 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
897 }
898 }
899
900 for (i = 0; i < vertex_array_count; i++) {
901 buf = r300_buffer(valid_vbuf[velem[i].vertex_buffer_index]);
902 OUT_CS_BUF_RELOC_NO_OFFSET(&buf->b.b, buf->domain, 0);
903 }
904 END_CS;
905 }
906
907 void r300_emit_vertex_arrays_swtcl(struct r300_context *r300, boolean indexed)
908 {
909 CS_LOCALS(r300);
910
911 DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, "
912 "vertex size %d\n", r300->vbo,
913 r300->vertex_info.size);
914 /* Set the pointer to our vertex buffer. The emitted values are this:
915 * PACKET3 [3D_LOAD_VBPNTR]
916 * COUNT [1]
917 * FORMAT [size | stride << 8]
918 * OFFSET [offset into BO]
919 * VBPNTR [relocated BO]
920 */
921 BEGIN_CS(7);
922 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
923 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
924 OUT_CS(r300->vertex_info.size |
925 (r300->vertex_info.size << 8));
926 OUT_CS(r300->draw_vbo_offset);
927 OUT_CS_BUF_RELOC(r300->vbo, 0, r300_buffer(r300->vbo)->domain, 0);
928 END_CS;
929 }
930
931 void r300_emit_vertex_stream_state(struct r300_context* r300,
932 unsigned size, void* state)
933 {
934 struct r300_vertex_stream_state *streams =
935 (struct r300_vertex_stream_state*)state;
936 unsigned i;
937 CS_LOCALS(r300);
938
939 if (DBG_ON(r300, DBG_PSC)) {
940 fprintf(stderr, "r300: PSC emit:\n");
941
942 for (i = 0; i < streams->count; i++) {
943 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i,
944 streams->vap_prog_stream_cntl[i]);
945 }
946
947 for (i = 0; i < streams->count; i++) {
948 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
949 streams->vap_prog_stream_cntl_ext[i]);
950 }
951 }
952
953 BEGIN_CS(size);
954 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
955 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
956 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
957 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
958 END_CS;
959 }
960
961 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
962 {
963 CS_LOCALS(r300);
964
965 BEGIN_CS(size);
966 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
967 END_CS;
968 }
969
970 void r300_emit_vap_invariant_state(struct r300_context *r300,
971 unsigned size, void *state)
972 {
973 CS_LOCALS(r300);
974 WRITE_CS_TABLE(state, size);
975 }
976
977 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
978 {
979 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
980 struct r300_vertex_program_code* code = &vs->code;
981 struct r300_screen* r300screen = r300->screen;
982 unsigned instruction_count = code->length / 4;
983
984 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
985 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
986 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
987 unsigned temp_count = MAX2(code->num_temporaries, 1);
988
989 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
990 vtx_mem_size / output_count, 10);
991 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5);
992
993 CS_LOCALS(r300);
994
995 BEGIN_CS(size);
996
997 /* R300_VAP_PVS_CODE_CNTL_0
998 * R300_VAP_PVS_CONST_CNTL
999 * R300_VAP_PVS_CODE_CNTL_1
1000 * See the r5xx docs for instructions on how to use these. */
1001 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) |
1002 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
1003 R300_PVS_LAST_INST(instruction_count - 1));
1004 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, instruction_count - 1);
1005
1006 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
1007 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
1008 OUT_CS_TABLE(code->body.d, code->length);
1009
1010 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
1011 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
1012 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
1013 R300_PVS_VF_MAX_VTX_NUM(12) |
1014 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
1015
1016 /* Emit flow control instructions. */
1017 if (code->num_fc_ops) {
1018
1019 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
1020 if (r300screen->caps.is_r500) {
1021 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, code->num_fc_ops * 2);
1022 OUT_CS_TABLE(code->fc_op_addrs.r500, code->num_fc_ops * 2);
1023 } else {
1024 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, code->num_fc_ops);
1025 OUT_CS_TABLE(code->fc_op_addrs.r300, code->num_fc_ops);
1026 }
1027 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, code->num_fc_ops);
1028 OUT_CS_TABLE(code->fc_loop_index, code->num_fc_ops);
1029 }
1030
1031 END_CS;
1032 }
1033
1034 void r300_emit_vs_constants(struct r300_context* r300,
1035 unsigned size, void *state)
1036 {
1037 unsigned count =
1038 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
1039 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
1040 struct r300_vertex_shader *vs = (struct r300_vertex_shader*)r300->vs_state.state;
1041 unsigned i;
1042 int imm_first = vs->externals_count;
1043 int imm_end = vs->code.constants.Count;
1044 int imm_count = vs->immediates_count;
1045 CS_LOCALS(r300);
1046
1047 BEGIN_CS(size);
1048 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL,
1049 R300_PVS_CONST_BASE_OFFSET(buf->buffer_base) |
1050 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end - 1, 0)));
1051 if (vs->externals_count) {
1052 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1053 (r300->screen->caps.is_r500 ?
1054 R500_PVS_CONST_START : R300_PVS_CONST_START) + buf->buffer_base);
1055 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1056 if (buf->remap_table){
1057 for (i = 0; i < count; i++) {
1058 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
1059 OUT_CS_TABLE(data, 4);
1060 }
1061 } else {
1062 OUT_CS_TABLE(buf->ptr, count * 4);
1063 }
1064 }
1065
1066 /* Emit immediates. */
1067 if (imm_count) {
1068 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1069 (r300->screen->caps.is_r500 ?
1070 R500_PVS_CONST_START : R300_PVS_CONST_START) +
1071 buf->buffer_base + imm_first);
1072 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
1073 for (i = imm_first; i < imm_end; i++) {
1074 const float *data = vs->code.constants.Constants[i].u.Immediate;
1075 OUT_CS_TABLE(data, 4);
1076 }
1077 }
1078 END_CS;
1079 }
1080
1081 void r300_emit_viewport_state(struct r300_context* r300,
1082 unsigned size, void* state)
1083 {
1084 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1085 CS_LOCALS(r300);
1086
1087 BEGIN_CS(size);
1088 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1089 OUT_CS_TABLE(&viewport->xscale, 6);
1090 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1091 END_CS;
1092 }
1093
1094 static void r300_emit_hiz_line_clear(struct r300_context *r300, int start, uint16_t count, uint32_t val)
1095 {
1096 CS_LOCALS(r300);
1097 BEGIN_CS(4);
1098 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2);
1099 OUT_CS(start);
1100 OUT_CS(count);
1101 OUT_CS(val);
1102 END_CS;
1103 }
1104
1105 static void r300_emit_zmask_line_clear(struct r300_context *r300, int start, uint16_t count, uint32_t val)
1106 {
1107 CS_LOCALS(r300);
1108 BEGIN_CS(4);
1109 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2);
1110 OUT_CS(start);
1111 OUT_CS(count);
1112 OUT_CS(val);
1113 END_CS;
1114 }
1115
1116 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1117
1118 void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state)
1119 {
1120 struct pipe_framebuffer_state *fb =
1121 (struct pipe_framebuffer_state*)r300->fb_state.state;
1122 struct r300_hyperz_state *z =
1123 (struct r300_hyperz_state*)r300->hyperz_state.state;
1124 struct r300_screen* r300screen = r300->screen;
1125 uint32_t stride, offset = 0, height, offset_shift;
1126 struct r300_texture* tex;
1127 int i;
1128
1129 tex = r300_texture(fb->zsbuf->texture);
1130
1131 offset = tex->hiz_mem[fb->zsbuf->u.tex.level]->ofs;
1132 stride = tex->desc.stride_in_pixels[fb->zsbuf->u.tex.level];
1133
1134 /* convert from pixels to 4x4 blocks */
1135 stride = ALIGN_DIVUP(stride, 4);
1136
1137 stride = ALIGN_DIVUP(stride, r300screen->caps.num_frag_pipes);
1138 /* there are 4 blocks per dwords */
1139 stride = ALIGN_DIVUP(stride, 4);
1140
1141 height = ALIGN_DIVUP(fb->zsbuf->height, 4);
1142
1143 offset_shift = 2;
1144 offset_shift += (r300screen->caps.num_frag_pipes / 2);
1145
1146 for (i = 0; i < height; i++) {
1147 offset = i * stride;
1148 offset <<= offset_shift;
1149 r300_emit_hiz_line_clear(r300, offset, stride, 0xffffffff);
1150 }
1151 z->current_func = -1;
1152
1153 /* Mark the current zbuffer's hiz ram as in use. */
1154 tex->hiz_in_use[fb->zsbuf->u.tex.level] = TRUE;
1155 }
1156
1157 void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state)
1158 {
1159 struct pipe_framebuffer_state *fb =
1160 (struct pipe_framebuffer_state*)r300->fb_state.state;
1161 struct r300_screen* r300screen = r300->screen;
1162 uint32_t stride, offset = 0;
1163 struct r300_texture* tex;
1164 uint32_t i, height;
1165 int mult, offset_shift;
1166
1167 tex = r300_texture(fb->zsbuf->texture);
1168 stride = tex->desc.stride_in_pixels[fb->zsbuf->u.tex.level];
1169
1170 offset = tex->zmask_mem[fb->zsbuf->u.tex.level]->ofs;
1171
1172 if (r300->z_compression == RV350_Z_COMPRESS_88)
1173 mult = 8;
1174 else
1175 mult = 4;
1176
1177 height = ALIGN_DIVUP(fb->zsbuf->height, mult);
1178
1179 offset_shift = 4;
1180 offset_shift += (r300screen->caps.num_frag_pipes / 2);
1181 stride = ALIGN_DIVUP(stride, r300screen->caps.num_frag_pipes);
1182
1183 /* okay have width in pixels - divide by block width */
1184 stride = ALIGN_DIVUP(stride, mult);
1185 /* have width in blocks - divide by number of fragment pipes screen width */
1186 /* 16 blocks per dword */
1187 stride = ALIGN_DIVUP(stride, 16);
1188
1189 for (i = 0; i < height; i++) {
1190 offset = i * stride;
1191 offset <<= offset_shift;
1192 r300_emit_zmask_line_clear(r300, offset, stride, 0x0);//0xffffffff);
1193 }
1194
1195 /* Mark the current zbuffer's zmask as in use. */
1196 tex->zmask_in_use[fb->zsbuf->u.tex.level] = TRUE;
1197 }
1198
1199 void r300_emit_ztop_state(struct r300_context* r300,
1200 unsigned size, void* state)
1201 {
1202 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1203 CS_LOCALS(r300);
1204
1205 BEGIN_CS(size);
1206 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1207 END_CS;
1208 }
1209
1210 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1211 {
1212 CS_LOCALS(r300);
1213
1214 BEGIN_CS(size);
1215 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1216 END_CS;
1217 }
1218
1219 boolean r300_emit_buffer_validate(struct r300_context *r300,
1220 boolean do_validate_vertex_buffers,
1221 struct pipe_resource *index_buffer)
1222 {
1223 struct pipe_framebuffer_state* fb =
1224 (struct pipe_framebuffer_state*)r300->fb_state.state;
1225 struct r300_textures_state *texstate =
1226 (struct r300_textures_state*)r300->textures_state.state;
1227 struct r300_texture* tex;
1228 struct pipe_resource **vbuf = r300->valid_vertex_buffer;
1229 unsigned i;
1230
1231 /* Clean out BOs. */
1232 r300->rws->cs_reset_buffers(r300->cs);
1233
1234 /* Color buffers... */
1235 for (i = 0; i < fb->nr_cbufs; i++) {
1236 tex = r300_texture(fb->cbufs[i]->texture);
1237 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1238 r300->rws->cs_add_buffer(r300->cs, tex->cs_buffer, 0,
1239 r300_surface(fb->cbufs[i])->domain);
1240 }
1241 /* ...depth buffer... */
1242 if (fb->zsbuf) {
1243 tex = r300_texture(fb->zsbuf->texture);
1244 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1245 r300->rws->cs_add_buffer(r300->cs, tex->cs_buffer, 0,
1246 r300_surface(fb->zsbuf)->domain);
1247 }
1248 /* ...textures... */
1249 for (i = 0; i < texstate->count; i++) {
1250 if (!(texstate->tx_enable & (1 << i))) {
1251 continue;
1252 }
1253
1254 tex = r300_texture(texstate->sampler_views[i]->base.texture);
1255 r300->rws->cs_add_buffer(r300->cs, tex->cs_buffer, tex->domain, 0);
1256 }
1257 /* ...occlusion query buffer... */
1258 if (r300->query_current)
1259 r300->rws->cs_add_buffer(r300->cs, r300->query_current->cs_buffer,
1260 0, r300->query_current->domain);
1261 /* ...vertex buffer for SWTCL path... */
1262 if (r300->vbo)
1263 r300->rws->cs_add_buffer(r300->cs, r300_buffer(r300->vbo)->cs_buf,
1264 r300_buffer(r300->vbo)->domain, 0);
1265 /* ...vertex buffers for HWTCL path... */
1266 if (do_validate_vertex_buffers) {
1267 for (i = 0; i < r300->vertex_buffer_count; i++) {
1268 if (!vbuf[i])
1269 continue;
1270
1271 r300->rws->cs_add_buffer(r300->cs, r300_buffer(vbuf[i])->cs_buf,
1272 r300_buffer(vbuf[i])->domain, 0);
1273 }
1274 }
1275 /* ...and index buffer for HWTCL path. */
1276 if (index_buffer)
1277 r300->rws->cs_add_buffer(r300->cs, r300_buffer(index_buffer)->cs_buf,
1278 r300_buffer(index_buffer)->domain, 0);
1279
1280 if (!r300->rws->cs_validate(r300->cs)) {
1281 return FALSE;
1282 }
1283
1284 return TRUE;
1285 }
1286
1287 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1288 {
1289 struct r300_atom* atom;
1290 unsigned dwords = 0;
1291
1292 foreach_dirty_atom(r300, atom) {
1293 if (atom->dirty) {
1294 dwords += atom->size;
1295 }
1296 }
1297
1298 /* let's reserve some more, just in case */
1299 dwords += 32;
1300
1301 return dwords;
1302 }
1303
1304 unsigned r300_get_num_cs_end_dwords(struct r300_context *r300)
1305 {
1306 unsigned dwords = 0;
1307
1308 /* Emitted in flush. */
1309 dwords += 26; /* emit_query_end */
1310 dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
1311 if (r300->screen->caps.index_bias_supported)
1312 dwords += 2;
1313
1314 return dwords;
1315 }
1316
1317 /* Emit all dirty state. */
1318 void r300_emit_dirty_state(struct r300_context* r300)
1319 {
1320 struct r300_atom *atom;
1321
1322 foreach_dirty_atom(r300, atom) {
1323 if (atom->dirty) {
1324 atom->emit(r300, atom->size, atom->state);
1325 atom->dirty = FALSE;
1326 }
1327 }
1328
1329 r300->first_dirty = NULL;
1330 r300->last_dirty = NULL;
1331 r300->dirty_hw++;
1332 }