2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
30 #include "r300_context.h"
32 #include "r300_emit.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
38 void r300_emit_blend_state(struct r300_context
* r300
,
39 unsigned size
, void* state
)
41 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
42 struct pipe_framebuffer_state
* fb
=
43 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
47 OUT_CS_REG(R300_RB3D_ROPCNTL
, blend
->rop
);
48 OUT_CS_REG_SEQ(R300_RB3D_CBLEND
, 3);
50 OUT_CS(blend
->blend_control
);
51 OUT_CS(blend
->alpha_blend_control
);
52 OUT_CS(blend
->color_channel_mask
);
57 /* XXX also disable fastfill here once it's supported */
59 OUT_CS_REG(R300_RB3D_DITHER_CTL
, blend
->dither
);
63 void r300_emit_blend_color_state(struct r300_context
* r300
,
64 unsigned size
, void* state
)
66 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
69 if (r300
->screen
->caps
.is_r500
) {
71 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR
, 2);
72 OUT_CS(bc
->blend_color_red_alpha
);
73 OUT_CS(bc
->blend_color_green_blue
);
77 OUT_CS_REG(R300_RB3D_BLEND_COLOR
, bc
->blend_color
);
82 void r300_emit_clip_state(struct r300_context
* r300
,
83 unsigned size
, void* state
)
85 struct pipe_clip_state
* clip
= (struct pipe_clip_state
*)state
;
88 if (r300
->screen
->caps
.has_tcl
) {
90 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
91 (r300
->screen
->caps
.is_r500
?
92 R500_PVS_UCP_START
: R300_PVS_UCP_START
));
93 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, 6 * 4);
94 OUT_CS_TABLE(clip
->ucp
, 6 * 4);
95 OUT_CS_REG(R300_VAP_CLIP_CNTL
, ((1 << clip
->nr
) - 1) |
96 R300_PS_UCP_MODE_CLIP_AS_TRIFAN
);
100 OUT_CS_REG(R300_VAP_CLIP_CNTL
, R300_CLIP_DISABLE
);
105 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
107 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
108 struct pipe_framebuffer_state
* fb
=
109 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
110 struct pipe_stencil_ref stencil_ref
= r300
->stencil_ref
;
114 OUT_CS_REG(R300_FG_ALPHA_FUNC
, dsa
->alpha_function
);
115 OUT_CS_REG_SEQ(R300_ZB_CNTL
, 3);
118 OUT_CS(dsa
->z_buffer_control
);
119 OUT_CS(dsa
->z_stencil_control
);
125 OUT_CS(dsa
->stencil_ref_mask
| stencil_ref
.ref_value
[0]);
127 if (r300
->screen
->caps
.is_r500
) {
128 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF
, dsa
->stencil_ref_bf
| stencil_ref
.ref_value
[1]);
133 static const float * get_rc_constant_state(
134 struct r300_context
* r300
,
135 struct rc_constant
* constant
)
137 struct r300_viewport_state
* viewport
= r300
->viewport_state
.state
;
138 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
139 static float vec
[4] = { 0.0, 0.0, 0.0, 1.0 };
140 struct pipe_resource
*tex
;
142 assert(constant
->Type
== RC_CONSTANT_STATE
);
144 switch (constant
->u
.State
[0]) {
145 /* Factor for converting rectangle coords to
146 * normalized coords. Should only show up on non-r500. */
147 case RC_STATE_R300_TEXRECT_FACTOR
:
148 tex
= texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
;
149 vec
[0] = 1.0 / tex
->width0
;
150 vec
[1] = 1.0 / tex
->height0
;
153 case RC_STATE_R300_VIEWPORT_SCALE
:
154 vec
[0] = viewport
->xscale
;
155 vec
[1] = viewport
->yscale
;
156 vec
[2] = viewport
->zscale
;
159 case RC_STATE_R300_VIEWPORT_OFFSET
:
160 vec
[0] = viewport
->xoffset
;
161 vec
[1] = viewport
->yoffset
;
162 vec
[2] = viewport
->zoffset
;
166 fprintf(stderr
, "r300: Implementation error: "
167 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
170 /* This should either be (0, 0, 0, 1), which should be a relatively safe
171 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
176 /* Convert a normal single-precision float into the 7.16 format
177 * used by the R300 fragment shader.
179 static uint32_t pack_float24(float f
)
187 uint32_t float24
= 0;
194 mantissa
= frexpf(f
, &exponent
);
198 float24
|= (1 << 23);
199 mantissa
= mantissa
* -1.0;
201 /* Handle exponent, bias of 63 */
203 float24
|= (exponent
<< 16);
204 /* Kill 7 LSB of mantissa */
205 float24
|= (u
.u
& 0x7FFFFF) >> 7;
210 unsigned r300_get_fs_atom_size(struct r300_context
*r300
)
212 struct r300_fragment_shader
*fs
= r300_fs(r300
);
213 unsigned imm_count
= fs
->shader
->immediates_count
;
214 struct r300_fragment_program_code
*code
= &fs
->shader
->code
.code
.r300
;
217 code
->alu
.length
* 4 +
218 (code
->tex
.length
? (1 + code
->tex
.length
) : 0) +
219 (imm_count
? imm_count
* 5 : 0);
222 void r300_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
224 struct r300_fragment_shader
*fs
= r300_fs(r300
);
225 struct rX00_fragment_program_code
* generic_code
= &fs
->shader
->code
;
226 struct r300_fragment_program_code
* code
= &generic_code
->code
.r300
;
228 unsigned imm_count
= fs
->shader
->immediates_count
;
229 unsigned imm_first
= fs
->shader
->externals_count
;
230 unsigned imm_end
= generic_code
->constants
.Count
;
231 struct rc_constant
*constants
= generic_code
->constants
.Constants
;
235 OUT_CS_REG(R300_US_CONFIG
, code
->config
);
236 OUT_CS_REG(R300_US_PIXSIZE
, code
->pixsize
);
237 OUT_CS_REG(R300_US_CODE_OFFSET
, code
->code_offset
);
239 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0
, 4);
240 OUT_CS_TABLE(code
->code_addr
, 4);
242 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0
, code
->alu
.length
);
243 for (i
= 0; i
< code
->alu
.length
; i
++)
244 OUT_CS(code
->alu
.inst
[i
].rgb_inst
);
246 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0
, code
->alu
.length
);
247 for (i
= 0; i
< code
->alu
.length
; i
++)
248 OUT_CS(code
->alu
.inst
[i
].rgb_addr
);
250 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0
, code
->alu
.length
);
251 for (i
= 0; i
< code
->alu
.length
; i
++)
252 OUT_CS(code
->alu
.inst
[i
].alpha_inst
);
254 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0
, code
->alu
.length
);
255 for (i
= 0; i
< code
->alu
.length
; i
++)
256 OUT_CS(code
->alu
.inst
[i
].alpha_addr
);
258 if (code
->tex
.length
) {
259 OUT_CS_REG_SEQ(R300_US_TEX_INST_0
, code
->tex
.length
);
260 OUT_CS_TABLE(code
->tex
.inst
, code
->tex
.length
);
263 /* Emit immediates. */
265 for(i
= imm_first
; i
< imm_end
; ++i
) {
266 if (constants
[i
].Type
== RC_CONSTANT_IMMEDIATE
) {
267 const float *data
= constants
[i
].u
.Immediate
;
269 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
270 OUT_CS(pack_float24(data
[0]));
271 OUT_CS(pack_float24(data
[1]));
272 OUT_CS(pack_float24(data
[2]));
273 OUT_CS(pack_float24(data
[3]));
278 OUT_CS_REG(R300_FG_DEPTH_SRC
, fs
->shader
->fg_depth_src
);
279 OUT_CS_REG(R300_US_W_FMT
, fs
->shader
->us_out_w
);
283 void r300_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
285 struct r300_fragment_shader
*fs
= r300_fs(r300
);
286 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
287 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
288 unsigned i
, count
= fs
->shader
->externals_count
;
295 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, count
* 4);
296 for(i
= 0; i
< count
; ++i
) {
298 assert(constants
->Constants
[i
].Type
== RC_CONSTANT_EXTERNAL
);
299 data
= buf
->constants
[i
];
300 OUT_CS(pack_float24(data
[0]));
301 OUT_CS(pack_float24(data
[1]));
302 OUT_CS(pack_float24(data
[2]));
303 OUT_CS(pack_float24(data
[3]));
308 void r300_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
310 struct r300_fragment_shader
*fs
= r300_fs(r300
);
311 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
313 unsigned count
= fs
->shader
->rc_state_count
;
314 unsigned first
= fs
->shader
->externals_count
;
315 unsigned end
= constants
->Count
;
322 for(i
= first
; i
< end
; ++i
) {
323 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
325 get_rc_constant_state(r300
, &constants
->Constants
[i
]);
327 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
328 OUT_CS(pack_float24(data
[0]));
329 OUT_CS(pack_float24(data
[1]));
330 OUT_CS(pack_float24(data
[2]));
331 OUT_CS(pack_float24(data
[3]));
337 unsigned r500_get_fs_atom_size(struct r300_context
*r300
)
339 struct r300_fragment_shader
*fs
= r300_fs(r300
);
340 unsigned imm_count
= fs
->shader
->immediates_count
;
341 struct r500_fragment_program_code
*code
= &fs
->shader
->code
.code
.r500
;
344 ((code
->inst_end
+ 1) * 6) +
345 (imm_count
? imm_count
* 7 : 0);
348 void r500_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
350 struct r300_fragment_shader
*fs
= r300_fs(r300
);
351 struct rX00_fragment_program_code
* generic_code
= &fs
->shader
->code
;
352 struct r500_fragment_program_code
* code
= &generic_code
->code
.r500
;
354 unsigned imm_count
= fs
->shader
->immediates_count
;
355 unsigned imm_first
= fs
->shader
->externals_count
;
356 unsigned imm_end
= generic_code
->constants
.Count
;
357 struct rc_constant
*constants
= generic_code
->constants
.Constants
;
361 OUT_CS_REG(R500_US_CONFIG
, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
);
362 OUT_CS_REG(R500_US_PIXSIZE
, code
->max_temp_idx
);
363 OUT_CS_REG(R500_US_CODE_RANGE
,
364 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code
->inst_end
));
365 OUT_CS_REG(R500_US_CODE_OFFSET
, 0);
366 OUT_CS_REG(R500_US_CODE_ADDR
,
367 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code
->inst_end
));
369 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_INSTR
);
370 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, (code
->inst_end
+ 1) * 6);
371 for (i
= 0; i
<= code
->inst_end
; i
++) {
372 OUT_CS(code
->inst
[i
].inst0
);
373 OUT_CS(code
->inst
[i
].inst1
);
374 OUT_CS(code
->inst
[i
].inst2
);
375 OUT_CS(code
->inst
[i
].inst3
);
376 OUT_CS(code
->inst
[i
].inst4
);
377 OUT_CS(code
->inst
[i
].inst5
);
380 /* Emit immediates. */
382 for(i
= imm_first
; i
< imm_end
; ++i
) {
383 if (constants
[i
].Type
== RC_CONSTANT_IMMEDIATE
) {
384 const float *data
= constants
[i
].u
.Immediate
;
386 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
387 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
388 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
389 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
390 OUT_CS_TABLE(data
, 4);
395 OUT_CS_REG(R300_FG_DEPTH_SRC
, fs
->shader
->fg_depth_src
);
396 OUT_CS_REG(R300_US_W_FMT
, fs
->shader
->us_out_w
);
400 void r500_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
402 struct r300_fragment_shader
*fs
= r300_fs(r300
);
403 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
404 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
405 unsigned i
, count
= fs
->shader
->externals_count
;
412 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
413 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, count
* 4);
414 for(i
= 0; i
< count
; ++i
) {
415 assert(constants
->Constants
[i
].Type
== RC_CONSTANT_EXTERNAL
);
417 OUT_CS_TABLE(buf
->constants
, count
* 4);
421 void r500_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
423 struct r300_fragment_shader
*fs
= r300_fs(r300
);
424 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
426 unsigned count
= fs
->shader
->rc_state_count
;
427 unsigned first
= fs
->shader
->externals_count
;
428 unsigned end
= constants
->Count
;
435 for(i
= first
; i
< end
; ++i
) {
436 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
438 get_rc_constant_state(r300
, &constants
->Constants
[i
]);
440 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
441 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
442 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
443 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
444 OUT_CS_TABLE(data
, 4);
450 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
452 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
453 struct r300_texture
* tex
;
454 struct pipe_surface
* surf
;
460 /* Flush and free renderbuffer caches. */
461 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT
,
462 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS
|
463 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
464 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
,
465 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
466 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
468 /* Set the number of colorbuffers. */
469 if (fb
->nr_cbufs
> 1) {
470 if (r300
->screen
->caps
.is_r500
) {
471 OUT_CS_REG(R300_RB3D_CCTL
,
472 R300_RB3D_CCTL_NUM_MULTIWRITES(fb
->nr_cbufs
) |
473 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
);
475 OUT_CS_REG(R300_RB3D_CCTL
,
476 R300_RB3D_CCTL_NUM_MULTIWRITES(fb
->nr_cbufs
));
479 OUT_CS_REG(R300_RB3D_CCTL
, 0x0);
482 /* Set up colorbuffers. */
483 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
485 tex
= r300_texture(surf
->texture
);
486 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
488 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
489 OUT_CS_TEX_RELOC(tex
, surf
->offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
491 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
492 OUT_CS_TEX_RELOC(tex
, tex
->fb_state
.colorpitch
[surf
->level
],
493 0, RADEON_GEM_DOMAIN_VRAM
, 0);
495 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
), tex
->fb_state
.us_out_fmt
);
498 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
), R300_US_OUT_FMT_UNUSED
);
501 /* Set up a zbuffer. */
504 tex
= r300_texture(surf
->texture
);
505 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
507 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
508 OUT_CS_TEX_RELOC(tex
, surf
->offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
510 OUT_CS_REG(R300_ZB_FORMAT
, tex
->fb_state
.zb_format
);
512 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
513 OUT_CS_TEX_RELOC(tex
, tex
->fb_state
.depthpitch
[surf
->level
],
514 0, RADEON_GEM_DOMAIN_VRAM
, 0);
517 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
518 if (r300
->screen
->caps
.is_r500
) {
520 OUT_CS(((fb
->width
- 1) << R300_SCISSORS_X_SHIFT
) |
521 ((fb
->height
- 1) << R300_SCISSORS_Y_SHIFT
));
523 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
524 (1440 << R300_SCISSORS_Y_SHIFT
));
525 OUT_CS(((fb
->width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
526 ((fb
->height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
531 void r300_emit_query_start(struct r300_context
*r300
, unsigned size
, void*state
)
533 struct r300_query
*query
= r300
->query_current
;
540 if (r300
->screen
->caps
.family
== CHIP_FAMILY_RV530
) {
541 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
543 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
545 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
547 query
->begin_emitted
= TRUE
;
551 static void r300_emit_query_end_frag_pipes(struct r300_context
*r300
,
552 struct r300_query
*query
)
554 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
557 assert(caps
->num_frag_pipes
);
559 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
560 /* I'm not so sure I like this switch, but it's hard to be elegant
561 * when there's so many special cases...
563 * So here's the basic idea. For each pipe, enable writes to it only,
564 * then put out the relocation for ZPASS_ADDR, taking into account a
565 * 4-byte offset for each pipe. RV380 and older are special; they have
566 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
567 * so there's a chipset cap for that. */
568 switch (caps
->num_frag_pipes
) {
571 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
572 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
573 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 3),
574 0, RADEON_GEM_DOMAIN_GTT
, 0);
577 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
578 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
579 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 2),
580 0, RADEON_GEM_DOMAIN_GTT
, 0);
583 /* As mentioned above, accomodate RV380 and older. */
584 OUT_CS_REG(R300_SU_REG_DEST
,
585 1 << (caps
->high_second_pipe
? 3 : 1));
586 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
587 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 1),
588 0, RADEON_GEM_DOMAIN_GTT
, 0);
591 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
592 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
593 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 0),
594 0, RADEON_GEM_DOMAIN_GTT
, 0);
597 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
598 " pixel pipes!\n", caps
->num_frag_pipes
);
602 /* And, finally, reset it to normal... */
603 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
607 static void rv530_emit_query_end_single_z(struct r300_context
*r300
,
608 struct r300_query
*query
)
613 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
614 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
615 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
616 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
620 static void rv530_emit_query_end_double_z(struct r300_context
*r300
,
621 struct r300_query
*query
)
626 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
627 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
628 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
629 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
630 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
631 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
632 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
636 void r300_emit_query_end(struct r300_context
* r300
)
638 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
639 struct r300_query
*query
= r300
->query_current
;
644 if (query
->begin_emitted
== FALSE
)
647 if (caps
->family
== CHIP_FAMILY_RV530
) {
648 if (caps
->num_z_pipes
== 2)
649 rv530_emit_query_end_double_z(r300
, query
);
651 rv530_emit_query_end_single_z(r300
, query
);
653 r300_emit_query_end_frag_pipes(r300
, query
);
655 query
->begin_emitted
= FALSE
;
658 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
660 struct r300_rs_state
* rs
= (struct r300_rs_state
*)state
;
665 OUT_CS_REG(R300_VAP_CNTL_STATUS
, rs
->vap_control_status
);
667 OUT_CS_REG(R300_GB_AA_CONFIG
, rs
->antialiasing_config
);
669 OUT_CS_REG(R300_GA_POINT_SIZE
, rs
->point_size
);
670 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX
, 2);
671 OUT_CS(rs
->point_minmax
);
672 OUT_CS(rs
->line_control
);
674 if (rs
->polygon_offset_enable
) {
675 scale
= rs
->depth_scale
* 12;
676 offset
= rs
->depth_offset
;
678 switch (r300
->zbuffer_bpp
) {
687 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
694 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE
, 2);
695 OUT_CS(rs
->polygon_offset_enable
);
696 OUT_CS(rs
->cull_mode
);
697 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG
, rs
->line_stipple_config
);
698 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE
, rs
->line_stipple_value
);
699 OUT_CS_REG(R300_GA_POLY_MODE
, rs
->polygon_mode
);
700 OUT_CS_REG(R300_SC_CLIP_RULE
, rs
->clip_rule
);
701 OUT_CS_REG(R300_GB_ENABLE
, rs
->stuffing_enable
);
702 OUT_CS_REG_SEQ(R300_GA_POINT_S0
, 4);
703 OUT_CS_32F(rs
->point_texcoord_left
);
704 OUT_CS_32F(rs
->point_texcoord_bottom
);
705 OUT_CS_32F(rs
->point_texcoord_right
);
706 OUT_CS_32F(rs
->point_texcoord_top
);
710 void r300_emit_rs_block_state(struct r300_context
* r300
,
711 unsigned size
, void* state
)
713 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
715 /* It's the same for both INST and IP tables */
716 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
719 DBG(r300
, DBG_DRAW
, "r300: RS emit:\n");
722 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
723 OUT_CS(rs
->vap_vtx_state_cntl
);
724 OUT_CS(rs
->vap_vsm_vtx_assm
);
725 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
726 OUT_CS(rs
->vap_out_vtx_fmt
[0]);
727 OUT_CS(rs
->vap_out_vtx_fmt
[1]);
729 if (r300
->screen
->caps
.is_r500
) {
730 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
732 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
734 OUT_CS_TABLE(rs
->ip
, count
);
735 for (i
= 0; i
< count
; i
++) {
736 DBG(r300
, DBG_DRAW
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
739 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
741 OUT_CS(rs
->inst_count
);
743 if (r300
->screen
->caps
.is_r500
) {
744 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
746 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
748 OUT_CS_TABLE(rs
->inst
, count
);
749 for (i
= 0; i
< count
; i
++) {
750 DBG(r300
, DBG_DRAW
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
753 DBG(r300
, DBG_DRAW
, " : count: 0x%08x inst_count: 0x%08x\n",
754 rs
->count
, rs
->inst_count
);
759 void r300_emit_scissor_state(struct r300_context
* r300
,
760 unsigned size
, void* state
)
762 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
766 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
767 if (r300
->screen
->caps
.is_r500
) {
768 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
769 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
770 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
771 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
773 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
774 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
775 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
776 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
781 void r300_emit_textures_state(struct r300_context
*r300
,
782 unsigned size
, void *state
)
784 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
785 struct r300_texture_sampler_state
*texstate
;
790 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
792 for (i
= 0; i
< allstate
->count
; i
++) {
793 if ((1 << i
) & allstate
->tx_enable
) {
794 texstate
= &allstate
->regs
[i
];
796 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
797 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
798 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
799 texstate
->border_color
);
801 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
802 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
803 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
805 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
806 OUT_CS_TEX_RELOC(r300_texture(allstate
->sampler_views
[i
]->base
.texture
),
807 texstate
->format
.tile_config
,
808 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0, 0);
814 void r300_emit_aos(struct r300_context
* r300
, unsigned offset
, boolean indexed
)
816 struct pipe_vertex_buffer
*vb1
, *vb2
, *vbuf
= r300
->vertex_buffer
;
817 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
819 unsigned size1
, size2
, aos_count
= r300
->velems
->count
;
820 unsigned packet_size
= (aos_count
* 3 + 1) / 2;
823 for (i
= 0; i
< aos_count
; i
++) {
824 if ((vbuf
[velem
[i
].vertex_buffer_index
].buffer_offset
+ velem
[i
].src_offset
) % 4 != 0) {
825 /* XXX We must align the buffer. */
827 fprintf(stderr
, "r300: Unaligned vertex buffer offsets aren't supported, aborting..\n");
832 BEGIN_CS(2 + packet_size
+ aos_count
* 2);
833 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
834 OUT_CS(aos_count
| (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
836 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
837 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
838 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
839 size1
= util_format_get_blocksize(velem
[i
].src_format
);
840 size2
= util_format_get_blocksize(velem
[i
+1].src_format
);
842 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
843 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
844 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
845 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
849 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
850 size1
= util_format_get_blocksize(velem
[i
].src_format
);
852 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
853 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
856 for (i
= 0; i
< aos_count
; i
++) {
857 OUT_CS_BUF_RELOC_NO_OFFSET(vbuf
[velem
[i
].vertex_buffer_index
].buffer
,
858 RADEON_GEM_DOMAIN_GTT
, 0, 0);
863 void r300_emit_vertex_buffer(struct r300_context
* r300
)
867 DBG(r300
, DBG_DRAW
, "r300: Preparing vertex buffer %p for render, "
868 "vertex size %d\n", r300
->vbo
,
869 r300
->vertex_info
.size
);
870 /* Set the pointer to our vertex buffer. The emitted values are this:
871 * PACKET3 [3D_LOAD_VBPNTR]
873 * FORMAT [size | stride << 8]
874 * OFFSET [offset into BO]
875 * VBPNTR [relocated BO]
878 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
880 OUT_CS(r300
->vertex_info
.size
|
881 (r300
->vertex_info
.size
<< 8));
882 OUT_CS(r300
->vbo_offset
);
883 OUT_CS_BUF_RELOC(r300
->vbo
, 0, RADEON_GEM_DOMAIN_GTT
, 0, 0);
887 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
888 unsigned size
, void* state
)
890 struct r300_vertex_stream_state
*streams
=
891 (struct r300_vertex_stream_state
*)state
;
895 DBG(r300
, DBG_DRAW
, "r300: PSC emit:\n");
898 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
899 OUT_CS_TABLE(streams
->vap_prog_stream_cntl
, streams
->count
);
900 for (i
= 0; i
< streams
->count
; i
++) {
901 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl%d: 0x%08x\n", i
,
902 streams
->vap_prog_stream_cntl
[i
]);
904 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
905 OUT_CS_TABLE(streams
->vap_prog_stream_cntl_ext
, streams
->count
);
906 for (i
= 0; i
< streams
->count
; i
++) {
907 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
908 streams
->vap_prog_stream_cntl_ext
[i
]);
913 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
918 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
922 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
924 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
925 struct r300_vertex_program_code
* code
= &vs
->code
;
926 struct r300_screen
* r300screen
= r300
->screen
;
927 unsigned instruction_count
= code
->length
/ 4;
930 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
931 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
932 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
933 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
935 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
936 vtx_mem_size
/ output_count
, 10);
937 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 6);
939 unsigned imm_first
= vs
->externals_count
;
940 unsigned imm_end
= vs
->code
.constants
.Count
;
941 unsigned imm_count
= vs
->immediates_count
;
946 /* R300_VAP_PVS_CODE_CNTL_0
947 * R300_VAP_PVS_CONST_CNTL
948 * R300_VAP_PVS_CODE_CNTL_1
949 * See the r5xx docs for instructions on how to use these. */
950 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
951 OUT_CS(R300_PVS_FIRST_INST(0) |
952 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
953 R300_PVS_LAST_INST(instruction_count
- 1));
954 OUT_CS(R300_PVS_MAX_CONST_ADDR(code
->constants
.Count
- 1));
955 OUT_CS(instruction_count
- 1);
957 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
958 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
959 OUT_CS_TABLE(code
->body
.d
, code
->length
);
961 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
962 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
963 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
964 R300_PVS_VF_MAX_VTX_NUM(12) |
965 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
967 /* Emit immediates. */
969 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
970 (r300
->screen
->caps
.is_r500
?
971 R500_PVS_CONST_START
: R300_PVS_CONST_START
) +
973 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, imm_count
* 4);
974 for (i
= imm_first
; i
< imm_end
; i
++) {
975 const float *data
= vs
->code
.constants
.Constants
[i
].u
.Immediate
;
976 OUT_CS_TABLE(data
, 4);
982 void r300_emit_vs_constants(struct r300_context
* r300
,
983 unsigned size
, void *state
)
986 ((struct r300_vertex_shader
*)r300
->vs_state
.state
)->externals_count
;
987 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
994 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
995 (r300
->screen
->caps
.is_r500
?
996 R500_PVS_CONST_START
: R300_PVS_CONST_START
));
997 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, count
* 4);
998 OUT_CS_TABLE(buf
->constants
, count
* 4);
1002 void r300_emit_viewport_state(struct r300_context
* r300
,
1003 unsigned size
, void* state
)
1005 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
1009 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
1010 OUT_CS_32F(viewport
->xscale
);
1011 OUT_CS_32F(viewport
->xoffset
);
1012 OUT_CS_32F(viewport
->yscale
);
1013 OUT_CS_32F(viewport
->yoffset
);
1014 OUT_CS_32F(viewport
->zscale
);
1015 OUT_CS_32F(viewport
->zoffset
);
1016 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
1020 void r300_emit_ztop_state(struct r300_context
* r300
,
1021 unsigned size
, void* state
)
1023 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
1027 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
1031 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
1036 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
1040 void r300_emit_buffer_validate(struct r300_context
*r300
,
1041 boolean do_validate_vertex_buffers
,
1042 struct pipe_resource
*index_buffer
)
1044 struct pipe_framebuffer_state
* fb
=
1045 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
1046 struct r300_textures_state
*texstate
=
1047 (struct r300_textures_state
*)r300
->textures_state
.state
;
1048 struct r300_texture
* tex
;
1049 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
1050 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
1051 struct pipe_resource
*pbuf
;
1053 boolean invalid
= FALSE
;
1055 /* upload buffers first */
1056 if (r300
->any_user_vbs
) {
1057 r300_upload_user_buffers(r300
);
1058 r300
->any_user_vbs
= false;
1061 /* Clean out BOs. */
1062 r300
->rws
->reset_bos(r300
->rws
);
1065 /* Color buffers... */
1066 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1067 tex
= r300_texture(fb
->cbufs
[i
]->texture
);
1068 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
1069 if (!r300_add_texture(r300
->rws
, tex
,
1070 0, RADEON_GEM_DOMAIN_VRAM
)) {
1071 r300
->context
.flush(&r300
->context
, 0, NULL
);
1075 /* ...depth buffer... */
1077 tex
= r300_texture(fb
->zsbuf
->texture
);
1078 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
1079 if (!r300_add_texture(r300
->rws
, tex
,
1080 0, RADEON_GEM_DOMAIN_VRAM
)) {
1081 r300
->context
.flush(&r300
->context
, 0, NULL
);
1085 /* ...textures... */
1086 for (i
= 0; i
< texstate
->count
; i
++) {
1087 if (!(texstate
->tx_enable
& (1 << i
))) {
1091 tex
= r300_texture(texstate
->sampler_views
[i
]->base
.texture
);
1092 if (!r300_add_texture(r300
->rws
, tex
,
1093 RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
, 0)) {
1094 r300
->context
.flush(&r300
->context
, 0, NULL
);
1098 /* ...occlusion query buffer... */
1099 if (r300
->query_start
.dirty
||
1100 (r300
->query_current
&& r300
->query_current
->begin_emitted
)) {
1101 if (!r300_add_buffer(r300
->rws
, r300
->oqbo
,
1102 0, RADEON_GEM_DOMAIN_GTT
)) {
1103 r300
->context
.flush(&r300
->context
, 0, NULL
);
1107 /* ...vertex buffer for SWTCL path... */
1109 if (!r300_add_buffer(r300
->rws
, r300
->vbo
,
1110 RADEON_GEM_DOMAIN_GTT
, 0)) {
1111 r300
->context
.flush(&r300
->context
, 0, NULL
);
1115 /* ...vertex buffers for HWTCL path... */
1116 if (do_validate_vertex_buffers
) {
1117 for (i
= 0; i
< r300
->velems
->count
; i
++) {
1118 pbuf
= vbuf
[velem
[i
].vertex_buffer_index
].buffer
;
1120 if (!r300_add_buffer(r300
->rws
, pbuf
,
1121 RADEON_GEM_DOMAIN_GTT
, 0)) {
1122 r300
->context
.flush(&r300
->context
, 0, NULL
);
1127 /* ...and index buffer for HWTCL path. */
1129 if (!r300_add_buffer(r300
->rws
, index_buffer
,
1130 RADEON_GEM_DOMAIN_GTT
, 0)) {
1131 r300
->context
.flush(&r300
->context
, 0, NULL
);
1135 if (!r300
->rws
->validate(r300
->rws
)) {
1136 r300
->context
.flush(&r300
->context
, 0, NULL
);
1139 fprintf(stderr
, "r300: Stuck in validation loop, gonna quit now.\n");
1147 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
1149 struct r300_atom
* atom
;
1150 unsigned dwords
= 0;
1152 foreach(atom
, &r300
->atom_list
) {
1154 dwords
+= atom
->size
;
1158 /* let's reserve some more, just in case */
1164 /* Emit all dirty state. */
1165 void r300_emit_dirty_state(struct r300_context
* r300
)
1167 struct r300_screen
* r300screen
= r300
->screen
;
1168 struct r300_atom
* atom
;
1170 foreach(atom
, &r300
->atom_list
) {
1172 atom
->emit(r300
, atom
->size
, atom
->state
);
1173 if (SCREEN_DBG_ON(r300
->screen
, DBG_STATS
)) {
1176 atom
->dirty
= FALSE
;
1180 /* Emit the VBO for SWTCL. */
1181 if (!r300screen
->caps
.has_tcl
) {
1182 r300_emit_vertex_buffer(r300
);