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r300g: add generating texture coordinates for point sprites (WIP)
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
36 #include "r300_state_inlines.h"
37 #include "r300_vs.h"
38
39 void r300_emit_blend_state(struct r300_context* r300,
40 unsigned size, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 struct pipe_framebuffer_state* fb =
44 (struct pipe_framebuffer_state*)r300->fb_state.state;
45 CS_LOCALS(r300);
46
47 BEGIN_CS(size);
48 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
49 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
50 if (fb->nr_cbufs) {
51 OUT_CS(blend->blend_control);
52 OUT_CS(blend->alpha_blend_control);
53 OUT_CS(blend->color_channel_mask);
54 } else {
55 OUT_CS(0);
56 OUT_CS(0);
57 OUT_CS(0);
58 /* XXX also disable fastfill here once it's supported */
59 }
60 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
61 END_CS;
62 }
63
64 void r300_emit_blend_color_state(struct r300_context* r300,
65 unsigned size, void* state)
66 {
67 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
68 struct r300_screen* r300screen = r300_screen(r300->context.screen);
69 CS_LOCALS(r300);
70
71 if (r300screen->caps->is_r500) {
72 BEGIN_CS(size);
73 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
74 OUT_CS(bc->blend_color_red_alpha);
75 OUT_CS(bc->blend_color_green_blue);
76 END_CS;
77 } else {
78 BEGIN_CS(size);
79 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
80 END_CS;
81 }
82 }
83
84 void r300_emit_clip_state(struct r300_context* r300,
85 unsigned size, void* state)
86 {
87 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
88 int i;
89 struct r300_screen* r300screen = r300_screen(r300->context.screen);
90 CS_LOCALS(r300);
91
92 if (r300screen->caps->has_tcl) {
93 BEGIN_CS(size);
94 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
95 (r300screen->caps->is_r500 ?
96 R500_PVS_UCP_START : R300_PVS_UCP_START));
97 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
98 for (i = 0; i < 6; i++) {
99 OUT_CS_32F(clip->ucp[i][0]);
100 OUT_CS_32F(clip->ucp[i][1]);
101 OUT_CS_32F(clip->ucp[i][2]);
102 OUT_CS_32F(clip->ucp[i][3]);
103 }
104 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
105 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
106 END_CS;
107 } else {
108 BEGIN_CS(size);
109 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
110 END_CS;
111 }
112
113 }
114
115 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
116 {
117 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
118 struct r300_screen* r300screen = r300_screen(r300->context.screen);
119 struct pipe_framebuffer_state* fb =
120 (struct pipe_framebuffer_state*)r300->fb_state.state;
121 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
122 CS_LOCALS(r300);
123
124 BEGIN_CS(size);
125 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
126 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
127
128 if (fb->zsbuf) {
129 OUT_CS(dsa->z_buffer_control);
130 OUT_CS(dsa->z_stencil_control);
131 } else {
132 OUT_CS(0);
133 OUT_CS(0);
134 }
135
136 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
137
138 if (r300screen->caps->is_r500) {
139 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
140 }
141 END_CS;
142 }
143
144 static const float * get_shader_constant(
145 struct r300_context * r300,
146 struct rc_constant * constant,
147 struct r300_constant_buffer * externals)
148 {
149 struct r300_viewport_state* viewport =
150 (struct r300_viewport_state*)r300->viewport_state.state;
151 struct r300_textures_state* texstate =
152 (struct r300_textures_state*)r300->textures_state.state;
153 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
154 struct pipe_texture *tex;
155
156 switch(constant->Type) {
157 case RC_CONSTANT_EXTERNAL:
158 return externals->constants[constant->u.External];
159
160 case RC_CONSTANT_IMMEDIATE:
161 return constant->u.Immediate;
162
163 case RC_CONSTANT_STATE:
164 switch (constant->u.State[0]) {
165 /* Factor for converting rectangle coords to
166 * normalized coords. Should only show up on non-r500. */
167 case RC_STATE_R300_TEXRECT_FACTOR:
168 tex = texstate->fragment_sampler_views[constant->u.State[1]]->texture;
169 vec[0] = 1.0 / tex->width0;
170 vec[1] = 1.0 / tex->height0;
171 break;
172
173 /* Texture compare-fail value. Shouldn't ever show up, but if
174 * it does, we'll be ready. */
175 case RC_STATE_SHADOW_AMBIENT:
176 vec[3] = 0;
177 break;
178
179 case RC_STATE_R300_VIEWPORT_SCALE:
180 vec[0] = viewport->xscale;
181 vec[1] = viewport->yscale;
182 vec[2] = viewport->zscale;
183 break;
184
185 case RC_STATE_R300_VIEWPORT_OFFSET:
186 vec[0] = viewport->xoffset;
187 vec[1] = viewport->yoffset;
188 vec[2] = viewport->zoffset;
189 break;
190
191 default:
192 debug_printf("r300: Implementation error: "
193 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
194 }
195 break;
196
197 default:
198 debug_printf("r300: Implementation error: "
199 "Unhandled constant type %d\n", constant->Type);
200 }
201
202 /* This should either be (0, 0, 0, 1), which should be a relatively safe
203 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
204 * state factors. */
205 return vec;
206 }
207
208 /* Convert a normal single-precision float into the 7.16 format
209 * used by the R300 fragment shader.
210 */
211 static uint32_t pack_float24(float f)
212 {
213 union {
214 float fl;
215 uint32_t u;
216 } u;
217 float mantissa;
218 int exponent;
219 uint32_t float24 = 0;
220
221 if (f == 0.0)
222 return 0;
223
224 u.fl = f;
225
226 mantissa = frexpf(f, &exponent);
227
228 /* Handle -ve */
229 if (mantissa < 0) {
230 float24 |= (1 << 23);
231 mantissa = mantissa * -1.0;
232 }
233 /* Handle exponent, bias of 63 */
234 exponent += 62;
235 float24 |= (exponent << 16);
236 /* Kill 7 LSB of mantissa */
237 float24 |= (u.u & 0x7FFFFF) >> 7;
238
239 return float24;
240 }
241
242 void r300_emit_fragment_program_code(struct r300_context* r300,
243 struct rX00_fragment_program_code* generic_code)
244 {
245 struct r300_fragment_program_code * code = &generic_code->code.r300;
246 int i;
247 CS_LOCALS(r300);
248
249 BEGIN_CS(15 +
250 code->alu.length * 4 +
251 (code->tex.length ? (1 + code->tex.length) : 0));
252
253 OUT_CS_REG(R300_US_CONFIG, code->config);
254 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
255 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
256
257 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
258 for(i = 0; i < 4; ++i)
259 OUT_CS(code->code_addr[i]);
260
261 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
262 for (i = 0; i < code->alu.length; i++)
263 OUT_CS(code->alu.inst[i].rgb_inst);
264
265 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
266 for (i = 0; i < code->alu.length; i++)
267 OUT_CS(code->alu.inst[i].rgb_addr);
268
269 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
270 for (i = 0; i < code->alu.length; i++)
271 OUT_CS(code->alu.inst[i].alpha_inst);
272
273 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
274 for (i = 0; i < code->alu.length; i++)
275 OUT_CS(code->alu.inst[i].alpha_addr);
276
277 if (code->tex.length) {
278 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
279 for(i = 0; i < code->tex.length; ++i)
280 OUT_CS(code->tex.inst[i]);
281 }
282
283 END_CS;
284 }
285
286 void r300_emit_fs_constant_buffer(struct r300_context* r300,
287 struct rc_constant_list* constants)
288 {
289 int i;
290 CS_LOCALS(r300);
291
292 if (constants->Count == 0)
293 return;
294
295 BEGIN_CS(constants->Count * 4 + 1);
296 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
297 for(i = 0; i < constants->Count; ++i) {
298 const float * data = get_shader_constant(r300,
299 &constants->Constants[i],
300 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
301 OUT_CS(pack_float24(data[0]));
302 OUT_CS(pack_float24(data[1]));
303 OUT_CS(pack_float24(data[2]));
304 OUT_CS(pack_float24(data[3]));
305 }
306 END_CS;
307 }
308
309 static void r300_emit_fragment_depth_config(struct r300_context* r300,
310 struct r300_fragment_shader* fs)
311 {
312 CS_LOCALS(r300);
313
314 BEGIN_CS(4);
315 if (r300_fragment_shader_writes_depth(fs)) {
316 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
317 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
318 } else {
319 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
320 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
321 }
322 END_CS;
323 }
324
325 void r500_emit_fragment_program_code(struct r300_context* r300,
326 struct rX00_fragment_program_code* generic_code)
327 {
328 struct r500_fragment_program_code * code = &generic_code->code.r500;
329 int i;
330 CS_LOCALS(r300);
331
332 BEGIN_CS(13 +
333 ((code->inst_end + 1) * 6));
334 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
335 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
336 OUT_CS_REG(R500_US_CODE_RANGE,
337 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
338 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
339 OUT_CS_REG(R500_US_CODE_ADDR,
340 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
341
342 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
343 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
344 for (i = 0; i <= code->inst_end; i++) {
345 OUT_CS(code->inst[i].inst0);
346 OUT_CS(code->inst[i].inst1);
347 OUT_CS(code->inst[i].inst2);
348 OUT_CS(code->inst[i].inst3);
349 OUT_CS(code->inst[i].inst4);
350 OUT_CS(code->inst[i].inst5);
351 }
352
353 END_CS;
354 }
355
356 void r500_emit_fs_constant_buffer(struct r300_context* r300,
357 struct rc_constant_list* constants)
358 {
359 int i;
360 CS_LOCALS(r300);
361
362 if (constants->Count == 0)
363 return;
364
365 BEGIN_CS(constants->Count * 4 + 3);
366 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
367 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
368 for (i = 0; i < constants->Count; i++) {
369 const float * data = get_shader_constant(r300,
370 &constants->Constants[i],
371 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
372 OUT_CS_32F(data[0]);
373 OUT_CS_32F(data[1]);
374 OUT_CS_32F(data[2]);
375 OUT_CS_32F(data[3]);
376 }
377 END_CS;
378 }
379
380 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
381 {
382 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
383 struct r300_screen* r300screen = r300_screen(r300->context.screen);
384 struct r300_texture* tex;
385 struct pipe_surface* surf;
386 int i;
387 CS_LOCALS(r300);
388
389 BEGIN_CS(size);
390
391 /* Flush and free renderbuffer caches. */
392 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
393 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
394 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
395 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
396 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
397 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
398
399 /* Set the number of colorbuffers. */
400 if (fb->nr_cbufs > 1) {
401 if (r300screen->caps->is_r500) {
402 OUT_CS_REG(R300_RB3D_CCTL,
403 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
404 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
405 } else {
406 OUT_CS_REG(R300_RB3D_CCTL,
407 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
408 }
409 } else {
410 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
411 }
412
413 /* Set up colorbuffers. */
414 for (i = 0; i < fb->nr_cbufs; i++) {
415 surf = fb->cbufs[i];
416 tex = (struct r300_texture*)surf->texture;
417 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
418
419 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
420 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
421
422 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
423 OUT_CS_TEX_RELOC(tex, tex->fb_state.colorpitch[surf->level],
424 0, RADEON_GEM_DOMAIN_VRAM, 0);
425
426 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
427 }
428 for (; i < 4; i++) {
429 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
430 }
431
432 /* Set up a zbuffer. */
433 if (fb->zsbuf) {
434 surf = fb->zsbuf;
435 tex = (struct r300_texture*)surf->texture;
436 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
437
438 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
439 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
440
441 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
442
443 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
444 OUT_CS_TEX_RELOC(tex, tex->fb_state.depthpitch[surf->level],
445 0, RADEON_GEM_DOMAIN_VRAM, 0);
446 }
447
448 OUT_CS_REG(R300_GA_POINT_MINMAX,
449 (MAX2(fb->width, fb->height) * 6) << R300_GA_POINT_MINMAX_MAX_SHIFT);
450 END_CS;
451 }
452
453 void r300_emit_query_start(struct r300_context *r300)
454 {
455 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
456 struct r300_query *query = r300->query_current;
457 CS_LOCALS(r300);
458
459 if (!query)
460 return;
461
462 BEGIN_CS(4);
463 if (caps->family == CHIP_FAMILY_RV530) {
464 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
465 } else {
466 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
467 }
468 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
469 END_CS;
470 query->begin_emitted = TRUE;
471 }
472
473
474 static void r300_emit_query_finish(struct r300_context *r300,
475 struct r300_query *query)
476 {
477 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
478 CS_LOCALS(r300);
479
480 assert(caps->num_frag_pipes);
481
482 BEGIN_CS(6 * caps->num_frag_pipes + 2);
483 /* I'm not so sure I like this switch, but it's hard to be elegant
484 * when there's so many special cases...
485 *
486 * So here's the basic idea. For each pipe, enable writes to it only,
487 * then put out the relocation for ZPASS_ADDR, taking into account a
488 * 4-byte offset for each pipe. RV380 and older are special; they have
489 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
490 * so there's a chipset cap for that. */
491 switch (caps->num_frag_pipes) {
492 case 4:
493 /* pipe 3 only */
494 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
495 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
496 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
497 0, RADEON_GEM_DOMAIN_GTT, 0);
498 case 3:
499 /* pipe 2 only */
500 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
501 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
502 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
503 0, RADEON_GEM_DOMAIN_GTT, 0);
504 case 2:
505 /* pipe 1 only */
506 /* As mentioned above, accomodate RV380 and older. */
507 OUT_CS_REG(R300_SU_REG_DEST,
508 1 << (caps->high_second_pipe ? 3 : 1));
509 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
510 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
511 0, RADEON_GEM_DOMAIN_GTT, 0);
512 case 1:
513 /* pipe 0 only */
514 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
515 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
516 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
517 0, RADEON_GEM_DOMAIN_GTT, 0);
518 break;
519 default:
520 debug_printf("r300: Implementation error: Chipset reports %d"
521 " pixel pipes!\n", caps->num_frag_pipes);
522 assert(0);
523 }
524
525 /* And, finally, reset it to normal... */
526 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
527 END_CS;
528 }
529
530 static void rv530_emit_query_single(struct r300_context *r300,
531 struct r300_query *query)
532 {
533 CS_LOCALS(r300);
534
535 BEGIN_CS(8);
536 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
537 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
538 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
539 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
540 END_CS;
541 }
542
543 static void rv530_emit_query_double(struct r300_context *r300,
544 struct r300_query *query)
545 {
546 CS_LOCALS(r300);
547
548 BEGIN_CS(14);
549 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
550 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
551 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
552 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
553 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
554 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
555 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
556 END_CS;
557 }
558
559 void r300_emit_query_end(struct r300_context* r300)
560 {
561 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
562 struct r300_query *query = r300->query_current;
563
564 if (!query)
565 return;
566
567 if (query->begin_emitted == FALSE)
568 return;
569
570 if (caps->family == CHIP_FAMILY_RV530) {
571 if (caps->num_z_pipes == 2)
572 rv530_emit_query_double(r300, query);
573 else
574 rv530_emit_query_single(r300, query);
575 } else
576 r300_emit_query_finish(r300, query);
577 }
578
579 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
580 {
581 struct r300_rs_state* rs = (struct r300_rs_state*)state;
582 float scale, offset;
583 CS_LOCALS(r300);
584
585 BEGIN_CS(size);
586 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
587
588 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
589
590 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
591 OUT_CS_REG(R300_GA_LINE_CNTL, rs->line_control);
592
593 if (rs->polygon_offset_enable) {
594 scale = rs->depth_scale * 12;
595 offset = rs->depth_offset;
596
597 switch (r300->zbuffer_bpp) {
598 case 16:
599 offset *= 4;
600 break;
601 case 24:
602 offset *= 2;
603 break;
604 }
605
606 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
607 OUT_CS_32F(scale);
608 OUT_CS_32F(offset);
609 OUT_CS_32F(scale);
610 OUT_CS_32F(offset);
611 }
612
613 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
614 OUT_CS(rs->polygon_offset_enable);
615 OUT_CS(rs->cull_mode);
616 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
617 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
618 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
619 OUT_CS_REG(R300_GB_ENABLE, rs->stuffing_enable);
620 OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4);
621 OUT_CS_32F(rs->point_texcoord_left);
622 OUT_CS_32F(rs->point_texcoord_bottom);
623 OUT_CS_32F(rs->point_texcoord_right);
624 OUT_CS_32F(rs->point_texcoord_top);
625 END_CS;
626 }
627
628 void r300_emit_rs_block_state(struct r300_context* r300,
629 unsigned size, void* state)
630 {
631 struct r300_rs_block* rs = (struct r300_rs_block*)state;
632 unsigned i;
633 struct r300_screen* r300screen = r300_screen(r300->context.screen);
634 /* It's the same for both INST and IP tables */
635 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
636 CS_LOCALS(r300);
637
638 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
639
640 BEGIN_CS(size);
641 if (r300screen->caps->is_r500) {
642 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
643 } else {
644 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
645 }
646 for (i = 0; i < count; i++) {
647 OUT_CS(rs->ip[i]);
648 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
649 }
650
651 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
652 OUT_CS(rs->count);
653 OUT_CS(rs->inst_count);
654
655 if (r300screen->caps->is_r500) {
656 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
657 } else {
658 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
659 }
660 for (i = 0; i < count; i++) {
661 OUT_CS(rs->inst[i]);
662 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
663 }
664
665 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
666 rs->count, rs->inst_count);
667
668 END_CS;
669 }
670
671 void r300_emit_scissor_state(struct r300_context* r300,
672 unsigned size, void* state)
673 {
674 unsigned minx, miny, maxx, maxy;
675 uint32_t top_left, bottom_right;
676 struct r300_screen* r300screen = r300_screen(r300->context.screen);
677 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
678 struct pipe_framebuffer_state* fb =
679 (struct pipe_framebuffer_state*)r300->fb_state.state;
680 CS_LOCALS(r300);
681
682 minx = miny = 0;
683 maxx = fb->width;
684 maxy = fb->height;
685
686 if (r300->scissor_enabled) {
687 minx = MAX2(minx, scissor->minx);
688 miny = MAX2(miny, scissor->miny);
689 maxx = MIN2(maxx, scissor->maxx);
690 maxy = MIN2(maxy, scissor->maxy);
691 }
692
693 /* Special case for zero-area scissor.
694 *
695 * We can't allow the variables maxx and maxy to be zero because they are
696 * subtracted from later in the code, which would cause emitting ~0 and
697 * making the kernel checker angry.
698 *
699 * Let's consider we change maxx and maxy to 1, which is effectively
700 * a one-pixel area. We must then change minx and miny to a number which is
701 * greater than 1 to get the zero area back. */
702 if (!maxx || !maxy) {
703 minx = 2;
704 miny = 2;
705 maxx = 1;
706 maxy = 1;
707 }
708
709 if (r300screen->caps->is_r500) {
710 top_left =
711 (minx << R300_SCISSORS_X_SHIFT) |
712 (miny << R300_SCISSORS_Y_SHIFT);
713 bottom_right =
714 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
715 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
716 } else {
717 /* Offset of 1440 in non-R500 chipsets. */
718 top_left =
719 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
720 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
721 bottom_right =
722 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
723 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
724 }
725
726 BEGIN_CS(size);
727 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
728 OUT_CS(top_left);
729 OUT_CS(bottom_right);
730 END_CS;
731 }
732
733 void r300_emit_textures_state(struct r300_context *r300,
734 unsigned size, void *state)
735 {
736 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
737 struct r300_texture_sampler_state *texstate;
738 unsigned i;
739 CS_LOCALS(r300);
740
741 BEGIN_CS(size);
742 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
743
744 for (i = 0; i < allstate->count; i++) {
745 if ((1 << i) & allstate->tx_enable) {
746 texstate = &allstate->regs[i];
747
748 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter[0]);
749 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter[1]);
750 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
751 texstate->border_color);
752
753 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format[0]);
754 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format[1]);
755 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format[2]);
756
757 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
758 OUT_CS_TEX_RELOC((struct r300_texture *)allstate->fragment_sampler_views[i]->texture,
759 texstate->tile_config,
760 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
761 }
762 }
763 END_CS;
764 }
765
766 void r300_emit_aos(struct r300_context* r300, unsigned offset)
767 {
768 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
769 struct pipe_vertex_element *velem = r300->velems->velem;
770 int i;
771 unsigned size1, size2, aos_count = r300->velems->count;
772 unsigned packet_size = (aos_count * 3 + 1) / 2;
773 CS_LOCALS(r300);
774
775 BEGIN_CS(2 + packet_size + aos_count * 2);
776 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
777 OUT_CS(aos_count);
778
779 for (i = 0; i < aos_count - 1; i += 2) {
780 vb1 = &vbuf[velem[i].vertex_buffer_index];
781 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
782 size1 = util_format_get_blocksize(velem[i].src_format);
783 size2 = util_format_get_blocksize(velem[i+1].src_format);
784
785 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
786 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
787 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
788 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
789 }
790
791 if (aos_count & 1) {
792 vb1 = &vbuf[velem[i].vertex_buffer_index];
793 size1 = util_format_get_blocksize(velem[i].src_format);
794
795 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
796 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
797 }
798
799 for (i = 0; i < aos_count; i++) {
800 OUT_CS_BUF_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
801 RADEON_GEM_DOMAIN_GTT, 0, 0);
802 }
803 END_CS;
804 }
805
806 void r300_emit_vertex_buffer(struct r300_context* r300)
807 {
808 CS_LOCALS(r300);
809
810 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
811 "vertex size %d\n", r300->vbo,
812 r300->vertex_info.size);
813 /* Set the pointer to our vertex buffer. The emitted values are this:
814 * PACKET3 [3D_LOAD_VBPNTR]
815 * COUNT [1]
816 * FORMAT [size | stride << 8]
817 * OFFSET [offset into BO]
818 * VBPNTR [relocated BO]
819 */
820 BEGIN_CS(7);
821 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
822 OUT_CS(1);
823 OUT_CS(r300->vertex_info.size |
824 (r300->vertex_info.size << 8));
825 OUT_CS(r300->vbo_offset);
826 OUT_CS_BUF_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
827 END_CS;
828 }
829
830 void r300_emit_vertex_stream_state(struct r300_context* r300,
831 unsigned size, void* state)
832 {
833 struct r300_vertex_stream_state *streams =
834 (struct r300_vertex_stream_state*)state;
835 unsigned i;
836 CS_LOCALS(r300);
837
838 DBG(r300, DBG_DRAW, "r300: PSC emit:\n");
839
840 BEGIN_CS(size);
841 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
842 for (i = 0; i < streams->count; i++) {
843 OUT_CS(streams->vap_prog_stream_cntl[i]);
844 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
845 streams->vap_prog_stream_cntl[i]);
846 }
847 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
848 for (i = 0; i < streams->count; i++) {
849 OUT_CS(streams->vap_prog_stream_cntl_ext[i]);
850 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
851 streams->vap_prog_stream_cntl_ext[i]);
852 }
853 END_CS;
854 }
855
856 void r300_emit_vap_output_state(struct r300_context* r300,
857 unsigned size, void* state)
858 {
859 struct r300_vap_output_state *vap_out_state =
860 (struct r300_vap_output_state*)state;
861 CS_LOCALS(r300);
862
863 DBG(r300, DBG_DRAW, "r300: VAP emit:\n");
864
865 BEGIN_CS(size);
866 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
867 OUT_CS(vap_out_state->vap_vtx_state_cntl);
868 OUT_CS(vap_out_state->vap_vsm_vtx_assm);
869 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
870 OUT_CS(vap_out_state->vap_out_vtx_fmt[0]);
871 OUT_CS(vap_out_state->vap_out_vtx_fmt[1]);
872 END_CS;
873 }
874
875 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
876 {
877 CS_LOCALS(r300);
878
879 BEGIN_CS(size);
880 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
881 END_CS;
882 }
883
884 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
885 {
886 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
887 struct r300_vertex_program_code* code = &vs->code;
888 struct r300_screen* r300screen = r300_screen(r300->context.screen);
889 unsigned instruction_count = code->length / 4;
890 unsigned i;
891
892 unsigned vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
893 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
894 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
895 unsigned temp_count = MAX2(code->num_temporaries, 1);
896
897 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
898 vtx_mem_size / output_count, 10);
899 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
900
901 CS_LOCALS(r300);
902
903 if (!r300screen->caps->has_tcl) {
904 debug_printf("r300: Implementation error: emit_vs_state called,"
905 " but has_tcl is FALSE!\n");
906 return;
907 }
908
909 BEGIN_CS(size);
910 /* R300_VAP_PVS_CODE_CNTL_0
911 * R300_VAP_PVS_CONST_CNTL
912 * R300_VAP_PVS_CODE_CNTL_1
913 * See the r5xx docs for instructions on how to use these. */
914 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
915 OUT_CS(R300_PVS_FIRST_INST(0) |
916 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
917 R300_PVS_LAST_INST(instruction_count - 1));
918 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
919 OUT_CS(instruction_count - 1);
920
921 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
922 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
923 for (i = 0; i < code->length; i++) {
924 OUT_CS(code->body.d[i]);
925 }
926
927 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
928 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
929 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
930 R300_PVS_VF_MAX_VTX_NUM(12) |
931 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
932 END_CS;
933 }
934
935 void r300_emit_vs_constant_buffer(struct r300_context* r300,
936 struct rc_constant_list* constants)
937 {
938 int i;
939 struct r300_screen* r300screen = r300_screen(r300->context.screen);
940 CS_LOCALS(r300);
941
942 if (!r300screen->caps->has_tcl) {
943 debug_printf("r300: Implementation error: emit_vs_constant_buffer called,"
944 " but has_tcl is FALSE!\n");
945 return;
946 }
947
948 if (constants->Count == 0)
949 return;
950
951 BEGIN_CS(constants->Count * 4 + 3);
952 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
953 (r300screen->caps->is_r500 ?
954 R500_PVS_CONST_START : R300_PVS_CONST_START));
955 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
956 for (i = 0; i < constants->Count; i++) {
957 const float * data = get_shader_constant(r300,
958 &constants->Constants[i],
959 &r300->shader_constants[PIPE_SHADER_VERTEX]);
960 OUT_CS_32F(data[0]);
961 OUT_CS_32F(data[1]);
962 OUT_CS_32F(data[2]);
963 OUT_CS_32F(data[3]);
964 }
965 END_CS;
966 }
967
968 void r300_emit_viewport_state(struct r300_context* r300,
969 unsigned size, void* state)
970 {
971 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
972 CS_LOCALS(r300);
973
974 BEGIN_CS(size);
975 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
976 OUT_CS_32F(viewport->xscale);
977 OUT_CS_32F(viewport->xoffset);
978 OUT_CS_32F(viewport->yscale);
979 OUT_CS_32F(viewport->yoffset);
980 OUT_CS_32F(viewport->zscale);
981 OUT_CS_32F(viewport->zoffset);
982 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
983 END_CS;
984 }
985
986 void r300_emit_ztop_state(struct r300_context* r300,
987 unsigned size, void* state)
988 {
989 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
990 CS_LOCALS(r300);
991
992 BEGIN_CS(size);
993 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
994 END_CS;
995 }
996
997 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
998 {
999 CS_LOCALS(r300);
1000
1001 BEGIN_CS(size);
1002 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1003 END_CS;
1004 }
1005
1006 void r300_emit_buffer_validate(struct r300_context *r300,
1007 boolean do_validate_vertex_buffers,
1008 struct pipe_buffer *index_buffer)
1009 {
1010 struct pipe_framebuffer_state* fb =
1011 (struct pipe_framebuffer_state*)r300->fb_state.state;
1012 struct r300_textures_state *texstate =
1013 (struct r300_textures_state*)r300->textures_state.state;
1014 struct r300_texture* tex;
1015 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1016 struct pipe_vertex_element *velem = r300->velems->velem;
1017 struct pipe_buffer *pbuf;
1018 unsigned i;
1019 boolean invalid = FALSE;
1020
1021 /* upload buffers first */
1022 if (r300->any_user_vbs) {
1023 r300_upload_user_buffers(r300);
1024 r300->any_user_vbs = false;
1025 }
1026
1027 /* Clean out BOs. */
1028 r300->rws->reset_bos(r300->rws);
1029
1030 validate:
1031 /* Color buffers... */
1032 for (i = 0; i < fb->nr_cbufs; i++) {
1033 tex = (struct r300_texture*)fb->cbufs[i]->texture;
1034 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1035 if (!r300_add_texture(r300->rws, tex,
1036 0, RADEON_GEM_DOMAIN_VRAM)) {
1037 r300->context.flush(&r300->context, 0, NULL);
1038 goto validate;
1039 }
1040 }
1041 /* ...depth buffer... */
1042 if (fb->zsbuf) {
1043 tex = (struct r300_texture*)fb->zsbuf->texture;
1044 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1045 if (!r300_add_texture(r300->rws, tex,
1046 0, RADEON_GEM_DOMAIN_VRAM)) {
1047 r300->context.flush(&r300->context, 0, NULL);
1048 goto validate;
1049 }
1050 }
1051 /* ...textures... */
1052 for (i = 0; i < texstate->count; i++) {
1053 tex = (struct r300_texture*)texstate->fragment_sampler_views[i]->texture;
1054 if (!tex || !texstate->sampler_states[i])
1055 continue;
1056 if (!r300_add_texture(r300->rws, tex,
1057 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1058 r300->context.flush(&r300->context, 0, NULL);
1059 goto validate;
1060 }
1061 }
1062 /* ...occlusion query buffer... */
1063 if (r300->dirty_state & R300_NEW_QUERY) {
1064 if (!r300_add_buffer(r300->rws, r300->oqbo,
1065 0, RADEON_GEM_DOMAIN_GTT)) {
1066 r300->context.flush(&r300->context, 0, NULL);
1067 goto validate;
1068 }
1069 }
1070 /* ...vertex buffer for SWTCL path... */
1071 if (r300->vbo) {
1072 if (!r300_add_buffer(r300->rws, r300->vbo,
1073 RADEON_GEM_DOMAIN_GTT, 0)) {
1074 r300->context.flush(&r300->context, 0, NULL);
1075 goto validate;
1076 }
1077 }
1078 /* ...vertex buffers for HWTCL path... */
1079 if (do_validate_vertex_buffers) {
1080 for (i = 0; i < r300->velems->count; i++) {
1081 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1082
1083 if (!r300_add_buffer(r300->rws, pbuf,
1084 RADEON_GEM_DOMAIN_GTT, 0)) {
1085 r300->context.flush(&r300->context, 0, NULL);
1086 goto validate;
1087 }
1088 }
1089 }
1090 /* ...and index buffer for HWTCL path. */
1091 if (index_buffer) {
1092 if (!r300_add_buffer(r300->rws, index_buffer,
1093 RADEON_GEM_DOMAIN_GTT, 0)) {
1094 r300->context.flush(&r300->context, 0, NULL);
1095 goto validate;
1096 }
1097 }
1098 if (!r300->rws->validate(r300->rws)) {
1099 r300->context.flush(&r300->context, 0, NULL);
1100 if (invalid) {
1101 /* Well, hell. */
1102 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1103 exit(1);
1104 }
1105 invalid = TRUE;
1106 goto validate;
1107 }
1108 }
1109
1110 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1111 {
1112 struct r300_atom* atom;
1113 unsigned dwords = 0;
1114
1115 foreach(atom, &r300->atom_list) {
1116 if (atom->dirty || atom->always_dirty) {
1117 dwords += atom->size;
1118 }
1119 }
1120
1121 /* XXX This is the compensation for the non-atomized states. */
1122 dwords += 1024;
1123
1124 return dwords;
1125 }
1126
1127 /* Emit all dirty state. */
1128 void r300_emit_dirty_state(struct r300_context* r300)
1129 {
1130 struct r300_screen* r300screen = r300_screen(r300->context.screen);
1131 struct r300_atom* atom;
1132
1133 if (r300->dirty_state & R300_NEW_QUERY) {
1134 r300_emit_query_start(r300);
1135 r300->dirty_state &= ~R300_NEW_QUERY;
1136 }
1137
1138 foreach(atom, &r300->atom_list) {
1139 if (atom->dirty || atom->always_dirty) {
1140 atom->emit(r300, atom->size, atom->state);
1141 atom->dirty = FALSE;
1142 }
1143 }
1144
1145 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1146 r300_emit_fragment_depth_config(r300, r300->fs);
1147 if (r300screen->caps->is_r500) {
1148 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1149 } else {
1150 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1151 }
1152 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1153 }
1154
1155 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1156 if (r300screen->caps->is_r500) {
1157 r500_emit_fs_constant_buffer(r300,
1158 &r300->fs->shader->code.constants);
1159 } else {
1160 r300_emit_fs_constant_buffer(r300,
1161 &r300->fs->shader->code.constants);
1162 }
1163 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1164 }
1165
1166 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1167 struct r300_vertex_shader* vs = r300->vs_state.state;
1168 r300_emit_vs_constant_buffer(r300, &vs->code.constants);
1169 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1170 }
1171
1172 /* XXX
1173 assert(r300->dirty_state == 0);
1174 */
1175
1176 /* Emit the VBO for SWTCL. */
1177 if (!r300screen->caps->has_tcl) {
1178 r300_emit_vertex_buffer(r300);
1179 }
1180
1181 r300->dirty_hw++;
1182 }