projects / mesa.git / blob
? search:


596ec21bc0e72087002bd709e1e82e50baa20fd0
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28
29 #include "r300_context.h"
30 #include "r300_cs.h"
31 #include "r300_emit.h"
32 #include "r300_fs.h"
33 #include "r300_screen.h"
34 #include "r300_state_derived.h"
35 #include "r300_state_inlines.h"
36 #include "r300_texture.h"
37 #include "r300_vs.h"
38
39 void r300_emit_blend_state(struct r300_context* r300,
40 struct r300_blend_state* blend)
41 {
42 CS_LOCALS(r300);
43 BEGIN_CS(8);
44 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
45 if (r300->framebuffer_state.nr_cbufs) {
46 OUT_CS(blend->blend_control);
47 OUT_CS(blend->alpha_blend_control);
48 OUT_CS(blend->color_channel_mask);
49 } else {
50 OUT_CS(0);
51 OUT_CS(0);
52 OUT_CS(0);
53 /* XXX also disable fastfill here once it's supported */
54 }
55 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
56 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
57 END_CS;
58 }
59
60 void r300_emit_blend_color_state(struct r300_context* r300,
61 struct r300_blend_color_state* bc)
62 {
63 struct r300_screen* r300screen = r300_screen(r300->context.screen);
64 CS_LOCALS(r300);
65
66 if (r300screen->caps->is_r500) {
67 BEGIN_CS(3);
68 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
69 OUT_CS(bc->blend_color_red_alpha);
70 OUT_CS(bc->blend_color_green_blue);
71 END_CS;
72 } else {
73 BEGIN_CS(2);
74 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
75 END_CS;
76 }
77 }
78
79 void r300_emit_clip_state(struct r300_context* r300,
80 struct pipe_clip_state* clip)
81 {
82 int i;
83 struct r300_screen* r300screen = r300_screen(r300->context.screen);
84 CS_LOCALS(r300);
85
86 if (r300screen->caps->has_tcl) {
87 BEGIN_CS(5 + (6 * 4));
88 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
89 (r300screen->caps->is_r500 ?
90 R500_PVS_UCP_START : R300_PVS_UCP_START));
91 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
92 for (i = 0; i < 6; i++) {
93 OUT_CS_32F(clip->ucp[i][0]);
94 OUT_CS_32F(clip->ucp[i][1]);
95 OUT_CS_32F(clip->ucp[i][2]);
96 OUT_CS_32F(clip->ucp[i][3]);
97 }
98 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
99 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
100 END_CS;
101 } else {
102 BEGIN_CS(2);
103 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
104 END_CS;
105 }
106
107 }
108
109 void r300_emit_dsa_state(struct r300_context* r300,
110 struct r300_dsa_state* dsa)
111 {
112 struct r300_screen* r300screen = r300_screen(r300->context.screen);
113 CS_LOCALS(r300);
114
115 BEGIN_CS(r300screen->caps->is_r500 ? 10 : 8);
116 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
117
118 /* not needed since we use the 8bit alpha ref */
119 /*if (r300screen->caps->is_r500) {
120 OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
121 }*/
122
123 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
124 OUT_CS(dsa->z_buffer_control);
125 OUT_CS(dsa->z_stencil_control);
126 OUT_CS(dsa->stencil_ref_mask);
127 OUT_CS_REG(R300_ZB_ZTOP, r300->ztop_state.z_buffer_top);
128
129 /* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
130 if (r300screen->caps->is_r500) {
131 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
132 }
133 END_CS;
134 }
135
136 static const float * get_shader_constant(
137 struct r300_context * r300,
138 struct rc_constant * constant,
139 struct r300_constant_buffer * externals)
140 {
141 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
142 struct pipe_texture *tex;
143
144 switch(constant->Type) {
145 case RC_CONSTANT_EXTERNAL:
146 return externals->constants[constant->u.External];
147
148 case RC_CONSTANT_IMMEDIATE:
149 return constant->u.Immediate;
150
151 case RC_CONSTANT_STATE:
152 switch (constant->u.State[0]) {
153 /* Factor for converting rectangle coords to
154 * normalized coords. Should only show up on non-r500. */
155 case RC_STATE_R300_TEXRECT_FACTOR:
156 tex = &r300->textures[constant->u.State[1]]->tex;
157 vec[0] = 1.0 / tex->width0;
158 vec[1] = 1.0 / tex->height0;
159 break;
160
161 /* Texture compare-fail value. */
162 /* XXX Since Gallium doesn't support GL_ARB_shadow_ambient,
163 * this is always (0,0,0,0). */
164 case RC_STATE_SHADOW_AMBIENT:
165 vec[3] = 0;
166 break;
167
168 default:
169 debug_printf("r300: Implementation error: "
170 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
171 }
172 break;
173
174 default:
175 debug_printf("r300: Implementation error: "
176 "Unhandled constant type %d\n", constant->Type);
177 }
178
179 /* This should either be (0, 0, 0, 1), which should be a relatively safe
180 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
181 * state factors. */
182 return vec;
183 }
184
185 /* Convert a normal single-precision float into the 7.16 format
186 * used by the R300 fragment shader.
187 */
188 static uint32_t pack_float24(float f)
189 {
190 union {
191 float fl;
192 uint32_t u;
193 } u;
194 float mantissa;
195 int exponent;
196 uint32_t float24 = 0;
197
198 if (f == 0.0)
199 return 0;
200
201 u.fl = f;
202
203 mantissa = frexpf(f, &exponent);
204
205 /* Handle -ve */
206 if (mantissa < 0) {
207 float24 |= (1 << 23);
208 mantissa = mantissa * -1.0;
209 }
210 /* Handle exponent, bias of 63 */
211 exponent += 62;
212 float24 |= (exponent << 16);
213 /* Kill 7 LSB of mantissa */
214 float24 |= (u.u & 0x7FFFFF) >> 7;
215
216 return float24;
217 }
218
219 void r300_emit_fragment_program_code(struct r300_context* r300,
220 struct rX00_fragment_program_code* generic_code)
221 {
222 struct r300_fragment_program_code * code = &generic_code->code.r300;
223 int i;
224 CS_LOCALS(r300);
225
226 BEGIN_CS(15 +
227 code->alu.length * 4 +
228 (code->tex.length ? (1 + code->tex.length) : 0));
229
230 OUT_CS_REG(R300_US_CONFIG, code->config);
231 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
232 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
233
234 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
235 for(i = 0; i < 4; ++i)
236 OUT_CS(code->code_addr[i]);
237
238 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
239 for (i = 0; i < code->alu.length; i++)
240 OUT_CS(code->alu.inst[i].rgb_inst);
241
242 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
243 for (i = 0; i < code->alu.length; i++)
244 OUT_CS(code->alu.inst[i].rgb_addr);
245
246 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
247 for (i = 0; i < code->alu.length; i++)
248 OUT_CS(code->alu.inst[i].alpha_inst);
249
250 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
251 for (i = 0; i < code->alu.length; i++)
252 OUT_CS(code->alu.inst[i].alpha_addr);
253
254 if (code->tex.length) {
255 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
256 for(i = 0; i < code->tex.length; ++i)
257 OUT_CS(code->tex.inst[i]);
258 }
259
260 END_CS;
261 }
262
263 void r300_emit_fs_constant_buffer(struct r300_context* r300,
264 struct rc_constant_list* constants)
265 {
266 int i;
267 CS_LOCALS(r300);
268
269 if (constants->Count == 0)
270 return;
271
272 BEGIN_CS(constants->Count * 4 + 1);
273 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
274 for(i = 0; i < constants->Count; ++i) {
275 const float * data = get_shader_constant(r300,
276 &constants->Constants[i],
277 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
278 OUT_CS(pack_float24(data[0]));
279 OUT_CS(pack_float24(data[1]));
280 OUT_CS(pack_float24(data[2]));
281 OUT_CS(pack_float24(data[3]));
282 }
283 END_CS;
284 }
285
286 static void r300_emit_fragment_depth_config(struct r300_context* r300,
287 struct r300_fragment_shader* fs)
288 {
289 CS_LOCALS(r300);
290
291 BEGIN_CS(4);
292 if (r300_fragment_shader_writes_depth(fs)) {
293 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
294 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
295 } else {
296 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
297 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
298 }
299 END_CS;
300 }
301
302 void r500_emit_fragment_program_code(struct r300_context* r300,
303 struct rX00_fragment_program_code* generic_code)
304 {
305 struct r500_fragment_program_code * code = &generic_code->code.r500;
306 int i;
307 CS_LOCALS(r300);
308
309 BEGIN_CS(13 +
310 ((code->inst_end + 1) * 6));
311 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
312 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
313 OUT_CS_REG(R500_US_CODE_RANGE,
314 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
315 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
316 OUT_CS_REG(R500_US_CODE_ADDR,
317 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
318
319 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
320 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
321 for (i = 0; i <= code->inst_end; i++) {
322 OUT_CS(code->inst[i].inst0);
323 OUT_CS(code->inst[i].inst1);
324 OUT_CS(code->inst[i].inst2);
325 OUT_CS(code->inst[i].inst3);
326 OUT_CS(code->inst[i].inst4);
327 OUT_CS(code->inst[i].inst5);
328 }
329
330 END_CS;
331 }
332
333 void r500_emit_fs_constant_buffer(struct r300_context* r300,
334 struct rc_constant_list* constants)
335 {
336 int i;
337 CS_LOCALS(r300);
338
339 if (constants->Count == 0)
340 return;
341
342 BEGIN_CS(constants->Count * 4 + 3);
343 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
344 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
345 for (i = 0; i < constants->Count; i++) {
346 const float * data = get_shader_constant(r300,
347 &constants->Constants[i],
348 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
349 OUT_CS_32F(data[0]);
350 OUT_CS_32F(data[1]);
351 OUT_CS_32F(data[2]);
352 OUT_CS_32F(data[3]);
353 }
354 END_CS;
355 }
356
357 void r300_emit_fb_state(struct r300_context* r300,
358 struct pipe_framebuffer_state* fb)
359 {
360 struct r300_texture* tex;
361 struct pipe_surface* surf;
362 int i;
363 CS_LOCALS(r300);
364
365 /* Shouldn't fail unless there is a bug in the state tracker. */
366 assert(fb->nr_cbufs <= 4);
367
368 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
369 (fb->zsbuf ? 10 : 0) + 6);
370
371 /* Flush and free renderbuffer caches. */
372 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
373 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
374 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
375 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
376 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
377 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
378
379 /* Set the number of colorbuffers. */
380 OUT_CS_REG(R300_RB3D_CCTL, R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
381
382 /* Set up colorbuffers. */
383 for (i = 0; i < fb->nr_cbufs; i++) {
384 surf = fb->cbufs[i];
385 tex = (struct r300_texture*)surf->texture;
386 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
387
388 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
389 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
390
391 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
392 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
393 r300_translate_colorformat(tex->tex.format), 0,
394 RADEON_GEM_DOMAIN_VRAM, 0);
395
396 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
397 r300_translate_out_fmt(surf->format));
398 }
399
400 /* Disable unused colorbuffers. */
401 for (; i < 4; i++) {
402 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
403 }
404
405 /* Set up a zbuffer. */
406 if (fb->zsbuf) {
407 surf = fb->zsbuf;
408 tex = (struct r300_texture*)surf->texture;
409 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
410
411 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
412 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
413
414 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
415
416 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
417 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level], 0,
418 RADEON_GEM_DOMAIN_VRAM, 0);
419 }
420
421 END_CS;
422 }
423
424 static void r300_emit_query_start(struct r300_context *r300)
425 {
426 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
427 struct r300_query *query = r300->query_current;
428 CS_LOCALS(r300);
429
430 if (!query)
431 return;
432
433 BEGIN_CS(4);
434 if (caps->family == CHIP_FAMILY_RV530) {
435 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
436 } else {
437 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
438 }
439 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
440 END_CS;
441 query->begin_emitted = TRUE;
442 }
443
444
445 static void r300_emit_query_finish(struct r300_context *r300,
446 struct r300_query *query)
447 {
448 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
449 CS_LOCALS(r300);
450
451 assert(caps->num_frag_pipes);
452
453 BEGIN_CS(6 * caps->num_frag_pipes + 2);
454 /* I'm not so sure I like this switch, but it's hard to be elegant
455 * when there's so many special cases...
456 *
457 * So here's the basic idea. For each pipe, enable writes to it only,
458 * then put out the relocation for ZPASS_ADDR, taking into account a
459 * 4-byte offset for each pipe. RV380 and older are special; they have
460 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
461 * so there's a chipset cap for that. */
462 switch (caps->num_frag_pipes) {
463 case 4:
464 /* pipe 3 only */
465 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
466 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
467 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
468 0, RADEON_GEM_DOMAIN_GTT, 0);
469 case 3:
470 /* pipe 2 only */
471 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
472 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
473 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
474 0, RADEON_GEM_DOMAIN_GTT, 0);
475 case 2:
476 /* pipe 1 only */
477 /* As mentioned above, accomodate RV380 and older. */
478 OUT_CS_REG(R300_SU_REG_DEST,
479 1 << (caps->high_second_pipe ? 3 : 1));
480 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
481 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
482 0, RADEON_GEM_DOMAIN_GTT, 0);
483 case 1:
484 /* pipe 0 only */
485 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
486 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
487 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
488 0, RADEON_GEM_DOMAIN_GTT, 0);
489 break;
490 default:
491 debug_printf("r300: Implementation error: Chipset reports %d"
492 " pixel pipes!\n", caps->num_frag_pipes);
493 assert(0);
494 }
495
496 /* And, finally, reset it to normal... */
497 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
498 END_CS;
499 }
500
501 static void rv530_emit_query_single(struct r300_context *r300,
502 struct r300_query *query)
503 {
504 CS_LOCALS(r300);
505
506 BEGIN_CS(8);
507 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
508 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
509 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
510 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
511 END_CS;
512 }
513
514 static void rv530_emit_query_double(struct r300_context *r300,
515 struct r300_query *query)
516 {
517 CS_LOCALS(r300);
518
519 BEGIN_CS(14);
520 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
521 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
522 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
523 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
524 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
525 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
526 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
527 END_CS;
528 }
529
530 void r300_emit_query_end(struct r300_context* r300)
531 {
532 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
533 struct r300_query *query = r300->query_current;
534
535 if (!query)
536 return;
537
538 if (query->begin_emitted == FALSE)
539 return;
540
541 if (caps->family == CHIP_FAMILY_RV530) {
542 if (caps->num_z_pipes == 2)
543 rv530_emit_query_double(r300, query);
544 else
545 rv530_emit_query_single(r300, query);
546 } else
547 r300_emit_query_finish(r300, query);
548 }
549
550 void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs)
551 {
552 CS_LOCALS(r300);
553
554 BEGIN_CS(22);
555 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
556 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
557 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
558 OUT_CS(rs->point_minmax);
559 OUT_CS(rs->line_control);
560 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6);
561 OUT_CS(rs->depth_scale_front);
562 OUT_CS(rs->depth_offset_front);
563 OUT_CS(rs->depth_scale_back);
564 OUT_CS(rs->depth_offset_back);
565 OUT_CS(rs->polygon_offset_enable);
566 OUT_CS(rs->cull_mode);
567 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
568 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
569 OUT_CS_REG(R300_GA_COLOR_CONTROL, rs->color_control);
570 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
571 END_CS;
572 }
573
574 void r300_emit_rs_block_state(struct r300_context* r300,
575 struct r300_rs_block* rs)
576 {
577 int i;
578 struct r300_screen* r300screen = r300_screen(r300->context.screen);
579 CS_LOCALS(r300);
580
581 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
582
583 BEGIN_CS(21);
584 if (r300screen->caps->is_r500) {
585 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
586 } else {
587 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
588 }
589 for (i = 0; i < 8; i++) {
590 OUT_CS(rs->ip[i]);
591 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
592 }
593
594 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
595 OUT_CS(rs->count);
596 OUT_CS(rs->inst_count);
597
598 if (r300screen->caps->is_r500) {
599 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
600 } else {
601 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
602 }
603 for (i = 0; i < 8; i++) {
604 OUT_CS(rs->inst[i]);
605 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
606 }
607
608 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
609 rs->count, rs->inst_count);
610
611 END_CS;
612 }
613
614 static void r300_emit_scissor_regs(struct r300_context* r300,
615 struct r300_scissor_regs* scissor)
616 {
617 CS_LOCALS(r300);
618
619 BEGIN_CS(3);
620 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
621 OUT_CS(scissor->top_left);
622 OUT_CS(scissor->bottom_right);
623 END_CS;
624 }
625
626 void r300_emit_scissor_state(struct r300_context* r300,
627 struct r300_scissor_state* scissor)
628 {
629 if (r300->rs_state->rs.scissor) {
630 r300_emit_scissor_regs(r300, &scissor->scissor);
631 } else {
632 r300_emit_scissor_regs(r300, &scissor->framebuffer);
633 }
634 }
635
636 void r300_emit_texture(struct r300_context* r300,
637 struct r300_sampler_state* sampler,
638 struct r300_texture* tex,
639 unsigned offset)
640 {
641 uint32_t filter0 = sampler->filter0;
642 uint32_t format0 = tex->state.format0;
643 unsigned min_level, max_level;
644 CS_LOCALS(r300);
645
646 /* to emulate 1D textures through 2D ones correctly */
647 if (tex->tex.target == PIPE_TEXTURE_1D) {
648 filter0 &= ~R300_TX_WRAP_T_MASK;
649 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
650 }
651
652 /* determine min/max levels */
653 /* the MAX_MIP level is the largest (finest) one */
654 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
655 min_level = MIN2(sampler->min_lod, max_level);
656 format0 |= R300_TX_NUM_LEVELS(max_level);
657 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
658
659 BEGIN_CS(16);
660 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
661 (offset << 28));
662 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
663 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
664
665 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
666 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
667 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
668 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
669 OUT_CS_RELOC(tex->buffer, 0,
670 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
671 END_CS;
672 }
673
674 static boolean r300_validate_aos(struct r300_context *r300)
675 {
676 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
677 struct pipe_vertex_element *velem = r300->vertex_element;
678 int i;
679
680 /* Check if formats and strides are aligned to the size of DWORD. */
681 for (i = 0; i < r300->vertex_element_count; i++) {
682 if (vbuf[velem[i].vertex_buffer_index].stride % 4 != 0 ||
683 util_format_get_blocksize(velem[i].src_format) % 4 != 0) {
684 return FALSE;
685 }
686 }
687 return TRUE;
688 }
689
690 void r300_emit_aos(struct r300_context* r300, unsigned offset)
691 {
692 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
693 struct pipe_vertex_element *velem = r300->vertex_element;
694 int i;
695 unsigned size1, size2, aos_count = r300->vertex_element_count;
696 unsigned packet_size = (aos_count * 3 + 1) / 2;
697 CS_LOCALS(r300);
698
699 /* XXX Move this checking to a more approriate place. */
700 if (!r300_validate_aos(r300)) {
701 /* XXX We should fallback using Draw. */
702 assert(0);
703 }
704
705 BEGIN_CS(2 + packet_size + aos_count * 2);
706 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
707 OUT_CS(aos_count);
708
709 for (i = 0; i < aos_count - 1; i += 2) {
710 vb1 = &vbuf[velem[i].vertex_buffer_index];
711 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
712 size1 = util_format_get_blocksize(velem[i].src_format);
713 size2 = util_format_get_blocksize(velem[i+1].src_format);
714
715 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
716 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
717 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
718 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
719 }
720
721 if (aos_count & 1) {
722 vb1 = &vbuf[velem[i].vertex_buffer_index];
723 size1 = util_format_get_blocksize(velem[i].src_format);
724
725 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
726 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
727 }
728
729 for (i = 0; i < aos_count; i++) {
730 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
731 RADEON_GEM_DOMAIN_GTT, 0, 0);
732 }
733 END_CS;
734 }
735
736 #if 0
737 void r300_emit_draw_packet(struct r300_context* r300)
738 {
739 CS_LOCALS(r300);
740
741 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
742 "vertex size %d\n", r300->vbo,
743 r300->vertex_info->vinfo.size);
744 /* Set the pointer to our vertex buffer. The emitted values are this:
745 * PACKET3 [3D_LOAD_VBPNTR]
746 * COUNT [1]
747 * FORMAT [size | stride << 8]
748 * OFFSET [offset into BO]
749 * VBPNTR [relocated BO]
750 */
751 BEGIN_CS(7);
752 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
753 OUT_CS(1);
754 OUT_CS(r300->vertex_info->vinfo.size |
755 (r300->vertex_info->vinfo.size << 8));
756 OUT_CS(r300->vbo_offset);
757 OUT_CS_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
758 END_CS;
759 }
760 #endif
761
762 void r300_emit_vertex_format_state(struct r300_context* r300)
763 {
764 int i;
765 CS_LOCALS(r300);
766
767 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
768
769 BEGIN_CS(26);
770 OUT_CS_REG(R300_VAP_VTX_SIZE, r300->vertex_info->vinfo.size);
771
772 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
773 OUT_CS(r300->vertex_info->vinfo.hwfmt[0]);
774 OUT_CS(r300->vertex_info->vinfo.hwfmt[1]);
775 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
776 OUT_CS(r300->vertex_info->vinfo.hwfmt[2]);
777 OUT_CS(r300->vertex_info->vinfo.hwfmt[3]);
778 for (i = 0; i < 4; i++) {
779 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
780 r300->vertex_info->vinfo.hwfmt[i]);
781 }
782
783 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
784 for (i = 0; i < 8; i++) {
785 OUT_CS(r300->vertex_info->vap_prog_stream_cntl[i]);
786 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
787 r300->vertex_info->vap_prog_stream_cntl[i]);
788 }
789 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
790 for (i = 0; i < 8; i++) {
791 OUT_CS(r300->vertex_info->vap_prog_stream_cntl_ext[i]);
792 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
793 r300->vertex_info->vap_prog_stream_cntl_ext[i]);
794 }
795 END_CS;
796 }
797
798
799 void r300_emit_vertex_program_code(struct r300_context* r300,
800 struct r300_vertex_program_code* code)
801 {
802 int i;
803 struct r300_screen* r300screen = r300_screen(r300->context.screen);
804 unsigned instruction_count = code->length / 4;
805
806 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
807 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
808 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
809 int temp_count = MAX2(code->num_temporaries, 1);
810 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
811 vtx_mem_size / output_count, 10);
812 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
813
814 CS_LOCALS(r300);
815
816 if (!r300screen->caps->has_tcl) {
817 debug_printf("r300: Implementation error: emit_vertex_shader called,"
818 " but has_tcl is FALSE!\n");
819 return;
820 }
821
822 BEGIN_CS(9 + code->length);
823 /* R300_VAP_PVS_CODE_CNTL_0
824 * R300_VAP_PVS_CONST_CNTL
825 * R300_VAP_PVS_CODE_CNTL_1
826 * See the r5xx docs for instructions on how to use these. */
827 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
828 OUT_CS(R300_PVS_FIRST_INST(0) |
829 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
830 R300_PVS_LAST_INST(instruction_count - 1));
831 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
832 OUT_CS(instruction_count - 1);
833
834 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
835 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
836 for (i = 0; i < code->length; i++)
837 OUT_CS(code->body.d[i]);
838
839 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
840 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
841 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
842 R300_PVS_VF_MAX_VTX_NUM(12) |
843 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
844 END_CS;
845 }
846
847 void r300_emit_vertex_shader(struct r300_context* r300,
848 struct r300_vertex_shader* vs)
849 {
850 r300_emit_vertex_program_code(r300, &vs->code);
851 }
852
853 void r300_emit_vs_constant_buffer(struct r300_context* r300,
854 struct rc_constant_list* constants)
855 {
856 int i;
857 struct r300_screen* r300screen = r300_screen(r300->context.screen);
858 CS_LOCALS(r300);
859
860 if (!r300screen->caps->has_tcl) {
861 debug_printf("r300: Implementation error: emit_vertex_shader called,"
862 " but has_tcl is FALSE!\n");
863 return;
864 }
865
866 if (constants->Count == 0)
867 return;
868
869 BEGIN_CS(constants->Count * 4 + 3);
870 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
871 (r300screen->caps->is_r500 ?
872 R500_PVS_CONST_START : R300_PVS_CONST_START));
873 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
874 for (i = 0; i < constants->Count; i++) {
875 const float * data = get_shader_constant(r300,
876 &constants->Constants[i],
877 &r300->shader_constants[PIPE_SHADER_VERTEX]);
878 OUT_CS_32F(data[0]);
879 OUT_CS_32F(data[1]);
880 OUT_CS_32F(data[2]);
881 OUT_CS_32F(data[3]);
882 }
883 END_CS;
884 }
885
886 void r300_emit_viewport_state(struct r300_context* r300,
887 struct r300_viewport_state* viewport)
888 {
889 CS_LOCALS(r300);
890
891 BEGIN_CS(9);
892 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
893 OUT_CS_32F(viewport->xscale);
894 OUT_CS_32F(viewport->xoffset);
895 OUT_CS_32F(viewport->yscale);
896 OUT_CS_32F(viewport->yoffset);
897 OUT_CS_32F(viewport->zscale);
898 OUT_CS_32F(viewport->zoffset);
899
900 if (r300->rs_state->enable_vte) {
901 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
902 } else {
903 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
904 }
905 END_CS;
906 }
907
908 void r300_emit_texture_count(struct r300_context* r300)
909 {
910 uint32_t tx_enable = 0;
911 int i;
912 CS_LOCALS(r300);
913
914 /* Notice that texture_count and sampler_count are just sizes
915 * of the respective arrays. We still have to check for the individual
916 * elements. */
917 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
918 if (r300->textures[i]) {
919 tx_enable |= 1 << i;
920 }
921 }
922
923 BEGIN_CS(2);
924 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
925 END_CS;
926
927 }
928
929 void r300_flush_textures(struct r300_context* r300)
930 {
931 CS_LOCALS(r300);
932
933 BEGIN_CS(2);
934 OUT_CS_REG(R300_TX_INVALTAGS, 0);
935 END_CS;
936 }
937
938 static void r300_flush_pvs(struct r300_context* r300)
939 {
940 CS_LOCALS(r300);
941
942 BEGIN_CS(2);
943 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
944 END_CS;
945 }
946
947 /* Emit all dirty state. */
948 void r300_emit_dirty_state(struct r300_context* r300)
949 {
950 struct r300_screen* r300screen = r300_screen(r300->context.screen);
951 struct r300_texture* tex;
952 int i, dirty_tex = 0;
953 boolean invalid = FALSE;
954
955 if (!(r300->dirty_state)) {
956 return;
957 }
958
959 /* Check size of CS. */
960 /* Make sure we have at least 8*1024 spare dwords. */
961 /* XXX It would be nice to know the number of dwords we really need to
962 * XXX emit. */
963 if (!r300->winsys->check_cs(r300->winsys, 8*1024)) {
964 r300->context.flush(&r300->context, 0, NULL);
965 }
966
967 /* Clean out BOs. */
968 r300->winsys->reset_bos(r300->winsys);
969
970 validate:
971 /* Color buffers... */
972 for (i = 0; i < r300->framebuffer_state.nr_cbufs; i++) {
973 tex = (struct r300_texture*)r300->framebuffer_state.cbufs[i]->texture;
974 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
975 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
976 0, RADEON_GEM_DOMAIN_VRAM)) {
977 r300->context.flush(&r300->context, 0, NULL);
978 goto validate;
979 }
980 }
981 /* ...depth buffer... */
982 if (r300->framebuffer_state.zsbuf) {
983 tex = (struct r300_texture*)r300->framebuffer_state.zsbuf->texture;
984 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
985 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
986 0, RADEON_GEM_DOMAIN_VRAM)) {
987 r300->context.flush(&r300->context, 0, NULL);
988 goto validate;
989 }
990 }
991 /* ...textures... */
992 for (i = 0; i < r300->texture_count; i++) {
993 tex = r300->textures[i];
994 if (!tex)
995 continue;
996 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
997 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
998 r300->context.flush(&r300->context, 0, NULL);
999 goto validate;
1000 }
1001 }
1002 /* ...occlusion query buffer... */
1003 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1004 0, RADEON_GEM_DOMAIN_GTT)) {
1005 r300->context.flush(&r300->context, 0, NULL);
1006 goto validate;
1007 }
1008 /* ...and vertex buffer. */
1009 if (r300->vbo) {
1010 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1011 RADEON_GEM_DOMAIN_GTT, 0)) {
1012 r300->context.flush(&r300->context, 0, NULL);
1013 goto validate;
1014 }
1015 } else {
1016 /* debug_printf("No VBO while emitting dirty state!\n"); */
1017 }
1018 if (!r300->winsys->validate(r300->winsys)) {
1019 r300->context.flush(&r300->context, 0, NULL);
1020 if (invalid) {
1021 /* Well, hell. */
1022 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1023 exit(1);
1024 }
1025 invalid = TRUE;
1026 goto validate;
1027 }
1028
1029 if (r300->dirty_state & R300_NEW_QUERY) {
1030 r300_emit_query_start(r300);
1031 r300->dirty_state &= ~R300_NEW_QUERY;
1032 }
1033
1034 if (r300->dirty_state & R300_NEW_BLEND) {
1035 r300_emit_blend_state(r300, r300->blend_state);
1036 r300->dirty_state &= ~R300_NEW_BLEND;
1037 }
1038
1039 if (r300->dirty_state & R300_NEW_BLEND_COLOR) {
1040 r300_emit_blend_color_state(r300, r300->blend_color_state);
1041 r300->dirty_state &= ~R300_NEW_BLEND_COLOR;
1042 }
1043
1044 if (r300->dirty_state & R300_NEW_CLIP) {
1045 r300_emit_clip_state(r300, &r300->clip_state);
1046 r300->dirty_state &= ~R300_NEW_CLIP;
1047 }
1048
1049 if (r300->dirty_state & R300_NEW_DSA) {
1050 r300_emit_dsa_state(r300, r300->dsa_state);
1051 r300->dirty_state &= ~R300_NEW_DSA;
1052 }
1053
1054 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1055 r300_emit_fragment_depth_config(r300, r300->fs);
1056 if (r300screen->caps->is_r500) {
1057 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1058 } else {
1059 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1060 }
1061 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1062 }
1063
1064 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1065 if (r300screen->caps->is_r500) {
1066 r500_emit_fs_constant_buffer(r300,
1067 &r300->fs->shader->code.constants);
1068 } else {
1069 r300_emit_fs_constant_buffer(r300,
1070 &r300->fs->shader->code.constants);
1071 }
1072 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1073 }
1074
1075 if (r300->dirty_state & R300_NEW_FRAMEBUFFERS) {
1076 r300_emit_fb_state(r300, &r300->framebuffer_state);
1077 r300->dirty_state &= ~R300_NEW_FRAMEBUFFERS;
1078 }
1079
1080 if (r300->dirty_state & R300_NEW_RASTERIZER) {
1081 r300_emit_rs_state(r300, r300->rs_state);
1082 r300->dirty_state &= ~R300_NEW_RASTERIZER;
1083 }
1084
1085 if (r300->dirty_state & R300_NEW_RS_BLOCK) {
1086 r300_emit_rs_block_state(r300, r300->rs_block);
1087 r300->dirty_state &= ~R300_NEW_RS_BLOCK;
1088 }
1089
1090 if (r300->dirty_state & R300_NEW_SCISSOR) {
1091 r300_emit_scissor_state(r300, r300->scissor_state);
1092 r300->dirty_state &= ~R300_NEW_SCISSOR;
1093 }
1094
1095 /* Samplers and textures are tracked separately but emitted together. */
1096 if (r300->dirty_state &
1097 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1098 r300_emit_texture_count(r300);
1099
1100 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1101 if (r300->dirty_state &
1102 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1103 if (r300->textures[i])
1104 r300_emit_texture(r300,
1105 r300->sampler_states[i],
1106 r300->textures[i],
1107 i);
1108 r300->dirty_state &=
1109 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1110 dirty_tex++;
1111 }
1112 }
1113 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1114 }
1115
1116 if (r300->dirty_state & R300_NEW_VIEWPORT) {
1117 r300_emit_viewport_state(r300, r300->viewport_state);
1118 r300->dirty_state &= ~R300_NEW_VIEWPORT;
1119 }
1120
1121 if (dirty_tex) {
1122 r300_flush_textures(r300);
1123 }
1124
1125 if (r300->dirty_state & R300_NEW_VERTEX_FORMAT) {
1126 r300_emit_vertex_format_state(r300);
1127 r300->dirty_state &= ~R300_NEW_VERTEX_FORMAT;
1128 }
1129
1130 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1131 r300_flush_pvs(r300);
1132 }
1133
1134 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1135 r300_emit_vertex_shader(r300, r300->vs);
1136 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1137 }
1138
1139 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1140 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1141 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1142 }
1143
1144 /* XXX
1145 assert(r300->dirty_state == 0);
1146 */
1147
1148 /* Finally, emit the VBO. */
1149 /* r300_emit_vertex_buffer(r300); */
1150
1151 r300->dirty_hw++;
1152 }