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gallium: make max_anisotropy a unsigned bitfield member
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_state_inlines.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300, void* state)
39 {
40 struct r300_blend_state* blend = (struct r300_blend_state*)state;
41 struct pipe_framebuffer_state* fb =
42 (struct pipe_framebuffer_state*)r300->fb_state.state;
43 CS_LOCALS(r300);
44
45 BEGIN_CS(8);
46 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
47 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
48 if (fb->nr_cbufs) {
49 OUT_CS(blend->blend_control);
50 OUT_CS(blend->alpha_blend_control);
51 OUT_CS(blend->color_channel_mask);
52 } else {
53 OUT_CS(0);
54 OUT_CS(0);
55 OUT_CS(0);
56 /* XXX also disable fastfill here once it's supported */
57 }
58 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
59 END_CS;
60 }
61
62 void r300_emit_blend_color_state(struct r300_context* r300, void* state)
63 {
64 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
65 struct r300_screen* r300screen = r300_screen(r300->context.screen);
66 CS_LOCALS(r300);
67
68 if (r300screen->caps->is_r500) {
69 BEGIN_CS(3);
70 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
71 OUT_CS(bc->blend_color_red_alpha);
72 OUT_CS(bc->blend_color_green_blue);
73 END_CS;
74 } else {
75 BEGIN_CS(2);
76 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
77 END_CS;
78 }
79 }
80
81 void r300_emit_clip_state(struct r300_context* r300, void* state)
82 {
83 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
84 int i;
85 struct r300_screen* r300screen = r300_screen(r300->context.screen);
86 CS_LOCALS(r300);
87
88 if (r300screen->caps->has_tcl) {
89 BEGIN_CS(5 + (6 * 4));
90 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
91 (r300screen->caps->is_r500 ?
92 R500_PVS_UCP_START : R300_PVS_UCP_START));
93 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
94 for (i = 0; i < 6; i++) {
95 OUT_CS_32F(clip->ucp[i][0]);
96 OUT_CS_32F(clip->ucp[i][1]);
97 OUT_CS_32F(clip->ucp[i][2]);
98 OUT_CS_32F(clip->ucp[i][3]);
99 }
100 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
101 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
102 END_CS;
103 } else {
104 BEGIN_CS(2);
105 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
106 END_CS;
107 }
108
109 }
110
111 void r300_emit_dsa_state(struct r300_context* r300, void* state)
112 {
113 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
114 struct r300_screen* r300screen = r300_screen(r300->context.screen);
115 struct pipe_framebuffer_state* fb =
116 (struct pipe_framebuffer_state*)r300->fb_state.state;
117 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
118 CS_LOCALS(r300);
119
120 BEGIN_CS(r300screen->caps->is_r500 ? 8 : 6);
121 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
122 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
123
124 if (fb->zsbuf) {
125 OUT_CS(dsa->z_buffer_control);
126 OUT_CS(dsa->z_stencil_control);
127 } else {
128 OUT_CS(0);
129 OUT_CS(0);
130 }
131
132 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
133
134 if (r300screen->caps->is_r500) {
135 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
136 }
137 END_CS;
138 }
139
140 static const float * get_shader_constant(
141 struct r300_context * r300,
142 struct rc_constant * constant,
143 struct r300_constant_buffer * externals)
144 {
145 struct r300_viewport_state* viewport =
146 (struct r300_viewport_state*)r300->viewport_state.state;
147 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
148 struct pipe_texture *tex;
149
150 switch(constant->Type) {
151 case RC_CONSTANT_EXTERNAL:
152 return externals->constants[constant->u.External];
153
154 case RC_CONSTANT_IMMEDIATE:
155 return constant->u.Immediate;
156
157 case RC_CONSTANT_STATE:
158 switch (constant->u.State[0]) {
159 /* Factor for converting rectangle coords to
160 * normalized coords. Should only show up on non-r500. */
161 case RC_STATE_R300_TEXRECT_FACTOR:
162 tex = &r300->textures[constant->u.State[1]]->tex;
163 vec[0] = 1.0 / tex->width0;
164 vec[1] = 1.0 / tex->height0;
165 break;
166
167 /* Texture compare-fail value. Shouldn't ever show up, but if
168 * it does, we'll be ready. */
169 case RC_STATE_SHADOW_AMBIENT:
170 vec[3] = 0;
171 break;
172
173 case RC_STATE_R300_VIEWPORT_SCALE:
174 if (r300->tcl_bypass) {
175 vec[0] = 1;
176 vec[1] = 1;
177 vec[2] = 1;
178 } else {
179 vec[0] = viewport->xscale;
180 vec[1] = viewport->yscale;
181 vec[2] = viewport->zscale;
182 }
183 break;
184
185 case RC_STATE_R300_VIEWPORT_OFFSET:
186 if (!r300->tcl_bypass) {
187 vec[0] = viewport->xoffset;
188 vec[1] = viewport->yoffset;
189 vec[2] = viewport->zoffset;
190 }
191 break;
192
193 default:
194 debug_printf("r300: Implementation error: "
195 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
196 }
197 break;
198
199 default:
200 debug_printf("r300: Implementation error: "
201 "Unhandled constant type %d\n", constant->Type);
202 }
203
204 /* This should either be (0, 0, 0, 1), which should be a relatively safe
205 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
206 * state factors. */
207 return vec;
208 }
209
210 /* Convert a normal single-precision float into the 7.16 format
211 * used by the R300 fragment shader.
212 */
213 static uint32_t pack_float24(float f)
214 {
215 union {
216 float fl;
217 uint32_t u;
218 } u;
219 float mantissa;
220 int exponent;
221 uint32_t float24 = 0;
222
223 if (f == 0.0)
224 return 0;
225
226 u.fl = f;
227
228 mantissa = frexpf(f, &exponent);
229
230 /* Handle -ve */
231 if (mantissa < 0) {
232 float24 |= (1 << 23);
233 mantissa = mantissa * -1.0;
234 }
235 /* Handle exponent, bias of 63 */
236 exponent += 62;
237 float24 |= (exponent << 16);
238 /* Kill 7 LSB of mantissa */
239 float24 |= (u.u & 0x7FFFFF) >> 7;
240
241 return float24;
242 }
243
244 void r300_emit_fragment_program_code(struct r300_context* r300,
245 struct rX00_fragment_program_code* generic_code)
246 {
247 struct r300_fragment_program_code * code = &generic_code->code.r300;
248 int i;
249 CS_LOCALS(r300);
250
251 BEGIN_CS(15 +
252 code->alu.length * 4 +
253 (code->tex.length ? (1 + code->tex.length) : 0));
254
255 OUT_CS_REG(R300_US_CONFIG, code->config);
256 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
257 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
258
259 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
260 for(i = 0; i < 4; ++i)
261 OUT_CS(code->code_addr[i]);
262
263 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
264 for (i = 0; i < code->alu.length; i++)
265 OUT_CS(code->alu.inst[i].rgb_inst);
266
267 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
268 for (i = 0; i < code->alu.length; i++)
269 OUT_CS(code->alu.inst[i].rgb_addr);
270
271 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
272 for (i = 0; i < code->alu.length; i++)
273 OUT_CS(code->alu.inst[i].alpha_inst);
274
275 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
276 for (i = 0; i < code->alu.length; i++)
277 OUT_CS(code->alu.inst[i].alpha_addr);
278
279 if (code->tex.length) {
280 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
281 for(i = 0; i < code->tex.length; ++i)
282 OUT_CS(code->tex.inst[i]);
283 }
284
285 END_CS;
286 }
287
288 void r300_emit_fs_constant_buffer(struct r300_context* r300,
289 struct rc_constant_list* constants)
290 {
291 int i;
292 CS_LOCALS(r300);
293
294 if (constants->Count == 0)
295 return;
296
297 BEGIN_CS(constants->Count * 4 + 1);
298 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
299 for(i = 0; i < constants->Count; ++i) {
300 const float * data = get_shader_constant(r300,
301 &constants->Constants[i],
302 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
303 OUT_CS(pack_float24(data[0]));
304 OUT_CS(pack_float24(data[1]));
305 OUT_CS(pack_float24(data[2]));
306 OUT_CS(pack_float24(data[3]));
307 }
308 END_CS;
309 }
310
311 static void r300_emit_fragment_depth_config(struct r300_context* r300,
312 struct r300_fragment_shader* fs)
313 {
314 CS_LOCALS(r300);
315
316 BEGIN_CS(4);
317 if (r300_fragment_shader_writes_depth(fs)) {
318 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
319 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
320 } else {
321 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
322 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
323 }
324 END_CS;
325 }
326
327 void r500_emit_fragment_program_code(struct r300_context* r300,
328 struct rX00_fragment_program_code* generic_code)
329 {
330 struct r500_fragment_program_code * code = &generic_code->code.r500;
331 int i;
332 CS_LOCALS(r300);
333
334 BEGIN_CS(13 +
335 ((code->inst_end + 1) * 6));
336 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
337 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
338 OUT_CS_REG(R500_US_CODE_RANGE,
339 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
340 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
341 OUT_CS_REG(R500_US_CODE_ADDR,
342 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
343
344 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
345 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
346 for (i = 0; i <= code->inst_end; i++) {
347 OUT_CS(code->inst[i].inst0);
348 OUT_CS(code->inst[i].inst1);
349 OUT_CS(code->inst[i].inst2);
350 OUT_CS(code->inst[i].inst3);
351 OUT_CS(code->inst[i].inst4);
352 OUT_CS(code->inst[i].inst5);
353 }
354
355 END_CS;
356 }
357
358 void r500_emit_fs_constant_buffer(struct r300_context* r300,
359 struct rc_constant_list* constants)
360 {
361 int i;
362 CS_LOCALS(r300);
363
364 if (constants->Count == 0)
365 return;
366
367 BEGIN_CS(constants->Count * 4 + 3);
368 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
369 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
370 for (i = 0; i < constants->Count; i++) {
371 const float * data = get_shader_constant(r300,
372 &constants->Constants[i],
373 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
374 OUT_CS_32F(data[0]);
375 OUT_CS_32F(data[1]);
376 OUT_CS_32F(data[2]);
377 OUT_CS_32F(data[3]);
378 }
379 END_CS;
380 }
381
382 void r300_emit_fb_state(struct r300_context* r300, void* state)
383 {
384 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
385 struct r300_texture* tex;
386 struct pipe_surface* surf;
387 int i;
388 CS_LOCALS(r300);
389
390 BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
391 (fb->zsbuf ? 10 : 0) + 6);
392
393 /* Flush and free renderbuffer caches. */
394 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
395 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
396 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
397 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
398 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
399 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
400
401 /* Set the number of colorbuffers. */
402 if (fb->nr_cbufs > 1) {
403 OUT_CS_REG(R300_RB3D_CCTL,
404 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
405 R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE |
406 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
407 } else {
408 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
409 }
410
411 /* Set up colorbuffers. */
412 for (i = 0; i < fb->nr_cbufs; i++) {
413 surf = fb->cbufs[i];
414 tex = (struct r300_texture*)surf->texture;
415 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
416
417 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
418 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
419
420 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
421 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
422 r300_translate_colorformat(tex->tex.format) |
423 R300_COLOR_TILE(tex->macrotile) |
424 R300_COLOR_MICROTILE(tex->microtile),
425 0, RADEON_GEM_DOMAIN_VRAM, 0);
426
427 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i),
428 r300_translate_out_fmt(surf->format));
429 }
430
431 /* Disable unused colorbuffers. */
432 for (; i < 4; i++) {
433 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
434 }
435
436 /* Set up a zbuffer. */
437 if (fb->zsbuf) {
438 surf = fb->zsbuf;
439 tex = (struct r300_texture*)surf->texture;
440 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
441
442 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
443 OUT_CS_RELOC(tex->buffer, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
444
445 OUT_CS_REG(R300_ZB_FORMAT, r300_translate_zsformat(tex->tex.format));
446
447 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
448 OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level] |
449 R300_DEPTHMACROTILE(tex->macrotile) |
450 R300_DEPTHMICROTILE(tex->microtile),
451 0, RADEON_GEM_DOMAIN_VRAM, 0);
452 }
453
454 END_CS;
455 }
456
457 static void r300_emit_query_start(struct r300_context *r300)
458 {
459 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
460 struct r300_query *query = r300->query_current;
461 CS_LOCALS(r300);
462
463 if (!query)
464 return;
465
466 BEGIN_CS(4);
467 if (caps->family == CHIP_FAMILY_RV530) {
468 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
469 } else {
470 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
471 }
472 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
473 END_CS;
474 query->begin_emitted = TRUE;
475 }
476
477
478 static void r300_emit_query_finish(struct r300_context *r300,
479 struct r300_query *query)
480 {
481 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
482 CS_LOCALS(r300);
483
484 assert(caps->num_frag_pipes);
485
486 BEGIN_CS(6 * caps->num_frag_pipes + 2);
487 /* I'm not so sure I like this switch, but it's hard to be elegant
488 * when there's so many special cases...
489 *
490 * So here's the basic idea. For each pipe, enable writes to it only,
491 * then put out the relocation for ZPASS_ADDR, taking into account a
492 * 4-byte offset for each pipe. RV380 and older are special; they have
493 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
494 * so there's a chipset cap for that. */
495 switch (caps->num_frag_pipes) {
496 case 4:
497 /* pipe 3 only */
498 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
499 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
500 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
501 0, RADEON_GEM_DOMAIN_GTT, 0);
502 case 3:
503 /* pipe 2 only */
504 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
505 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
506 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
507 0, RADEON_GEM_DOMAIN_GTT, 0);
508 case 2:
509 /* pipe 1 only */
510 /* As mentioned above, accomodate RV380 and older. */
511 OUT_CS_REG(R300_SU_REG_DEST,
512 1 << (caps->high_second_pipe ? 3 : 1));
513 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
514 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
515 0, RADEON_GEM_DOMAIN_GTT, 0);
516 case 1:
517 /* pipe 0 only */
518 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
519 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
520 OUT_CS_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
521 0, RADEON_GEM_DOMAIN_GTT, 0);
522 break;
523 default:
524 debug_printf("r300: Implementation error: Chipset reports %d"
525 " pixel pipes!\n", caps->num_frag_pipes);
526 assert(0);
527 }
528
529 /* And, finally, reset it to normal... */
530 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
531 END_CS;
532 }
533
534 static void rv530_emit_query_single(struct r300_context *r300,
535 struct r300_query *query)
536 {
537 CS_LOCALS(r300);
538
539 BEGIN_CS(8);
540 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
541 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
542 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
543 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
544 END_CS;
545 }
546
547 static void rv530_emit_query_double(struct r300_context *r300,
548 struct r300_query *query)
549 {
550 CS_LOCALS(r300);
551
552 BEGIN_CS(14);
553 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
554 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
555 OUT_CS_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
556 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
557 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
558 OUT_CS_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
559 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
560 END_CS;
561 }
562
563 void r300_emit_query_end(struct r300_context* r300)
564 {
565 struct r300_capabilities *caps = r300_screen(r300->context.screen)->caps;
566 struct r300_query *query = r300->query_current;
567
568 if (!query)
569 return;
570
571 if (query->begin_emitted == FALSE)
572 return;
573
574 if (caps->family == CHIP_FAMILY_RV530) {
575 if (caps->num_z_pipes == 2)
576 rv530_emit_query_double(r300, query);
577 else
578 rv530_emit_query_single(r300, query);
579 } else
580 r300_emit_query_finish(r300, query);
581 }
582
583 void r300_emit_rs_state(struct r300_context* r300, void* state)
584 {
585 struct r300_rs_state* rs = (struct r300_rs_state*)state;
586 float scale, offset;
587 CS_LOCALS(r300);
588
589 BEGIN_CS(18 + (rs->polygon_offset_enable ? 5 : 0));
590 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
591
592 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
593
594 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
595 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX, 2);
596 OUT_CS(rs->point_minmax);
597 OUT_CS(rs->line_control);
598
599 if (rs->polygon_offset_enable) {
600 scale = rs->depth_scale * 12;
601 offset = rs->depth_offset;
602
603 switch (r300->zbuffer_bpp) {
604 case 16:
605 offset *= 4;
606 break;
607 case 24:
608 offset *= 2;
609 break;
610 }
611
612 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
613 OUT_CS_32F(scale);
614 OUT_CS_32F(offset);
615 OUT_CS_32F(scale);
616 OUT_CS_32F(offset);
617 }
618
619 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
620 OUT_CS(rs->polygon_offset_enable);
621 OUT_CS(rs->cull_mode);
622 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
623 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
624 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
625 END_CS;
626 }
627
628 void r300_emit_rs_block_state(struct r300_context* r300, void* state)
629 {
630 struct r300_rs_block* rs = (struct r300_rs_block*)state;
631 unsigned i;
632 struct r300_screen* r300screen = r300_screen(r300->context.screen);
633 CS_LOCALS(r300);
634
635 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
636
637 BEGIN_CS(21);
638 if (r300screen->caps->is_r500) {
639 OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
640 } else {
641 OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
642 }
643 for (i = 0; i < 8; i++) {
644 OUT_CS(rs->ip[i]);
645 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
646 }
647
648 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
649 OUT_CS(rs->count);
650 OUT_CS(rs->inst_count);
651
652 if (r300screen->caps->is_r500) {
653 OUT_CS_REG_SEQ(R500_RS_INST_0, 8);
654 } else {
655 OUT_CS_REG_SEQ(R300_RS_INST_0, 8);
656 }
657 for (i = 0; i < 8; i++) {
658 OUT_CS(rs->inst[i]);
659 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
660 }
661
662 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
663 rs->count, rs->inst_count);
664
665 END_CS;
666 }
667
668 void r300_emit_scissor_state(struct r300_context* r300, void* state)
669 {
670 unsigned minx, miny, maxx, maxy;
671 uint32_t top_left, bottom_right;
672 struct r300_screen* r300screen = r300_screen(r300->context.screen);
673 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
674 struct pipe_framebuffer_state* fb =
675 (struct pipe_framebuffer_state*)r300->fb_state.state;
676 CS_LOCALS(r300);
677
678 minx = miny = 0;
679 maxx = fb->width;
680 maxy = fb->height;
681
682 if (((struct r300_rs_state*)r300->rs_state.state)->rs.scissor) {
683 minx = MAX2(minx, scissor->minx);
684 miny = MAX2(miny, scissor->miny);
685 maxx = MIN2(maxx, scissor->maxx);
686 maxy = MIN2(maxy, scissor->maxy);
687 }
688
689 /* Special case for zero-area scissor.
690 *
691 * We can't allow the variables maxx and maxy to be zero because they are
692 * subtracted from later in the code, which would cause emitting ~0 and
693 * making the kernel checker angry.
694 *
695 * Let's consider we change maxx and maxy to 1, which is effectively
696 * a one-pixel area. We must then change minx and miny to a number which is
697 * greater than 1 to get the zero area back. */
698 if (!maxx || !maxy) {
699 minx = 2;
700 miny = 2;
701 maxx = 1;
702 maxy = 1;
703 }
704
705 if (r300screen->caps->is_r500) {
706 top_left =
707 (minx << R300_SCISSORS_X_SHIFT) |
708 (miny << R300_SCISSORS_Y_SHIFT);
709 bottom_right =
710 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
711 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
712 } else {
713 /* Offset of 1440 in non-R500 chipsets. */
714 top_left =
715 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
716 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
717 bottom_right =
718 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
719 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
720 }
721
722 BEGIN_CS(3);
723 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
724 OUT_CS(top_left);
725 OUT_CS(bottom_right);
726 END_CS;
727 }
728
729 void r300_emit_texture(struct r300_context* r300,
730 struct r300_sampler_state* sampler,
731 struct r300_texture* tex,
732 unsigned offset)
733 {
734 uint32_t filter0 = sampler->filter0;
735 uint32_t format0 = tex->state.format0;
736 unsigned min_level, max_level;
737 CS_LOCALS(r300);
738
739 /* to emulate 1D textures through 2D ones correctly */
740 if (tex->tex.target == PIPE_TEXTURE_1D) {
741 filter0 &= ~R300_TX_WRAP_T_MASK;
742 filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
743 }
744
745 if (tex->is_npot) {
746 /* NPOT textures don't support mip filter, unfortunately.
747 * This prevents incorrect rendering. */
748 filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK;
749 } else {
750 /* determine min/max levels */
751 /* the MAX_MIP level is the largest (finest) one */
752 max_level = MIN2(sampler->max_lod, tex->tex.last_level);
753 min_level = MIN2(sampler->min_lod, max_level);
754 format0 |= R300_TX_NUM_LEVELS(max_level);
755 filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
756 }
757
758 BEGIN_CS(16);
759 OUT_CS_REG(R300_TX_FILTER0_0 + (offset * 4), filter0 |
760 (offset << 28));
761 OUT_CS_REG(R300_TX_FILTER1_0 + (offset * 4), sampler->filter1);
762 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (offset * 4), sampler->border_color);
763
764 OUT_CS_REG(R300_TX_FORMAT0_0 + (offset * 4), format0);
765 OUT_CS_REG(R300_TX_FORMAT1_0 + (offset * 4), tex->state.format1);
766 OUT_CS_REG(R300_TX_FORMAT2_0 + (offset * 4), tex->state.format2);
767 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (offset * 4), 1);
768 OUT_CS_RELOC(tex->buffer,
769 R300_TXO_MACRO_TILE(tex->macrotile) |
770 R300_TXO_MICRO_TILE(tex->microtile),
771 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
772 END_CS;
773 }
774
775 void r300_emit_aos(struct r300_context* r300, unsigned offset)
776 {
777 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
778 struct pipe_vertex_element *velem = r300->vertex_element;
779 int i;
780 unsigned size1, size2, aos_count = r300->vertex_element_count;
781 unsigned packet_size = (aos_count * 3 + 1) / 2;
782 CS_LOCALS(r300);
783
784 BEGIN_CS(2 + packet_size + aos_count * 2);
785 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
786 OUT_CS(aos_count);
787
788 for (i = 0; i < aos_count - 1; i += 2) {
789 vb1 = &vbuf[velem[i].vertex_buffer_index];
790 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
791 size1 = util_format_get_blocksize(velem[i].src_format);
792 size2 = util_format_get_blocksize(velem[i+1].src_format);
793
794 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
795 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
796 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
797 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
798 }
799
800 if (aos_count & 1) {
801 vb1 = &vbuf[velem[i].vertex_buffer_index];
802 size1 = util_format_get_blocksize(velem[i].src_format);
803
804 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
805 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
806 }
807
808 for (i = 0; i < aos_count; i++) {
809 OUT_CS_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
810 RADEON_GEM_DOMAIN_GTT, 0, 0);
811 }
812 END_CS;
813 }
814
815 void r300_emit_vertex_format_state(struct r300_context* r300, void* state)
816 {
817 struct r300_vertex_info* vertex_info = (struct r300_vertex_info*)state;
818 unsigned i;
819 CS_LOCALS(r300);
820
821 DBG(r300, DBG_DRAW, "r300: VAP/PSC emit:\n");
822
823 BEGIN_CS(26);
824 OUT_CS_REG(R300_VAP_VTX_SIZE, vertex_info->vinfo.size);
825
826 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
827 OUT_CS(vertex_info->vinfo.hwfmt[0]);
828 OUT_CS(vertex_info->vinfo.hwfmt[1]);
829 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
830 OUT_CS(vertex_info->vinfo.hwfmt[2]);
831 OUT_CS(vertex_info->vinfo.hwfmt[3]);
832 for (i = 0; i < 4; i++) {
833 DBG(r300, DBG_DRAW, " : hwfmt%d: 0x%08x\n", i,
834 vertex_info->vinfo.hwfmt[i]);
835 }
836
837 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 8);
838 for (i = 0; i < 8; i++) {
839 OUT_CS(vertex_info->vap_prog_stream_cntl[i]);
840 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
841 vertex_info->vap_prog_stream_cntl[i]);
842 }
843 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, 8);
844 for (i = 0; i < 8; i++) {
845 OUT_CS(vertex_info->vap_prog_stream_cntl_ext[i]);
846 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
847 vertex_info->vap_prog_stream_cntl_ext[i]);
848 }
849 END_CS;
850 }
851
852
853 void r300_emit_vertex_program_code(struct r300_context* r300,
854 struct r300_vertex_program_code* code)
855 {
856 int i;
857 struct r300_screen* r300screen = r300_screen(r300->context.screen);
858 unsigned instruction_count = code->length / 4;
859
860 int vtx_mem_size = r300screen->caps->is_r500 ? 128 : 72;
861 int input_count = MAX2(util_bitcount(code->InputsRead), 1);
862 int output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
863 int temp_count = MAX2(code->num_temporaries, 1);
864 int pvs_num_slots = MIN3(vtx_mem_size / input_count,
865 vtx_mem_size / output_count, 10);
866 int pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
867
868 CS_LOCALS(r300);
869
870 if (!r300screen->caps->has_tcl) {
871 debug_printf("r300: Implementation error: emit_vertex_shader called,"
872 " but has_tcl is FALSE!\n");
873 return;
874 }
875
876 BEGIN_CS(9 + code->length);
877 /* R300_VAP_PVS_CODE_CNTL_0
878 * R300_VAP_PVS_CONST_CNTL
879 * R300_VAP_PVS_CODE_CNTL_1
880 * See the r5xx docs for instructions on how to use these. */
881 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
882 OUT_CS(R300_PVS_FIRST_INST(0) |
883 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
884 R300_PVS_LAST_INST(instruction_count - 1));
885 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
886 OUT_CS(instruction_count - 1);
887
888 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
889 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
890 for (i = 0; i < code->length; i++)
891 OUT_CS(code->body.d[i]);
892
893 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
894 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
895 R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
896 R300_PVS_VF_MAX_VTX_NUM(12) |
897 (r300screen->caps->is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
898 END_CS;
899 }
900
901 void r300_emit_vertex_shader(struct r300_context* r300,
902 struct r300_vertex_shader* vs)
903 {
904 r300_emit_vertex_program_code(r300, &vs->code);
905 }
906
907 void r300_emit_vs_constant_buffer(struct r300_context* r300,
908 struct rc_constant_list* constants)
909 {
910 int i;
911 struct r300_screen* r300screen = r300_screen(r300->context.screen);
912 CS_LOCALS(r300);
913
914 if (!r300screen->caps->has_tcl) {
915 debug_printf("r300: Implementation error: emit_vertex_shader called,"
916 " but has_tcl is FALSE!\n");
917 return;
918 }
919
920 if (constants->Count == 0)
921 return;
922
923 BEGIN_CS(constants->Count * 4 + 3);
924 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
925 (r300screen->caps->is_r500 ?
926 R500_PVS_CONST_START : R300_PVS_CONST_START));
927 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
928 for (i = 0; i < constants->Count; i++) {
929 const float * data = get_shader_constant(r300,
930 &constants->Constants[i],
931 &r300->shader_constants[PIPE_SHADER_VERTEX]);
932 OUT_CS_32F(data[0]);
933 OUT_CS_32F(data[1]);
934 OUT_CS_32F(data[2]);
935 OUT_CS_32F(data[3]);
936 }
937 END_CS;
938 }
939
940 void r300_emit_viewport_state(struct r300_context* r300, void* state)
941 {
942 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
943 CS_LOCALS(r300);
944
945 if (r300->tcl_bypass) {
946 BEGIN_CS(2);
947 OUT_CS_REG(R300_VAP_VTE_CNTL, 0);
948 END_CS;
949 } else {
950 BEGIN_CS(9);
951 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
952 OUT_CS_32F(viewport->xscale);
953 OUT_CS_32F(viewport->xoffset);
954 OUT_CS_32F(viewport->yscale);
955 OUT_CS_32F(viewport->yoffset);
956 OUT_CS_32F(viewport->zscale);
957 OUT_CS_32F(viewport->zoffset);
958 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
959 END_CS;
960 }
961 }
962
963 void r300_emit_texture_count(struct r300_context* r300)
964 {
965 uint32_t tx_enable = 0;
966 int i;
967 CS_LOCALS(r300);
968
969 /* Notice that texture_count and sampler_count are just sizes
970 * of the respective arrays. We still have to check for the individual
971 * elements. */
972 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
973 if (r300->textures[i]) {
974 tx_enable |= 1 << i;
975 }
976 }
977
978 BEGIN_CS(2);
979 OUT_CS_REG(R300_TX_ENABLE, tx_enable);
980 END_CS;
981
982 }
983
984 void r300_emit_ztop_state(struct r300_context* r300, void* state)
985 {
986 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
987 CS_LOCALS(r300);
988
989 BEGIN_CS(2);
990 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
991 END_CS;
992 }
993
994 void r300_flush_textures(struct r300_context* r300)
995 {
996 CS_LOCALS(r300);
997
998 BEGIN_CS(2);
999 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1000 END_CS;
1001 }
1002
1003 static void r300_flush_pvs(struct r300_context* r300)
1004 {
1005 CS_LOCALS(r300);
1006
1007 BEGIN_CS(2);
1008 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
1009 END_CS;
1010 }
1011
1012 void r300_emit_buffer_validate(struct r300_context *r300)
1013 {
1014 struct pipe_framebuffer_state* fb =
1015 (struct pipe_framebuffer_state*)r300->fb_state.state;
1016 struct r300_texture* tex;
1017 unsigned i;
1018 boolean invalid = FALSE;
1019
1020 /* Clean out BOs. */
1021 r300->winsys->reset_bos(r300->winsys);
1022
1023 validate:
1024 /* Color buffers... */
1025 for (i = 0; i < fb->nr_cbufs; i++) {
1026 tex = (struct r300_texture*)fb->cbufs[i]->texture;
1027 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1028 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1029 0, RADEON_GEM_DOMAIN_VRAM)) {
1030 r300->context.flush(&r300->context, 0, NULL);
1031 goto validate;
1032 }
1033 }
1034 /* ...depth buffer... */
1035 if (fb->zsbuf) {
1036 tex = (struct r300_texture*)fb->zsbuf->texture;
1037 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1038 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1039 0, RADEON_GEM_DOMAIN_VRAM)) {
1040 r300->context.flush(&r300->context, 0, NULL);
1041 goto validate;
1042 }
1043 }
1044 /* ...textures... */
1045 for (i = 0; i < r300->texture_count; i++) {
1046 tex = r300->textures[i];
1047 if (!tex)
1048 continue;
1049 if (!r300->winsys->add_buffer(r300->winsys, tex->buffer,
1050 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1051 r300->context.flush(&r300->context, 0, NULL);
1052 goto validate;
1053 }
1054 }
1055 /* ...occlusion query buffer... */
1056 if (r300->dirty_state & R300_NEW_QUERY) {
1057 if (!r300->winsys->add_buffer(r300->winsys, r300->oqbo,
1058 0, RADEON_GEM_DOMAIN_GTT)) {
1059 r300->context.flush(&r300->context, 0, NULL);
1060 goto validate;
1061 }
1062 }
1063 /* ...and vertex buffer. */
1064 if (r300->vbo) {
1065 if (!r300->winsys->add_buffer(r300->winsys, r300->vbo,
1066 RADEON_GEM_DOMAIN_GTT, 0)) {
1067 r300->context.flush(&r300->context, 0, NULL);
1068 goto validate;
1069 }
1070 } else {
1071 /* debug_printf("No VBO while emitting dirty state!\n"); */
1072 }
1073 if (!r300->winsys->validate(r300->winsys)) {
1074 r300->context.flush(&r300->context, 0, NULL);
1075 if (invalid) {
1076 /* Well, hell. */
1077 debug_printf("r300: Stuck in validation loop, gonna quit now.");
1078 exit(1);
1079 }
1080 invalid = TRUE;
1081 goto validate;
1082 }
1083 }
1084
1085 /* Emit all dirty state. */
1086 void r300_emit_dirty_state(struct r300_context* r300)
1087 {
1088 struct r300_screen* r300screen = r300_screen(r300->context.screen);
1089 struct r300_atom* atom;
1090 unsigned i, dwords = 1024;
1091 int dirty_tex = 0;
1092
1093 /* Check the required number of dwords against the space remaining in the
1094 * current CS object. If we need more, then flush. */
1095
1096 foreach(atom, &r300->atom_list) {
1097 if (atom->dirty || atom->always_dirty) {
1098 dwords += atom->size;
1099 }
1100 }
1101
1102 /* Make sure we have at least 2*1024 spare dwords. */
1103 /* XXX It would be nice to know the number of dwords we really need to
1104 * XXX emit. */
1105 while (!r300->winsys->check_cs(r300->winsys, dwords)) {
1106 r300->context.flush(&r300->context, 0, NULL);
1107 }
1108
1109 if (r300->dirty_state & R300_NEW_QUERY) {
1110 r300_emit_query_start(r300);
1111 r300->dirty_state &= ~R300_NEW_QUERY;
1112 }
1113
1114 foreach(atom, &r300->atom_list) {
1115 if (atom->dirty || atom->always_dirty) {
1116 atom->emit(r300, atom->state);
1117 atom->dirty = FALSE;
1118 }
1119 }
1120
1121 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1122 r300_emit_fragment_depth_config(r300, r300->fs);
1123 if (r300screen->caps->is_r500) {
1124 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1125 } else {
1126 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1127 }
1128 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1129 }
1130
1131 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1132 if (r300screen->caps->is_r500) {
1133 r500_emit_fs_constant_buffer(r300,
1134 &r300->fs->shader->code.constants);
1135 } else {
1136 r300_emit_fs_constant_buffer(r300,
1137 &r300->fs->shader->code.constants);
1138 }
1139 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1140 }
1141
1142 /* Samplers and textures are tracked separately but emitted together. */
1143 if (r300->dirty_state &
1144 (R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES)) {
1145 r300_emit_texture_count(r300);
1146
1147 for (i = 0; i < MIN2(r300->sampler_count, r300->texture_count); i++) {
1148 if (r300->dirty_state &
1149 ((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i))) {
1150 if (r300->textures[i])
1151 r300_emit_texture(r300,
1152 r300->sampler_states[i],
1153 r300->textures[i],
1154 i);
1155 r300->dirty_state &=
1156 ~((R300_NEW_SAMPLER << i) | (R300_NEW_TEXTURE << i));
1157 dirty_tex++;
1158 }
1159 }
1160 r300->dirty_state &= ~(R300_ANY_NEW_SAMPLERS | R300_ANY_NEW_TEXTURES);
1161 }
1162
1163 if (dirty_tex) {
1164 r300_flush_textures(r300);
1165 }
1166
1167 if (r300->dirty_state & (R300_NEW_VERTEX_SHADER | R300_NEW_VERTEX_SHADER_CONSTANTS)) {
1168 r300_flush_pvs(r300);
1169 }
1170
1171 if (r300->dirty_state & R300_NEW_VERTEX_SHADER) {
1172 r300_emit_vertex_shader(r300, r300->vs);
1173 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER;
1174 }
1175
1176 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1177 r300_emit_vs_constant_buffer(r300, &r300->vs->code.constants);
1178 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1179 }
1180
1181 /* XXX
1182 assert(r300->dirty_state == 0);
1183 */
1184
1185 /* Finally, emit the VBO. */
1186 /* r300_emit_vertex_buffer(r300); */
1187
1188 r300->dirty_hw++;
1189 }